MIPS: KVM: Recognise r6 CACHE encoding
Recognise the new MIPSr6 CACHE instruction encoding rather than the pre-r6 one when an r6 kernel is being built. A SPECIAL3 opcode is used and the immediate field is reduced to 9 bits wide since MIPSr6. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim KrÄmář <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -72,7 +72,10 @@ int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
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synci_inst.i_format.opcode = bcond_op;
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synci_inst.i_format.rs = inst.i_format.rs;
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synci_inst.i_format.rt = synci_op;
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synci_inst.i_format.simmediate = inst.i_format.simmediate;
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if (cpu_has_mips_r6)
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synci_inst.i_format.simmediate = inst.spec3_format.simmediate;
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else
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synci_inst.i_format.simmediate = inst.i_format.simmediate;
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return kvm_mips_trans_replace(vcpu, opc, synci_inst);
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}
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@ -1601,7 +1601,10 @@ enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
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base = inst.i_format.rs;
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op_inst = inst.i_format.rt;
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offset = inst.i_format.simmediate;
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if (cpu_has_mips_r6)
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offset = inst.spec3_format.simmediate;
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else
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offset = inst.i_format.simmediate;
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cache = op_inst & CacheOp_Cache;
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op = op_inst & CacheOp_Op;
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@ -1764,11 +1767,27 @@ enum emulation_result kvm_mips_emulate_inst(u32 cause, u32 *opc,
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er = kvm_mips_emulate_load(inst, cause, run, vcpu);
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break;
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#ifndef CONFIG_CPU_MIPSR6
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case cache_op:
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++vcpu->stat.cache_exits;
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trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
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er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu);
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break;
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#else
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case spec3_op:
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switch (inst.spec3_format.func) {
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case cache6_op:
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++vcpu->stat.cache_exits;
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trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
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er = kvm_mips_emulate_cache(inst, opc, cause, run,
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vcpu);
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break;
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default:
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goto unknown;
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};
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break;
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unknown:
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#endif
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default:
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kvm_err("Instruction emulation not supported (%p/%#x)\n", opc,
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