drm/i915: Make the intel_device_info structure kept in dev_priv writable
Turns out it'd be nice to change some device information at run-time or simply
have some code to fill in the info struct instead of having to declare the
values in 30+ structures.
What prompted this change is handling fused out display/pipe and tweaking
num_pipes at run-time, but I'm quite sure we'll find other flags/limits to
stick into dev_priv->info.
Most of the changes were done with a sed:
sed -i -e 's/dev_priv->info->/dev_priv->info./g' drivers/gpu/drm/i915/*[ch]
with a few tweaks to make it all work:
- Change the field definition in struct drm_i915_private
- adjust i915_dump_device_info()
- adjust i915_driver_load()
- adjust the INTEL_INFO() macro
v2: cast the info pointer returned by INTEL_INFO() to be const to catch
uses that would modify the structure post-initialization.
(Ville Syrjälä)
v3: Redo the patch onto latest drm-nightly,
Keep the info field const to catch post initialization writes
instead of the v2 solution,
Use a direct structure copy for the initial info initialization to
use the compiler type safety (Ville Syrjälä)
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> (for v2)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (for v2)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Damien Lespiau
Daniel Vetter
parent
3d13ef2e2d
commit
5c969aa7e1
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@ -1442,7 +1442,7 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
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static void i915_dump_device_info(struct drm_i915_private *dev_priv)
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{
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const struct intel_device_info *info = dev_priv->info;
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const struct intel_device_info *info = &dev_priv->info;
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#define PRINT_S(name) "%s"
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#define SEP_EMPTY
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@ -1473,7 +1473,7 @@ static void i915_dump_device_info(struct drm_i915_private *dev_priv)
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int i915_driver_load(struct drm_device *dev, unsigned long flags)
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{
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struct drm_i915_private *dev_priv;
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struct intel_device_info *info;
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struct intel_device_info *info, *device_info;
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int ret = 0, mmio_bar, mmio_size;
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uint32_t aperture_size;
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@ -1496,7 +1496,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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dev->dev_private = (void *)dev_priv;
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dev_priv->dev = dev;
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dev_priv->info = info;
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/* copy initial configuration to dev_priv->info */
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device_info = (struct intel_device_info *)&dev_priv->info;
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*device_info = *info;
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spin_lock_init(&dev_priv->irq_lock);
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spin_lock_init(&dev_priv->gpu_error.lock);
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@ -1390,7 +1390,7 @@ typedef struct drm_i915_private {
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struct drm_device *dev;
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struct kmem_cache *slab;
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const struct intel_device_info *info;
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const struct intel_device_info info;
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int relative_constants_mode;
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@ -1799,7 +1799,7 @@ struct drm_i915_file_private {
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atomic_t rps_wait_boost;
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};
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#define INTEL_INFO(dev) (to_i915(dev)->info)
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#define INTEL_INFO(dev) (&to_i915(dev)->info)
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#define IS_I830(dev) ((dev)->pdev->device == 0x3577)
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#define IS_845G(dev) ((dev)->pdev->device == 0x2562)
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@ -1205,8 +1205,8 @@
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*/
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#define DPLL_A_OFFSET 0x6014
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#define DPLL_B_OFFSET 0x6018
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#define DPLL(pipe) (dev_priv->info->dpll_offsets[pipe] + \
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dev_priv->info->display_mmio_offset)
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#define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
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dev_priv->info.display_mmio_offset)
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#define VGA0 0x6000
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#define VGA1 0x6004
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@ -1283,8 +1283,8 @@
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#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
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#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
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#define DPLL_MD(pipe) (dev_priv->info->dpll_md_offsets[pipe] + \
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dev_priv->info->display_mmio_offset)
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#define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
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dev_priv->info.display_mmio_offset)
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/*
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* UDI pixel divider, controlling how many pixels are stuffed into a packet.
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@ -1353,7 +1353,7 @@
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#define DSTATE_PLL_D3_OFF (1<<3)
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#define DSTATE_GFX_CLOCK_GATING (1<<1)
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#define DSTATE_DOT_CLOCK_GATING (1<<0)
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#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200)
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#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
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# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
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# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
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# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
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@ -1479,8 +1479,8 @@
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*/
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#define PALETTE_A_OFFSET 0xa000
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#define PALETTE_B_OFFSET 0xa800
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#define PALETTE(pipe) (dev_priv->info->palette_offsets[pipe] + \
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dev_priv->info->display_mmio_offset)
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#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
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dev_priv->info.display_mmio_offset)
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/* MCH MMIO space */
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@ -1970,9 +1970,9 @@
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#define TRANSCODER_C_OFFSET 0x62000
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#define TRANSCODER_EDP_OFFSET 0x6f000
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#define _TRANSCODER2(pipe, reg) (dev_priv->info->trans_offsets[(pipe)] - \
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dev_priv->info->trans_offsets[TRANSCODER_A] + (reg) + \
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dev_priv->info->display_mmio_offset)
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#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
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dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
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dev_priv->info.display_mmio_offset)
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#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
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#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
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@ -2099,7 +2099,7 @@
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/* Hotplug control (945+ only) */
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#define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110)
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#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
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#define PORTB_HOTPLUG_INT_EN (1 << 29)
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#define PORTC_HOTPLUG_INT_EN (1 << 28)
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#define PORTD_HOTPLUG_INT_EN (1 << 27)
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@ -2129,7 +2129,7 @@
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#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
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#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
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#define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114)
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#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
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/*
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* HDMI/DP bits are gen4+
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*
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@ -2406,7 +2406,7 @@
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#define PP_DIVISOR 0x61210
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/* Panel fitting */
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#define PFIT_CONTROL (dev_priv->info->display_mmio_offset + 0x61230)
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#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
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#define PFIT_ENABLE (1 << 31)
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#define PFIT_PIPE_MASK (3 << 29)
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#define PFIT_PIPE_SHIFT 29
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@ -2424,7 +2424,7 @@
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#define PFIT_SCALING_PROGRAMMED (1 << 26)
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#define PFIT_SCALING_PILLAR (2 << 26)
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#define PFIT_SCALING_LETTER (3 << 26)
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#define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234)
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#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
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/* Pre-965 */
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#define PFIT_VERT_SCALE_SHIFT 20
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#define PFIT_VERT_SCALE_MASK 0xfff00000
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@ -2436,25 +2436,25 @@
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#define PFIT_HORIZ_SCALE_SHIFT_965 0
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#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
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#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
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#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
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#define _VLV_BLC_PWM_CTL2_A (dev_priv->info->display_mmio_offset + 0x61250)
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#define _VLV_BLC_PWM_CTL2_B (dev_priv->info->display_mmio_offset + 0x61350)
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#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
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#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
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#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
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_VLV_BLC_PWM_CTL2_B)
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#define _VLV_BLC_PWM_CTL_A (dev_priv->info->display_mmio_offset + 0x61254)
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#define _VLV_BLC_PWM_CTL_B (dev_priv->info->display_mmio_offset + 0x61354)
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#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
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#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
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#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
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_VLV_BLC_PWM_CTL_B)
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#define _VLV_BLC_HIST_CTL_A (dev_priv->info->display_mmio_offset + 0x61260)
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#define _VLV_BLC_HIST_CTL_B (dev_priv->info->display_mmio_offset + 0x61360)
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#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
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#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
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#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
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_VLV_BLC_HIST_CTL_B)
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/* Backlight control */
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#define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */
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#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
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#define BLM_PWM_ENABLE (1 << 31)
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#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
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#define BLM_PIPE_SELECT (1 << 29)
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@ -2477,7 +2477,7 @@
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#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
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#define BLM_PHASE_IN_INCR_SHIFT (0)
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#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
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#define BLC_PWM_CTL (dev_priv->info->display_mmio_offset + 0x61254)
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#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
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/*
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* This is the most significant 15 bits of the number of backlight cycles in a
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* complete cycle of the modulated backlight control.
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@ -2499,7 +2499,7 @@
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#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
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#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
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#define BLC_HIST_CTL (dev_priv->info->display_mmio_offset + 0x61260)
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#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
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/* New registers for PCH-split platforms. Safe where new bits show up, the
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* register layout machtes with gen4 BLC_PWM_CTL[12]. */
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@ -3288,9 +3288,9 @@
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*/
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#define PIPE_EDP_OFFSET 0x7f000
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#define _PIPE2(pipe, reg) (dev_priv->info->pipe_offsets[pipe] - \
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dev_priv->info->pipe_offsets[PIPE_A] + (reg) + \
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dev_priv->info->display_mmio_offset)
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#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
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dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
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dev_priv->info.display_mmio_offset)
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#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
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#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
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@ -3352,7 +3352,7 @@
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#define DSPARB_BEND_SHIFT 9 /* on 855 */
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#define DSPARB_AEND_SHIFT 0
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#define DSPFW1 (dev_priv->info->display_mmio_offset + 0x70034)
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#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
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#define DSPFW_SR_SHIFT 23
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#define DSPFW_SR_MASK (0x1ff<<23)
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#define DSPFW_CURSORB_SHIFT 16
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@ -3360,11 +3360,11 @@
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#define DSPFW_PLANEB_SHIFT 8
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#define DSPFW_PLANEB_MASK (0x7f<<8)
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#define DSPFW_PLANEA_MASK (0x7f)
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#define DSPFW2 (dev_priv->info->display_mmio_offset + 0x70038)
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#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
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#define DSPFW_CURSORA_MASK 0x00003f00
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#define DSPFW_CURSORA_SHIFT 8
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#define DSPFW_PLANEC_MASK (0x7f)
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#define DSPFW3 (dev_priv->info->display_mmio_offset + 0x7003c)
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#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
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#define DSPFW_HPLL_SR_EN (1<<31)
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#define DSPFW_CURSOR_SR_SHIFT 24
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#define PINEVIEW_SELF_REFRESH_EN (1<<30)
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@ -3372,8 +3372,8 @@
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#define DSPFW_HPLL_CURSOR_SHIFT 16
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#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
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#define DSPFW_HPLL_SR_MASK (0x1ff)
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#define DSPFW4 (dev_priv->info->display_mmio_offset + 0x70070)
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#define DSPFW7 (dev_priv->info->display_mmio_offset + 0x7007c)
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#define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070)
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#define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c)
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/* drain latency register values*/
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#define DRAIN_LATENCY_PRECISION_32 32
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#define PIPE_PIXEL_MASK 0x00ffffff
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#define PIPE_PIXEL_SHIFT 0
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/* GM45+ just has to be different */
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#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70040)
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#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70044)
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#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70040)
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#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70044)
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#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
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/* Cursor A & B regs */
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#define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080)
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#define _CURACNTR (dev_priv->info.display_mmio_offset + 0x70080)
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/* Old style CUR*CNTR flags (desktop 8xx) */
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#define CURSOR_ENABLE 0x80000000
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#define CURSOR_GAMMA_ENABLE 0x40000000
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#define MCURSOR_PIPE_B (1 << 28)
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#define MCURSOR_GAMMA_ENABLE (1 << 26)
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#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
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#define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084)
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#define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088)
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#define _CURABASE (dev_priv->info.display_mmio_offset + 0x70084)
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#define _CURAPOS (dev_priv->info.display_mmio_offset + 0x70088)
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#define CURSOR_POS_MASK 0x007FF
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#define CURSOR_POS_SIGN 0x8000
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#define CURSOR_X_SHIFT 0
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#define CURSOR_Y_SHIFT 16
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#define CURSIZE 0x700a0
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#define _CURBCNTR (dev_priv->info->display_mmio_offset + 0x700c0)
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#define _CURBBASE (dev_priv->info->display_mmio_offset + 0x700c4)
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#define _CURBPOS (dev_priv->info->display_mmio_offset + 0x700c8)
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#define _CURBCNTR (dev_priv->info.display_mmio_offset + 0x700c0)
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#define _CURBBASE (dev_priv->info.display_mmio_offset + 0x700c4)
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#define _CURBPOS (dev_priv->info.display_mmio_offset + 0x700c8)
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#define _CURBCNTR_IVB 0x71080
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#define _CURBBASE_IVB 0x71084
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#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
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/* VBIOS flags */
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#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410)
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#define SWF01 (dev_priv->info->display_mmio_offset + 0x71414)
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#define SWF02 (dev_priv->info->display_mmio_offset + 0x71418)
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#define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c)
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#define SWF04 (dev_priv->info->display_mmio_offset + 0x71420)
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#define SWF05 (dev_priv->info->display_mmio_offset + 0x71424)
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#define SWF06 (dev_priv->info->display_mmio_offset + 0x71428)
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#define SWF10 (dev_priv->info->display_mmio_offset + 0x70410)
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#define SWF11 (dev_priv->info->display_mmio_offset + 0x70414)
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#define SWF14 (dev_priv->info->display_mmio_offset + 0x71420)
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#define SWF30 (dev_priv->info->display_mmio_offset + 0x72414)
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#define SWF31 (dev_priv->info->display_mmio_offset + 0x72418)
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#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c)
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#define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
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#define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
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#define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
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#define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
|
||||
#define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
|
||||
#define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
|
||||
#define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
|
||||
#define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
|
||||
#define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
|
||||
#define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
|
||||
#define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
|
||||
#define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
|
||||
#define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
|
||||
|
||||
/* Pipe B */
|
||||
#define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000)
|
||||
#define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008)
|
||||
#define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024)
|
||||
#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
|
||||
#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
|
||||
#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
|
||||
#define _PIPEBFRAMEHIGH 0x71040
|
||||
#define _PIPEBFRAMEPIXEL 0x71044
|
||||
#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71040)
|
||||
#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71044)
|
||||
#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
|
||||
#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
|
||||
|
||||
|
||||
/* Display B control */
|
||||
#define _DSPBCNTR (dev_priv->info->display_mmio_offset + 0x71180)
|
||||
#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
|
||||
#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
|
||||
#define DISPPLANE_ALPHA_TRANS_DISABLE 0
|
||||
#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
|
||||
#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
|
||||
#define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184)
|
||||
#define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188)
|
||||
#define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C)
|
||||
#define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190)
|
||||
#define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C)
|
||||
#define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4)
|
||||
#define _DSPBOFFSET (dev_priv->info->display_mmio_offset + 0x711A4)
|
||||
#define _DSPBSURFLIVE (dev_priv->info->display_mmio_offset + 0x711AC)
|
||||
#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
|
||||
#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
|
||||
#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
|
||||
#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
|
||||
#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
|
||||
#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
|
||||
#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
|
||||
#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
|
||||
|
||||
/* Sprite A control */
|
||||
#define _DVSACNTR 0x72180
|
||||
|
|
@ -5052,7 +5052,7 @@
|
|||
#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
|
||||
#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
|
||||
|
||||
#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020)
|
||||
#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
|
||||
#define INTEL_AUDIO_DEVCL 0x808629FB
|
||||
#define INTEL_AUDIO_DEVBLC 0x80862801
|
||||
#define INTEL_AUDIO_DEVCTG 0x80862802
|
||||
|
|
@ -5905,11 +5905,11 @@
|
|||
#define READ_DATA_VALID(n) (1 << (n))
|
||||
|
||||
/* For UMS only (deprecated): */
|
||||
#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
|
||||
#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
|
||||
#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
|
||||
#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
|
||||
#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c)
|
||||
#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020)
|
||||
#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
|
||||
#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
|
||||
#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
|
||||
#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
|
||||
#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
|
||||
#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
|
||||
|
||||
#endif /* _I915_REG_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue