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drm/nouveau: pass perflvl struct to clock_pre() 

On certain boards, there's BIOS scripts and memory timings that need to
be modified with the memclk.  Just pass in the entire perflvl struct and
let the chipset-specific code decide what to do.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2010-09-27 09:47:56 +10:00
parent fe224bb7e1
commit 5c6dc65754
5 changed files with 17 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/nouveau/nouveau_drv.h
View File

@ -432,7 +432,8 @@ struct nouveau_pm_engine {
struct device *hwmon;
int (*clock_get)(struct drm_device *, u32 id);
void *(*clock_pre)(struct drm_device *, u32 id, int khz);
void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
u32 id, int khz);
void (*clock_set)(struct drm_device *, void *);
int (*voltage_get)(struct drm_device *);
int (*voltage_set)(struct drm_device *, int voltage);

13
drivers/gpu/drm/nouveau/nouveau_pm.c
View File

@ -31,7 +31,8 @@
#include <linux/hwmon-sysfs.h>
static int
nouveau_pm_clock_set(struct drm_device *dev, u8 id, u32 khz)
nouveau_pm_clock_set(struct drm_device *dev, struct nouveau_pm_level *perflvl,
u8 id, u32 khz)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
@ -40,7 +41,7 @@ nouveau_pm_clock_set(struct drm_device *dev, u8 id, u32 khz)
if (khz == 0)
return 0;
pre_state = pm->clock_pre(dev, id, khz);
pre_state = pm->clock_pre(dev, perflvl, id, khz);
if (IS_ERR(pre_state))
return PTR_ERR(pre_state);
@ -67,10 +68,10 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl)
}
}
nouveau_pm_clock_set(dev, PLL_CORE, perflvl->core);
nouveau_pm_clock_set(dev, PLL_SHADER, perflvl->shader);
nouveau_pm_clock_set(dev, PLL_MEMORY, perflvl->memory);
nouveau_pm_clock_set(dev, PLL_UNK05, perflvl->unk05);
nouveau_pm_clock_set(dev, perflvl, PLL_CORE, perflvl->core);
nouveau_pm_clock_set(dev, perflvl, PLL_SHADER, perflvl->shader);
nouveau_pm_clock_set(dev, perflvl, PLL_MEMORY, perflvl->memory);
nouveau_pm_clock_set(dev, perflvl, PLL_UNK05, perflvl->unk05);
pm->cur = perflvl;
return 0;

6
drivers/gpu/drm/nouveau/nouveau_pm.h
View File

@ -48,12 +48,14 @@ void nouveau_mem_timing_fini(struct drm_device *);
/* nv04_pm.c */
int nv04_pm_clock_get(struct drm_device *, u32 id);
void *nv04_pm_clock_pre(struct drm_device *, u32 id, int khz);
void *nv04_pm_clock_pre(struct drm_device *, struct nouveau_pm_level *,
u32 id, int khz);
void nv04_pm_clock_set(struct drm_device *, void *);
/* nv50_pm.c */
int nv50_pm_clock_get(struct drm_device *, u32 id);
void *nv50_pm_clock_pre(struct drm_device *, u32 id, int khz);
void *nv50_pm_clock_pre(struct drm_device *, struct nouveau_pm_level *,
u32 id, int khz);
void nv50_pm_clock_set(struct drm_device *, void *);
/* nouveau_temp.c */

3
drivers/gpu/drm/nouveau/nv04_pm.c
View File

@ -39,7 +39,8 @@ nv04_pm_clock_get(struct drm_device *dev, u32 id)
}
void *
nv04_pm_clock_pre(struct drm_device *dev, u32 id, int khz)
nv04_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
u32 id, int khz)
{
struct nv04_pm_state *state;
int ret;

3
drivers/gpu/drm/nouveau/nv50_pm.c
View File

@ -67,7 +67,8 @@ nv50_pm_clock_get(struct drm_device *dev, u32 id)
}
void *
nv50_pm_clock_pre(struct drm_device *dev, u32 id, int khz)
nv50_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
u32 id, int khz)
{
struct nv50_pm_state *state;
int dummy, ret;