irqchip core changes for v4.5
- renesas-intc-irqpin: Remove platform code, improve clock handling - sunxi-nmi: Extend NMI support to include A80 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJWesk9AAoJEP45WPkGe8ZnHz4QAL0yHVogWn/ggUcMl+B+UF6J 0RhiaVupNM7fvHP8xShqYUTn/f5j4OqkfAjKxN46uaa6a5LcL3Oq9fvZJ2IhYT8u MKoeBfDFLxjQ/ua58xs7tiloXxrk2DMBhm1+w0w7n0HRGQL5OEVX6hC08k/5K3X0 bOUEwU6ICJRzzxYOm9J2tXulfH6iCGurPbojk6x1sefOOeRbo48xIHWZ2wrDKpGD GHpmYA215+kfwibFH5eXojonRVt7R5YvGo9SZD48+NZv0l5CfC3v7QG8IsX0sFID rhwUVYo1LJ5lQlg0GOwRHVORSnTodMmiD7N6+aPJ90H0PrukA4J4CPZJydZfiJMa RXL5c7SDN/tJ0EzITSC63VQ06/kada2/I+w7jJesSAn44M+tyMx3zt5ZPLSU+MXn gpXTyVRQ8p068Eed/c946tz/rFoZJBE0CkpA++cYS3dc1ljPA3vt3CdaeH7AN29T nNW7qkVEQogZwC1Cjs3KXDmfsARlVmKfQ1zfoPftIr6Qh7xkXZL9m9lLJreZbtNj 3FgAoLQG/5WomzuBy46b8iMVfhst8tzL4K29xnMubYn79ir7rfd8JGqP8DZCFyNM IBzTJdDKBp1Digguybev3xfwNqdIOd3dXQwhqRF/TeQhsVuN0EcCeGD+DTdH17h2 4Pt/izUaD64pYeyV9USU =PJ3c -----END PGP SIGNATURE----- Merge tag 'irqchip-core-v4.5' of git://git.infradead.org/users/jcooper/linux into irq/core Pull irqchip core changes for v4.5 from Jason Cooper: - renesas-intc-irqpin: Remove platform code, improve clock handling - sunxi-nmi: Extend NMI support to include A80
This commit is contained in:
Thomas Gleixner
commit
5c4acd97e8
|
|
@ -4,7 +4,7 @@ Allwinner Sunxi NMI Controller
|
|||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
|
||||
"allwinner,sun6i-a31-sc-nmi"
|
||||
"allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
|
|
@ -31,7 +31,6 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
|
||||
|
|
@ -75,18 +74,20 @@ struct intc_irqpin_irq {
|
|||
struct intc_irqpin_priv {
|
||||
struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
|
||||
struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
|
||||
struct renesas_intc_irqpin_config config;
|
||||
unsigned int number_of_irqs;
|
||||
unsigned int sense_bitfield_width;
|
||||
struct platform_device *pdev;
|
||||
struct irq_chip irq_chip;
|
||||
struct irq_domain *irq_domain;
|
||||
struct clk *clk;
|
||||
bool shared_irqs;
|
||||
unsigned shared_irqs:1;
|
||||
unsigned needs_clk:1;
|
||||
u8 shared_irq_mask;
|
||||
};
|
||||
|
||||
struct intc_irqpin_irlm_config {
|
||||
struct intc_irqpin_config {
|
||||
unsigned int irlm_bit;
|
||||
unsigned needs_irlm:1;
|
||||
unsigned needs_clk:1;
|
||||
};
|
||||
|
||||
static unsigned long intc_irqpin_read32(void __iomem *iomem)
|
||||
|
|
@ -171,7 +172,7 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
|
|||
static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
|
||||
{
|
||||
/* The SENSE register is assumed to be 32-bit. */
|
||||
int bitfield_width = p->config.sense_bitfield_width;
|
||||
int bitfield_width = p->sense_bitfield_width;
|
||||
int shift = 32 - (irq + 1) * bitfield_width;
|
||||
|
||||
dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
|
||||
|
|
@ -361,8 +362,15 @@ static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
|
|||
.xlate = irq_domain_xlate_twocell,
|
||||
};
|
||||
|
||||
static const struct intc_irqpin_irlm_config intc_irqpin_irlm_r8a777x = {
|
||||
static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
|
||||
.irlm_bit = 23, /* ICR0.IRLM0 */
|
||||
.needs_irlm = 1,
|
||||
.needs_clk = 0,
|
||||
};
|
||||
|
||||
static const struct intc_irqpin_config intc_irqpin_rmobile = {
|
||||
.needs_irlm = 0,
|
||||
.needs_clk = 1,
|
||||
};
|
||||
|
||||
static const struct of_device_id intc_irqpin_dt_ids[] = {
|
||||
|
|
@ -371,14 +379,18 @@ static const struct of_device_id intc_irqpin_dt_ids[] = {
|
|||
.data = &intc_irqpin_irlm_r8a777x },
|
||||
{ .compatible = "renesas,intc-irqpin-r8a7779",
|
||||
.data = &intc_irqpin_irlm_r8a777x },
|
||||
{ .compatible = "renesas,intc-irqpin-r8a7740",
|
||||
.data = &intc_irqpin_rmobile },
|
||||
{ .compatible = "renesas,intc-irqpin-sh73a0",
|
||||
.data = &intc_irqpin_rmobile },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
|
||||
|
||||
static int intc_irqpin_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct intc_irqpin_config *config = NULL;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct renesas_intc_irqpin_config *pdata = dev->platform_data;
|
||||
const struct of_device_id *of_id;
|
||||
struct intc_irqpin_priv *p;
|
||||
struct intc_irqpin_iomem *i;
|
||||
|
|
@ -388,6 +400,8 @@ static int intc_irqpin_probe(struct platform_device *pdev)
|
|||
void (*enable_fn)(struct irq_data *d);
|
||||
void (*disable_fn)(struct irq_data *d);
|
||||
const char *name = dev_name(dev);
|
||||
bool control_parent;
|
||||
unsigned int nirqs;
|
||||
int ref_irq;
|
||||
int ret;
|
||||
int k;
|
||||
|
|
@ -399,23 +413,28 @@ static int intc_irqpin_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
/* deal with driver instance configuration */
|
||||
if (pdata) {
|
||||
memcpy(&p->config, pdata, sizeof(*pdata));
|
||||
} else {
|
||||
of_property_read_u32(dev->of_node, "sense-bitfield-width",
|
||||
&p->config.sense_bitfield_width);
|
||||
p->config.control_parent = of_property_read_bool(dev->of_node,
|
||||
"control-parent");
|
||||
}
|
||||
if (!p->config.sense_bitfield_width)
|
||||
p->config.sense_bitfield_width = 4; /* default to 4 bits */
|
||||
of_property_read_u32(dev->of_node, "sense-bitfield-width",
|
||||
&p->sense_bitfield_width);
|
||||
control_parent = of_property_read_bool(dev->of_node, "control-parent");
|
||||
if (!p->sense_bitfield_width)
|
||||
p->sense_bitfield_width = 4; /* default to 4 bits */
|
||||
|
||||
p->pdev = pdev;
|
||||
platform_set_drvdata(pdev, p);
|
||||
|
||||
of_id = of_match_device(intc_irqpin_dt_ids, dev);
|
||||
if (of_id && of_id->data) {
|
||||
config = of_id->data;
|
||||
p->needs_clk = config->needs_clk;
|
||||
}
|
||||
|
||||
p->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(p->clk)) {
|
||||
dev_warn(dev, "unable to get clock\n");
|
||||
if (p->needs_clk) {
|
||||
dev_err(dev, "unable to get clock\n");
|
||||
ret = PTR_ERR(p->clk);
|
||||
goto err0;
|
||||
}
|
||||
p->clk = NULL;
|
||||
}
|
||||
|
||||
|
|
@ -443,8 +462,8 @@ static int intc_irqpin_probe(struct platform_device *pdev)
|
|||
p->irq[k].requested_irq = irq->start;
|
||||
}
|
||||
|
||||
p->number_of_irqs = k;
|
||||
if (p->number_of_irqs < 1) {
|
||||
nirqs = k;
|
||||
if (nirqs < 1) {
|
||||
dev_err(dev, "not enough IRQ resources\n");
|
||||
ret = -EINVAL;
|
||||
goto err0;
|
||||
|
|
@ -485,20 +504,16 @@ static int intc_irqpin_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
/* configure "individual IRQ mode" where needed */
|
||||
of_id = of_match_device(intc_irqpin_dt_ids, dev);
|
||||
if (of_id && of_id->data) {
|
||||
const struct intc_irqpin_irlm_config *irlm_config = of_id->data;
|
||||
|
||||
if (config && config->needs_irlm) {
|
||||
if (io[INTC_IRQPIN_REG_IRLM])
|
||||
intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
|
||||
irlm_config->irlm_bit,
|
||||
1, 1);
|
||||
config->irlm_bit, 1, 1);
|
||||
else
|
||||
dev_warn(dev, "unable to select IRLM mode\n");
|
||||
}
|
||||
|
||||
/* mask all interrupts using priority */
|
||||
for (k = 0; k < p->number_of_irqs; k++)
|
||||
for (k = 0; k < nirqs; k++)
|
||||
intc_irqpin_mask_unmask_prio(p, k, 1);
|
||||
|
||||
/* clear all pending interrupts */
|
||||
|
|
@ -506,16 +521,16 @@ static int intc_irqpin_probe(struct platform_device *pdev)
|
|||
|
||||
/* scan for shared interrupt lines */
|
||||
ref_irq = p->irq[0].requested_irq;
|
||||
p->shared_irqs = true;
|
||||
for (k = 1; k < p->number_of_irqs; k++) {
|
||||
p->shared_irqs = 1;
|
||||
for (k = 1; k < nirqs; k++) {
|
||||
if (ref_irq != p->irq[k].requested_irq) {
|
||||
p->shared_irqs = false;
|
||||
p->shared_irqs = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* use more severe masking method if requested */
|
||||
if (p->config.control_parent) {
|
||||
if (control_parent) {
|
||||
enable_fn = intc_irqpin_irq_enable_force;
|
||||
disable_fn = intc_irqpin_irq_disable_force;
|
||||
} else if (!p->shared_irqs) {
|
||||
|
|
@ -534,9 +549,7 @@ static int intc_irqpin_probe(struct platform_device *pdev)
|
|||
irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
|
||||
irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
|
||||
|
||||
p->irq_domain = irq_domain_add_simple(dev->of_node,
|
||||
p->number_of_irqs,
|
||||
p->config.irq_base,
|
||||
p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
|
||||
&intc_irqpin_irq_domain_ops, p);
|
||||
if (!p->irq_domain) {
|
||||
ret = -ENXIO;
|
||||
|
|
@ -555,7 +568,7 @@ static int intc_irqpin_probe(struct platform_device *pdev)
|
|||
}
|
||||
} else {
|
||||
/* request interrupts one by one */
|
||||
for (k = 0; k < p->number_of_irqs; k++) {
|
||||
for (k = 0; k < nirqs; k++) {
|
||||
if (devm_request_irq(dev, p->irq[k].requested_irq,
|
||||
intc_irqpin_irq_handler, 0, name,
|
||||
&p->irq[k])) {
|
||||
|
|
@ -567,17 +580,10 @@ static int intc_irqpin_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
/* unmask all interrupts on prio level */
|
||||
for (k = 0; k < p->number_of_irqs; k++)
|
||||
for (k = 0; k < nirqs; k++)
|
||||
intc_irqpin_mask_unmask_prio(p, k, 0);
|
||||
|
||||
dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
|
||||
|
||||
/* warn in case of mismatch if irq base is specified */
|
||||
if (p->config.irq_base) {
|
||||
if (p->config.irq_base != p->irq[0].domain_irq)
|
||||
dev_warn(dev, "irq base mismatch (%d/%d)\n",
|
||||
p->config.irq_base, p->irq[0].domain_irq);
|
||||
}
|
||||
dev_info(dev, "driving %d irqs\n", nirqs);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -50,6 +50,12 @@ static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
|
|||
.enable = 0x34,
|
||||
};
|
||||
|
||||
static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = {
|
||||
.ctrl = 0x00,
|
||||
.pend = 0x08,
|
||||
.enable = 0x04,
|
||||
};
|
||||
|
||||
static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
|
||||
u32 val)
|
||||
{
|
||||
|
|
@ -207,3 +213,10 @@ static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
|
|||
return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs);
|
||||
}
|
||||
IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
|
||||
|
||||
static int __init sun9i_nmi_irq_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs);
|
||||
}
|
||||
IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
/*
|
||||
* Renesas INTC External IRQ Pin Driver
|
||||
*
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __IRQ_RENESAS_INTC_IRQPIN_H__
|
||||
#define __IRQ_RENESAS_INTC_IRQPIN_H__
|
||||
|
||||
struct renesas_intc_irqpin_config {
|
||||
unsigned int sense_bitfield_width;
|
||||
unsigned int irq_base;
|
||||
bool control_parent;
|
||||
};
|
||||
|
||||
#endif /* __IRQ_RENESAS_INTC_IRQPIN_H__ */
|
||||
Loading…
Reference in New Issue