mtd: nand_ids: improve LEGACY_ID_NAND macro a bit
Notice that all the flashes belonging to the "legacy ID" class have 512 bytes NAND page. This means we may simplify the 'LEGACY_ID_NAND()' macro as well as the NAND ID table a little. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Artem Bityutskiy
David Woodhouse
parent
92a2645820
commit
5bfa9b71a2
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@ -44,36 +44,36 @@ struct nand_flash_dev nand_flash_ids[] = {
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{ .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },
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SZ_8K, SZ_8K, SZ_2M, 0, 8, 640},
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LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 512, 4, 0x2000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 512, 4, 0x2000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 512, 4, 0x2000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 512, 8, 0x2000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 512, 8, 0x2000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, 0x2000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, 0x2000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, 0x2000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, 0x2000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, 0x2000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 16, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 16, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 32MiB 1,8V 8-bit", 0x35, 32, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 32MiB 3,3V 8-bit", 0x75, 32, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 32MiB 1,8V 16-bit", 0x45, 32, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 32MiB 3,3V 16-bit", 0x55, 32, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 64MiB 1,8V 8-bit", 0x36, 64, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 64MiB 3,3V 8-bit", 0x76, 64, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 64MiB 1,8V 16-bit", 0x46, 64, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 64MiB 3,3V 16-bit", 0x56, 64, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 128MiB 1,8V 8-bit", 0x78, 128, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 128MiB 1,8V 8-bit", 0x39, 128, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 128MiB 3,3V 8-bit", 0x79, 128, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x72, 128, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 128MiB 1,8V 16-bit", 0x49, 128, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 128MiB 3,3V 16-bit", 0x74, 128, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 128MiB 3,3V 16-bit", 0x59, 128, 0x4000, SP_OPTIONS16),
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LEGACY_ID_NAND("NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 256MiB 3,3V 8-bit", 0x71, 256, 0x4000, SP_OPTIONS),
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/*
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* These are the new chips with large page size. Their page size and
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@ -68,35 +68,35 @@ static int sm_block_markbad(struct mtd_info *mtd, loff_t ofs)
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}
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static struct nand_flash_dev nand_smartmedia_flash_ids[] = {
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LEGACY_ID_NAND("SmartMedia 2MiB 3,3V ROM", 0x5d, 512, 2, 0x2000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 4MiB 3,3V", 0xe3, 512, 4, 0x2000, 0),
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LEGACY_ID_NAND("SmartMedia 4MiB 3,3/5V", 0xe5, 512, 4, 0x2000, 0),
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LEGACY_ID_NAND("SmartMedia 4MiB 5V", 0x6b, 512, 4, 0x2000, 0),
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LEGACY_ID_NAND("SmartMedia 4MiB 3,3V ROM", 0xd5, 512, 4, 0x2000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 8MiB 3,3V", 0xe6, 512, 8, 0x2000, 0),
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LEGACY_ID_NAND("SmartMedia 8MiB 3,3V ROM", 0xd6, 512, 8, 0x2000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 16MiB 3,3V", 0x73, 512, 16, 0x4000, 0),
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LEGACY_ID_NAND("SmartMedia 16MiB 3,3V ROM", 0x57, 512, 16, 0x4000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 32MiB 3,3V", 0x75, 512, 32, 0x4000, 0),
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LEGACY_ID_NAND("SmartMedia 32MiB 3,3V ROM", 0x58, 512, 32, 0x4000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 64MiB 3,3V", 0x76, 512, 64, 0x4000, 0),
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LEGACY_ID_NAND("SmartMedia 64MiB 3,3V ROM", 0xd9, 512, 64, 0x4000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 128MiB 3,3V", 0x79, 512, 128, 0x4000, 0),
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LEGACY_ID_NAND("SmartMedia 128MiB 3,3V ROM", 0xda, 512, 128, 0x4000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 256MiB 3, 3V", 0x71, 512, 256, 0x4000, 0),
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LEGACY_ID_NAND("SmartMedia 256MiB 3,3V ROM", 0x5b, 512, 256, 0x4000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 2MiB 3,3V ROM", 0x5d, 2, 0x2000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 4MiB 3,3V", 0xe3, 4, 0x2000, 0),
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LEGACY_ID_NAND("SmartMedia 4MiB 3,3/5V", 0xe5, 4, 0x2000, 0),
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LEGACY_ID_NAND("SmartMedia 4MiB 5V", 0x6b, 4, 0x2000, 0),
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LEGACY_ID_NAND("SmartMedia 4MiB 3,3V ROM", 0xd5, 4, 0x2000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 8MiB 3,3V", 0xe6, 8, 0x2000, 0),
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LEGACY_ID_NAND("SmartMedia 8MiB 3,3V ROM", 0xd6, 8, 0x2000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 16MiB 3,3V", 0x73, 16, 0x4000, 0),
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LEGACY_ID_NAND("SmartMedia 16MiB 3,3V ROM", 0x57, 16, 0x4000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 32MiB 3,3V", 0x75, 32, 0x4000, 0),
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LEGACY_ID_NAND("SmartMedia 32MiB 3,3V ROM", 0x58, 32, 0x4000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 64MiB 3,3V", 0x76, 64, 0x4000, 0),
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LEGACY_ID_NAND("SmartMedia 64MiB 3,3V ROM", 0xd9, 64, 0x4000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 128MiB 3,3V", 0x79, 128, 0x4000, 0),
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LEGACY_ID_NAND("SmartMedia 128MiB 3,3V ROM", 0xda, 128, 0x4000, NAND_ROM),
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LEGACY_ID_NAND("SmartMedia 256MiB 3, 3V", 0x71, 256, 0x4000, 0),
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LEGACY_ID_NAND("SmartMedia 256MiB 3,3V ROM", 0x5b, 256, 0x4000, NAND_ROM),
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{NULL}
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};
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static struct nand_flash_dev nand_xd_flash_ids[] = {
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LEGACY_ID_NAND("xD 16MiB 3,3V", 0x73, 512, 16, 0x4000, 0),
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LEGACY_ID_NAND("xD 32MiB 3,3V", 0x75, 512, 32, 0x4000, 0),
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LEGACY_ID_NAND("xD 64MiB 3,3V", 0x76, 512, 64, 0x4000, 0),
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LEGACY_ID_NAND("xD 128MiB 3,3V", 0x79, 512, 128, 0x4000, 0),
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LEGACY_ID_NAND("xD 256MiB 3,3V", 0x71, 512, 256, 0x4000, NAND_BROKEN_XD),
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LEGACY_ID_NAND("xD 512MiB 3,3V", 0xdc, 512, 512, 0x4000, NAND_BROKEN_XD),
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LEGACY_ID_NAND("xD 1GiB 3,3V", 0xd3, 512, 1024, 0x4000, NAND_BROKEN_XD),
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LEGACY_ID_NAND("xD 2GiB 3,3V", 0xd5, 512, 2048, 0x4000, NAND_BROKEN_XD),
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LEGACY_ID_NAND("xD 16MiB 3,3V", 0x73, 16, 0x4000, 0),
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LEGACY_ID_NAND("xD 32MiB 3,3V", 0x75, 32, 0x4000, 0),
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LEGACY_ID_NAND("xD 64MiB 3,3V", 0x76, 64, 0x4000, 0),
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LEGACY_ID_NAND("xD 128MiB 3,3V", 0x79, 128, 0x4000, 0),
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LEGACY_ID_NAND("xD 256MiB 3,3V", 0x71, 256, 0x4000, NAND_BROKEN_XD),
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LEGACY_ID_NAND("xD 512MiB 3,3V", 0xdc, 512, 0x4000, NAND_BROKEN_XD),
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LEGACY_ID_NAND("xD 1GiB 3,3V", 0xd3, 1024, 0x4000, NAND_BROKEN_XD),
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LEGACY_ID_NAND("xD 2GiB 3,3V", 0xd5, 2048, 0x4000, NAND_BROKEN_XD),
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{NULL}
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};
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@ -552,12 +552,11 @@ struct nand_chip {
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/*
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* A helper for defining older NAND chips where the second ID byte fully
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* defined the chip, including the geometry (chip size, eraseblock size, page
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* size).
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* size). All these chips have 512 bytes NAND page size.
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*/
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#define LEGACY_ID_NAND(nm, devid, pagesz, chipsz, erasesz, opts) \
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{ .name = (nm), {{ .dev_id = (devid) }}, .pagesize = (pagesz), \
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.chipsize = (chipsz), .erasesize = (erasesz), \
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.options = (opts) }
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#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
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{ .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
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.chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
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/*
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* A helper for defining newer chips which report their page size and
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