Merge remote-tracking branch 'asoc/topic/fsl' into asoc-next
This commit is contained in:
Mark Brown
commit
5bf83bf8f1
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@ -0,0 +1,54 @@
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Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
|
||||
|
||||
The Freescale S/PDIF audio block is a stereo transceiver that allows the
|
||||
processor to receive and transmit digital audio via an coaxial cable or
|
||||
a fibre cable.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Compatible list, must contain "fsl,imx35-spdif".
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||||
|
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- reg : Offset and length of the register set for the device.
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||||
|
||||
- interrupts : Contains the spdif interrupt.
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||||
|
||||
- dmas : Generic dma devicetree binding as described in
|
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Documentation/devicetree/bindings/dma/dma.txt.
|
||||
|
||||
- dma-names : Two dmas have to be defined, "tx" and "rx".
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|
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- clocks : Contains an entry for each entry in clock-names.
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|
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- clock-names : Includes the following entries:
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"core" The core clock of spdif controller
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"rxtx<0-7>" Clock source list for tx and rx clock.
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This clock list should be identical to
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the source list connecting to the spdif
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clock mux in "SPDIF Transceiver Clock
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Diagram" of SoC reference manual. It
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can also be referred to TxClk_Source
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bit of register SPDIF_STC.
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Example:
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spdif: spdif@02004000 {
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compatible = "fsl,imx35-spdif";
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reg = <0x02004000 0x4000>;
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interrupts = <0 52 0x04>;
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dmas = <&sdma 14 18 0>,
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<&sdma 15 18 0>;
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dma-names = "rx", "tx";
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clocks = <&clks 197>, <&clks 3>,
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<&clks 197>, <&clks 107>,
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<&clks 0>, <&clks 118>,
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<&clks 62>, <&clks 139>,
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<&clks 0>;
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clock-names = "core", "rxtx0",
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"rxtx1", "rxtx2",
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"rxtx3", "rxtx4",
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"rxtx5", "rxtx6",
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"rxtx7";
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status = "okay";
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};
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|
@ -43,10 +43,22 @@ Required properties:
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together. This would still allow different sample sizes,
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but not different sample rates.
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Required are also ac97 link bindings if ac97 is used. See
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Documentation/devicetree/bindings/sound/soc-ac97link.txt for the necessary
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bindings.
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Optional properties:
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- codec-handle: Phandle to a 'codec' node that defines an audio
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codec connected to this SSI. This node is typically
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a child of an I2C or other control node.
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- fsl,fiq-stream-filter: Bool property. Disabled DMA and use FIQ instead to
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filter the codec stream. This is necessary for some boards
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where an incompatible codec is connected to this SSI, e.g.
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on pca100 and pcm043.
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- dmas: Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq
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is not defined.
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Child 'codec' node required properties:
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- compatible: Compatible list, contains the name of the codec
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|
@ -5,6 +5,15 @@ Required properties:
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or "fsl,imx31-audmux" for the version firstly used on i.MX31.
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- reg : Should contain AUDMUX registers location and length
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An initial configuration can be setup using child nodes.
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Required properties of optional child nodes:
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- fsl,audmux-port : Integer of the audmux port that is configured by this
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child node.
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- fsl,port-config : List of configuration options for the specific port. For
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imx31-audmux and above, it is a list of tuples <ptcr pdcr>. For
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imx21-audmux it is a list of pcr values.
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Example:
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audmux@021d8000 {
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|
|
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@ -0,0 +1,56 @@
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#ifndef __DT_FSL_IMX_AUDMUX_H
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#define __DT_FSL_IMX_AUDMUX_H
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#define MX27_AUDMUX_HPCR1_SSI0 0
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#define MX27_AUDMUX_HPCR2_SSI1 1
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#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2
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#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3
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#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4
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#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5
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#define MX31_AUDMUX_PORT1_SSI0 0
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#define MX31_AUDMUX_PORT2_SSI1 1
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#define MX31_AUDMUX_PORT3_SSI_PINS_3 2
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#define MX31_AUDMUX_PORT4_SSI_PINS_4 3
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#define MX31_AUDMUX_PORT5_SSI_PINS_5 4
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#define MX31_AUDMUX_PORT6_SSI_PINS_6 5
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#define MX31_AUDMUX_PORT7_SSI_PINS_7 6
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#define MX51_AUDMUX_PORT1_SSI0 0
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#define MX51_AUDMUX_PORT2_SSI1 1
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#define MX51_AUDMUX_PORT3 2
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#define MX51_AUDMUX_PORT4 3
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#define MX51_AUDMUX_PORT5 4
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#define MX51_AUDMUX_PORT6 5
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#define MX51_AUDMUX_PORT7 6
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/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
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#define IMX_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff)
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#define IMX_AUDMUX_V1_PCR_INMEN (1 << 8)
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#define IMX_AUDMUX_V1_PCR_TXRXEN (1 << 10)
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#define IMX_AUDMUX_V1_PCR_SYN (1 << 12)
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#define IMX_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13)
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#define IMX_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20)
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#define IMX_AUDMUX_V1_PCR_RCLKDIR (1 << 24)
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#define IMX_AUDMUX_V1_PCR_RFSDIR (1 << 25)
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#define IMX_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26)
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#define IMX_AUDMUX_V1_PCR_TCLKDIR (1 << 30)
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#define IMX_AUDMUX_V1_PCR_TFSDIR (1 << 31)
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/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */
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#define IMX_AUDMUX_V2_PTCR_TFSDIR (1 << 31)
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#define IMX_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27)
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#define IMX_AUDMUX_V2_PTCR_TCLKDIR (1 << 26)
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#define IMX_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22)
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#define IMX_AUDMUX_V2_PTCR_RFSDIR (1 << 21)
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#define IMX_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17)
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#define IMX_AUDMUX_V2_PTCR_RCLKDIR (1 << 16)
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#define IMX_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12)
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#define IMX_AUDMUX_V2_PTCR_SYN (1 << 11)
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#define IMX_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13)
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#define IMX_AUDMUX_V2_PDCR_TXRXEN (1 << 12)
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#define IMX_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8)
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#define IMX_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff)
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#endif /* __DT_FSL_IMX_AUDMUX_H */
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@ -1,6 +1,9 @@
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config SND_SOC_FSL_SSI
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tristate
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config SND_SOC_FSL_SPDIF
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tristate
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config SND_SOC_FSL_UTILS
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tristate
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@ -98,7 +101,7 @@ endif # SND_POWERPC_SOC
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menuconfig SND_IMX_SOC
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tristate "SoC Audio for Freescale i.MX CPUs"
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depends on ARCH_MXC
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depends on ARCH_MXC || COMPILE_TEST
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help
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Say Y or M if you want to add support for codecs attached to
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||||
the i.MX CPUs.
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|
@ -109,11 +112,11 @@ config SND_SOC_IMX_SSI
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tristate
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config SND_SOC_IMX_PCM_FIQ
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bool
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tristate
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select FIQ
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config SND_SOC_IMX_PCM_DMA
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bool
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tristate
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select SND_SOC_GENERIC_DMAENGINE_PCM
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config SND_SOC_IMX_AUDMUX
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@ -175,7 +178,6 @@ config SND_SOC_IMX_WM8962
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select SND_SOC_IMX_PCM_DMA
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select SND_SOC_IMX_AUDMUX
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select SND_SOC_FSL_SSI
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select SND_SOC_FSL_UTILS
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help
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Say Y if you want to add support for SoC audio on an i.MX board with
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a wm8962 codec.
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@ -187,14 +189,13 @@ config SND_SOC_IMX_SGTL5000
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select SND_SOC_IMX_PCM_DMA
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select SND_SOC_IMX_AUDMUX
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select SND_SOC_FSL_SSI
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select SND_SOC_FSL_UTILS
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help
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Say Y if you want to add support for SoC audio on an i.MX board with
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a sgtl5000 codec.
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config SND_SOC_IMX_MC13783
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tristate "SoC Audio support for I.MX boards with mc13783"
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depends on MFD_MC13783
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depends on MFD_MC13783 && ARM
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select SND_SOC_IMX_SSI
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select SND_SOC_IMX_AUDMUX
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select SND_SOC_MC13783
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|
|
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@ -12,9 +12,11 @@ obj-$(CONFIG_SND_SOC_P1022_RDK) += snd-soc-p1022-rdk.o
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# Freescale PowerPC SSI/DMA Platform Support
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snd-soc-fsl-ssi-objs := fsl_ssi.o
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snd-soc-fsl-spdif-objs := fsl_spdif.o
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snd-soc-fsl-utils-objs := fsl_utils.o
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snd-soc-fsl-dma-objs := fsl_dma.o
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obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
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obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
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obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
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obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
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|
|
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File diff suppressed because it is too large
Load Diff
|
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@ -0,0 +1,191 @@
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/*
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* fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
|
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*
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||||
* Copyright (C) 2013 Freescale Semiconductor, Inc.
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||||
*
|
||||
* Author: Nicolin Chen <b42378@freescale.com>
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||||
*
|
||||
* Based on fsl_ssi.h
|
||||
* Author: Timur Tabi <timur@freescale.com>
|
||||
* Copyright 2007-2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
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|
||||
#ifndef _FSL_SPDIF_DAI_H
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||||
#define _FSL_SPDIF_DAI_H
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||||
|
||||
/* S/PDIF Register Map */
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#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
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#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
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||||
#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
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||||
#define REG_SPDIF_SIE 0xc /* InterruptEn Register */
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#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
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#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
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||||
#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
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||||
#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
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||||
#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
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||||
#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
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#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
|
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#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
|
||||
#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
|
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#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
|
||||
#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
|
||||
#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
|
||||
#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
|
||||
#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
|
||||
|
||||
|
||||
/* SPDIF Configuration register */
|
||||
#define SCR_RXFIFO_CTL_OFFSET 23
|
||||
#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
|
||||
#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
|
||||
#define SCR_RXFIFO_OFF_OFFSET 22
|
||||
#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
|
||||
#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
|
||||
#define SCR_RXFIFO_RST_OFFSET 21
|
||||
#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
|
||||
#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
|
||||
#define SCR_RXFIFO_FSEL_OFFSET 19
|
||||
#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
|
||||
#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
|
||||
#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
|
||||
#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
|
||||
#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
|
||||
#define SCR_RXFIFO_AUTOSYNC_OFFSET 18
|
||||
#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
|
||||
#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
|
||||
#define SCR_TXFIFO_AUTOSYNC_OFFSET 17
|
||||
#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
|
||||
#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
|
||||
#define SCR_TXFIFO_FSEL_OFFSET 15
|
||||
#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
|
||||
#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
|
||||
#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
|
||||
#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
|
||||
#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
|
||||
#define SCR_LOW_POWER (1 << 13)
|
||||
#define SCR_SOFT_RESET (1 << 12)
|
||||
#define SCR_TXFIFO_CTRL_OFFSET 10
|
||||
#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
|
||||
#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
|
||||
#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
|
||||
#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
|
||||
#define SCR_DMA_RX_EN_OFFSET 9
|
||||
#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
|
||||
#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
|
||||
#define SCR_DMA_TX_EN_OFFSET 8
|
||||
#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
|
||||
#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
|
||||
#define SCR_VAL_OFFSET 5
|
||||
#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
|
||||
#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
|
||||
#define SCR_TXSEL_OFFSET 2
|
||||
#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
|
||||
#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
|
||||
#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
|
||||
#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
|
||||
#define SCR_USRC_SEL_OFFSET 0x0
|
||||
#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
|
||||
#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
|
||||
#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
|
||||
#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
|
||||
|
||||
/* SPDIF CDText control */
|
||||
#define SRCD_CD_USER_OFFSET 1
|
||||
#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
|
||||
|
||||
/* SPDIF Phase Configuration register */
|
||||
#define SRPC_DPLL_LOCKED (1 << 6)
|
||||
#define SRPC_CLKSRC_SEL_OFFSET 7
|
||||
#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
|
||||
#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) & SRPC_CLKSRC_SEL_MASK)
|
||||
#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
|
||||
#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
|
||||
#define SRPC_GAINSEL_OFFSET 3
|
||||
#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
|
||||
#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) & SRPC_GAINSEL_MASK)
|
||||
|
||||
#define SRPC_CLKSRC_MAX 16
|
||||
|
||||
enum spdif_gainsel {
|
||||
GAINSEL_MULTI_24 = 0,
|
||||
GAINSEL_MULTI_16,
|
||||
GAINSEL_MULTI_12,
|
||||
GAINSEL_MULTI_8,
|
||||
GAINSEL_MULTI_6,
|
||||
GAINSEL_MULTI_4,
|
||||
GAINSEL_MULTI_3,
|
||||
};
|
||||
#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
|
||||
#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
|
||||
|
||||
/* SPDIF interrupt mask define */
|
||||
#define INT_DPLL_LOCKED (1 << 20)
|
||||
#define INT_TXFIFO_UNOV (1 << 19)
|
||||
#define INT_TXFIFO_RESYNC (1 << 18)
|
||||
#define INT_CNEW (1 << 17)
|
||||
#define INT_VAL_NOGOOD (1 << 16)
|
||||
#define INT_SYM_ERR (1 << 15)
|
||||
#define INT_BIT_ERR (1 << 14)
|
||||
#define INT_URX_FUL (1 << 10)
|
||||
#define INT_URX_OV (1 << 9)
|
||||
#define INT_QRX_FUL (1 << 8)
|
||||
#define INT_QRX_OV (1 << 7)
|
||||
#define INT_UQ_SYNC (1 << 6)
|
||||
#define INT_UQ_ERR (1 << 5)
|
||||
#define INT_RXFIFO_UNOV (1 << 4)
|
||||
#define INT_RXFIFO_RESYNC (1 << 3)
|
||||
#define INT_LOSS_LOCK (1 << 2)
|
||||
#define INT_TX_EM (1 << 1)
|
||||
#define INT_RXFIFO_FUL (1 << 0)
|
||||
|
||||
/* SPDIF Clock register */
|
||||
#define STC_SYSCLK_DIV_OFFSET 11
|
||||
#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
|
||||
#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK)
|
||||
#define STC_TXCLK_SRC_OFFSET 8
|
||||
#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
|
||||
#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)
|
||||
#define STC_TXCLK_ALL_EN_OFFSET 7
|
||||
#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
|
||||
#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
|
||||
#define STC_TXCLK_DIV_OFFSET 0
|
||||
#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
|
||||
#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_TXCLK_DIV_MASK)
|
||||
#define STC_TXCLK_SRC_MAX 8
|
||||
|
||||
/* SPDIF tx rate */
|
||||
enum spdif_txrate {
|
||||
SPDIF_TXRATE_32000 = 0,
|
||||
SPDIF_TXRATE_44100,
|
||||
SPDIF_TXRATE_48000,
|
||||
};
|
||||
#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
|
||||
|
||||
|
||||
#define SPDIF_CSTATUS_BYTE 6
|
||||
#define SPDIF_UBITS_SIZE 96
|
||||
#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
|
||||
|
||||
|
||||
#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
|
||||
SNDRV_PCM_RATE_44100 | \
|
||||
SNDRV_PCM_RATE_48000)
|
||||
|
||||
#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
|
||||
SNDRV_PCM_RATE_32000 | \
|
||||
SNDRV_PCM_RATE_44100 | \
|
||||
SNDRV_PCM_RATE_48000 | \
|
||||
SNDRV_PCM_RATE_64000 | \
|
||||
SNDRV_PCM_RATE_96000)
|
||||
|
||||
#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
|
||||
SNDRV_PCM_FMTBIT_S20_3LE | \
|
||||
SNDRV_PCM_FMTBIT_S24_LE)
|
||||
|
||||
#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
|
||||
|
||||
#endif /* _FSL_SPDIF_DAI_H */
|
||||
|
|
@ -8,6 +8,26 @@
|
|||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*
|
||||
*
|
||||
* Some notes why imx-pcm-fiq is used instead of DMA on some boards:
|
||||
*
|
||||
* The i.MX SSI core has some nasty limitations in AC97 mode. While most
|
||||
* sane processor vendors have a FIFO per AC97 slot, the i.MX has only
|
||||
* one FIFO which combines all valid receive slots. We cannot even select
|
||||
* which slots we want to receive. The WM9712 with which this driver
|
||||
* was developed with always sends GPIO status data in slot 12 which
|
||||
* we receive in our (PCM-) data stream. The only chance we have is to
|
||||
* manually skip this data in the FIQ handler. With sampling rates different
|
||||
* from 48000Hz not every frame has valid receive data, so the ratio
|
||||
* between pcm data and GPIO status data changes. Our FIQ handler is not
|
||||
* able to handle this, hence this driver only works with 48000Hz sampling
|
||||
* rate.
|
||||
* Reading and writing AC97 registers is another challenge. The core
|
||||
* provides us status bits when the read register is updated with *another*
|
||||
* value. When we read the same register two times (and the register still
|
||||
* contains the same value) these status bits are not set. We work
|
||||
* around this by not polling these bits but only wait a fixed delay.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
|
|
@ -36,7 +56,7 @@
|
|||
#define read_ssi(addr) in_be32(addr)
|
||||
#define write_ssi(val, addr) out_be32(addr, val)
|
||||
#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
|
||||
#elif defined ARM
|
||||
#else
|
||||
#define read_ssi(addr) readl(addr)
|
||||
#define write_ssi(val, addr) writel(val, addr)
|
||||
/*
|
||||
|
|
@ -121,11 +141,14 @@ struct fsl_ssi_private {
|
|||
|
||||
bool new_binding;
|
||||
bool ssi_on_imx;
|
||||
bool imx_ac97;
|
||||
bool use_dma;
|
||||
struct clk *clk;
|
||||
struct snd_dmaengine_dai_dma_data dma_params_tx;
|
||||
struct snd_dmaengine_dai_dma_data dma_params_rx;
|
||||
struct imx_dma_data filter_data_tx;
|
||||
struct imx_dma_data filter_data_rx;
|
||||
struct imx_pcm_fiq_params fiq_params;
|
||||
|
||||
struct {
|
||||
unsigned int rfrc;
|
||||
|
|
@ -298,6 +321,102 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
|
||||
{
|
||||
struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
|
||||
u8 i2s_mode;
|
||||
u8 wm;
|
||||
int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
|
||||
|
||||
if (ssi_private->imx_ac97)
|
||||
i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
|
||||
else
|
||||
i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
|
||||
|
||||
/*
|
||||
* Section 16.5 of the MPC8610 reference manual says that the SSI needs
|
||||
* to be disabled before updating the registers we set here.
|
||||
*/
|
||||
write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
|
||||
|
||||
/*
|
||||
* Program the SSI into I2S Slave Non-Network Synchronous mode. Also
|
||||
* enable the transmit and receive FIFO.
|
||||
*
|
||||
* FIXME: Little-endian samples require a different shift dir
|
||||
*/
|
||||
write_ssi_mask(&ssi->scr,
|
||||
CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
|
||||
CCSR_SSI_SCR_TFR_CLK_DIS |
|
||||
i2s_mode |
|
||||
(synchronous ? CCSR_SSI_SCR_SYN : 0));
|
||||
|
||||
write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
|
||||
CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
|
||||
CCSR_SSI_STCR_TSCKP, &ssi->stcr);
|
||||
|
||||
write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
|
||||
CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
|
||||
CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
|
||||
/*
|
||||
* The DC and PM bits are only used if the SSI is the clock master.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
|
||||
* use FIFO 1. We program the transmit water to signal a DMA transfer
|
||||
* if there are only two (or fewer) elements left in the FIFO. Two
|
||||
* elements equals one frame (left channel, right channel). This value,
|
||||
* however, depends on the depth of the transmit buffer.
|
||||
*
|
||||
* We set the watermark on the same level as the DMA burstsize. For
|
||||
* fiq it is probably better to use the biggest possible watermark
|
||||
* size.
|
||||
*/
|
||||
if (ssi_private->use_dma)
|
||||
wm = ssi_private->fifo_depth - 2;
|
||||
else
|
||||
wm = ssi_private->fifo_depth;
|
||||
|
||||
write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
|
||||
CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
|
||||
&ssi->sfcsr);
|
||||
|
||||
/*
|
||||
* For ac97 interrupts are enabled with the startup of the substream
|
||||
* because it is also running without an active substream. Normally SSI
|
||||
* is only enabled when there is a substream.
|
||||
*/
|
||||
if (ssi_private->imx_ac97) {
|
||||
/*
|
||||
* Setup the clock control register
|
||||
*/
|
||||
write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
|
||||
&ssi->stccr);
|
||||
write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
|
||||
&ssi->srccr);
|
||||
|
||||
/*
|
||||
* Enable AC97 mode and startup the SSI
|
||||
*/
|
||||
write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
|
||||
&ssi->sacnt);
|
||||
write_ssi(0xff, &ssi->saccdis);
|
||||
write_ssi(0x300, &ssi->saccen);
|
||||
|
||||
/*
|
||||
* Enable SSI, Transmit and Receive
|
||||
*/
|
||||
write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
|
||||
CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
|
||||
|
||||
write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* fsl_ssi_startup: create a new substream
|
||||
*
|
||||
|
|
@ -319,70 +438,14 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
|
|||
* and initialize the SSI registers.
|
||||
*/
|
||||
if (!ssi_private->first_stream) {
|
||||
struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
|
||||
|
||||
ssi_private->first_stream = substream;
|
||||
|
||||
/*
|
||||
* Section 16.5 of the MPC8610 reference manual says that the
|
||||
* SSI needs to be disabled before updating the registers we set
|
||||
* here.
|
||||
*/
|
||||
write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
|
||||
|
||||
/*
|
||||
* Program the SSI into I2S Slave Non-Network Synchronous mode.
|
||||
* Also enable the transmit and receive FIFO.
|
||||
*
|
||||
* FIXME: Little-endian samples require a different shift dir
|
||||
*/
|
||||
write_ssi_mask(&ssi->scr,
|
||||
CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
|
||||
CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE
|
||||
| (synchronous ? CCSR_SSI_SCR_SYN : 0));
|
||||
|
||||
write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
|
||||
CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
|
||||
CCSR_SSI_STCR_TSCKP, &ssi->stcr);
|
||||
|
||||
write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
|
||||
CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
|
||||
CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
|
||||
|
||||
/*
|
||||
* The DC and PM bits are only used if the SSI is the clock
|
||||
* master.
|
||||
*/
|
||||
|
||||
/* Enable the interrupts and DMA requests */
|
||||
write_ssi(SIER_FLAGS, &ssi->sier);
|
||||
|
||||
/*
|
||||
* Set the watermark for transmit FIFI 0 and receive FIFO 0. We
|
||||
* don't use FIFO 1. We program the transmit water to signal a
|
||||
* DMA transfer if there are only two (or fewer) elements left
|
||||
* in the FIFO. Two elements equals one frame (left channel,
|
||||
* right channel). This value, however, depends on the depth of
|
||||
* the transmit buffer.
|
||||
*
|
||||
* We program the receive FIFO to notify us if at least two
|
||||
* elements (one frame) have been written to the FIFO. We could
|
||||
* make this value larger (and maybe we should), but this way
|
||||
* data will be written to memory as soon as it's available.
|
||||
*/
|
||||
write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
|
||||
CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2),
|
||||
&ssi->sfcsr);
|
||||
|
||||
/*
|
||||
* We keep the SSI disabled because if we enable it, then the
|
||||
* DMA controller will start. It's not supposed to start until
|
||||
* the SCR.TE (or SCR.RE) bit is set, but it does anyway. The
|
||||
* DMA controller will transfer one "BWC" of data (i.e. the
|
||||
* amount of data that the MR.BWC bits are set to). The reason
|
||||
* this is bad is because at this point, the PCM driver has not
|
||||
* finished initializing the DMA controller.
|
||||
* fsl_ssi_setup was already called by ac97_init earlier if
|
||||
* the driver is in ac97 mode.
|
||||
*/
|
||||
if (!ssi_private->imx_ac97)
|
||||
fsl_ssi_setup(ssi_private);
|
||||
} else {
|
||||
if (synchronous) {
|
||||
struct snd_pcm_runtime *first_runtime =
|
||||
|
|
@ -492,6 +555,27 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
|
|||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
|
||||
struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
|
||||
unsigned int sier_bits;
|
||||
|
||||
/*
|
||||
* Enable only the interrupts and DMA requests
|
||||
* that are needed for the channel. As the fiq
|
||||
* is polling for this bits, we have to ensure
|
||||
* that this are aligned with the preallocated
|
||||
* buffers
|
||||
*/
|
||||
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
if (ssi_private->use_dma)
|
||||
sier_bits = SIER_FLAGS;
|
||||
else
|
||||
sier_bits = CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN;
|
||||
} else {
|
||||
if (ssi_private->use_dma)
|
||||
sier_bits = SIER_FLAGS;
|
||||
else
|
||||
sier_bits = CCSR_SSI_SIER_RIE | CCSR_SSI_SIER_RFF0_EN;
|
||||
}
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
|
|
@ -510,12 +594,18 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
|
|||
write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
|
||||
else
|
||||
write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
|
||||
|
||||
if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
|
||||
(CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0)
|
||||
write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
write_ssi(sier_bits, &ssi->sier);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -534,22 +624,13 @@ static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
|
|||
ssi_private->first_stream = ssi_private->second_stream;
|
||||
|
||||
ssi_private->second_stream = NULL;
|
||||
|
||||
/*
|
||||
* If this is the last active substream, disable the SSI.
|
||||
*/
|
||||
if (!ssi_private->first_stream) {
|
||||
struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
|
||||
|
||||
write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
|
||||
{
|
||||
struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
|
||||
|
||||
if (ssi_private->ssi_on_imx) {
|
||||
if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
|
||||
dai->playback_dma_data = &ssi_private->dma_params_tx;
|
||||
dai->capture_dma_data = &ssi_private->dma_params_rx;
|
||||
}
|
||||
|
|
@ -587,6 +668,133 @@ static const struct snd_soc_component_driver fsl_ssi_component = {
|
|||
.name = "fsl-ssi",
|
||||
};
|
||||
|
||||
/**
|
||||
* fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
|
||||
*
|
||||
* This function is called by ALSA to start, stop, pause, and resume the
|
||||
* transfer of data.
|
||||
*/
|
||||
static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(
|
||||
rtd->cpu_dai);
|
||||
struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
||||
write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE |
|
||||
CCSR_SSI_SIER_TFE0_EN);
|
||||
else
|
||||
write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE |
|
||||
CCSR_SSI_SIER_RFF0_EN);
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
||||
write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE |
|
||||
CCSR_SSI_SIER_TFE0_EN, 0);
|
||||
else
|
||||
write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE |
|
||||
CCSR_SSI_SIER_RFF0_EN, 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
||||
write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
|
||||
else
|
||||
write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = {
|
||||
.startup = fsl_ssi_startup,
|
||||
.shutdown = fsl_ssi_shutdown,
|
||||
.trigger = fsl_ssi_ac97_trigger,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
|
||||
.ac97_control = 1,
|
||||
.playback = {
|
||||
.stream_name = "AC97 Playback",
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_8000_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
.capture = {
|
||||
.stream_name = "AC97 Capture",
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
.ops = &fsl_ssi_ac97_dai_ops,
|
||||
};
|
||||
|
||||
|
||||
static struct fsl_ssi_private *fsl_ac97_data;
|
||||
|
||||
static void fsl_ssi_ac97_init(void)
|
||||
{
|
||||
fsl_ssi_setup(fsl_ac97_data);
|
||||
}
|
||||
|
||||
void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
|
||||
unsigned short val)
|
||||
{
|
||||
struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
|
||||
unsigned int lreg;
|
||||
unsigned int lval;
|
||||
|
||||
if (reg > 0x7f)
|
||||
return;
|
||||
|
||||
|
||||
lreg = reg << 12;
|
||||
write_ssi(lreg, &ssi->sacadd);
|
||||
|
||||
lval = val << 4;
|
||||
write_ssi(lval , &ssi->sacdat);
|
||||
|
||||
write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
|
||||
CCSR_SSI_SACNT_WR);
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
|
||||
unsigned short reg)
|
||||
{
|
||||
struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
|
||||
|
||||
unsigned short val = -1;
|
||||
unsigned int lreg;
|
||||
|
||||
lreg = (reg & 0x7f) << 12;
|
||||
write_ssi(lreg, &ssi->sacadd);
|
||||
write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
|
||||
CCSR_SSI_SACNT_RD);
|
||||
|
||||
udelay(100);
|
||||
|
||||
val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
|
||||
.read = fsl_ssi_ac97_read,
|
||||
.write = fsl_ssi_ac97_write,
|
||||
};
|
||||
|
||||
/* Show the statistics of a flag only if its interrupt is enabled. The
|
||||
* compiler will optimze this code to a no-op if the interrupt is not
|
||||
* enabled.
|
||||
|
|
@ -663,6 +871,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
|
|||
struct resource res;
|
||||
char name[64];
|
||||
bool shared;
|
||||
bool ac97 = false;
|
||||
|
||||
/* SSIs that are not connected on the board should have a
|
||||
* status = "disabled"
|
||||
|
|
@ -673,14 +882,20 @@ static int fsl_ssi_probe(struct platform_device *pdev)
|
|||
|
||||
/* We only support the SSI in "I2S Slave" mode */
|
||||
sprop = of_get_property(np, "fsl,mode", NULL);
|
||||
if (!sprop || strcmp(sprop, "i2s-slave")) {
|
||||
if (!sprop) {
|
||||
dev_err(&pdev->dev, "fsl,mode property is necessary\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
if (!strcmp(sprop, "ac97-slave")) {
|
||||
ac97 = true;
|
||||
} else if (strcmp(sprop, "i2s-slave")) {
|
||||
dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* The DAI name is the last part of the full name of the node. */
|
||||
p = strrchr(np->full_name, '/') + 1;
|
||||
ssi_private = kzalloc(sizeof(struct fsl_ssi_private) + strlen(p),
|
||||
ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
|
||||
GFP_KERNEL);
|
||||
if (!ssi_private) {
|
||||
dev_err(&pdev->dev, "could not allocate DAI object\n");
|
||||
|
|
@ -689,38 +904,41 @@ static int fsl_ssi_probe(struct platform_device *pdev)
|
|||
|
||||
strcpy(ssi_private->name, p);
|
||||
|
||||
/* Initialize this copy of the CPU DAI driver structure */
|
||||
memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
|
||||
sizeof(fsl_ssi_dai_template));
|
||||
ssi_private->use_dma = !of_property_read_bool(np,
|
||||
"fsl,fiq-stream-filter");
|
||||
|
||||
if (ac97) {
|
||||
memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
|
||||
sizeof(fsl_ssi_ac97_dai));
|
||||
|
||||
fsl_ac97_data = ssi_private;
|
||||
ssi_private->imx_ac97 = true;
|
||||
|
||||
snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
|
||||
} else {
|
||||
/* Initialize this copy of the CPU DAI driver structure */
|
||||
memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
|
||||
sizeof(fsl_ssi_dai_template));
|
||||
}
|
||||
ssi_private->cpu_dai_drv.name = ssi_private->name;
|
||||
|
||||
/* Get the addresses and IRQ */
|
||||
ret = of_address_to_resource(np, 0, &res);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "could not determine device resources\n");
|
||||
goto error_kmalloc;
|
||||
return ret;
|
||||
}
|
||||
ssi_private->ssi = of_iomap(np, 0);
|
||||
if (!ssi_private->ssi) {
|
||||
dev_err(&pdev->dev, "could not map device resources\n");
|
||||
ret = -ENOMEM;
|
||||
goto error_kmalloc;
|
||||
return -ENOMEM;
|
||||
}
|
||||
ssi_private->ssi_phys = res.start;
|
||||
|
||||
ssi_private->irq = irq_of_parse_and_map(np, 0);
|
||||
if (ssi_private->irq == NO_IRQ) {
|
||||
dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
|
||||
ret = -ENXIO;
|
||||
goto error_iomap;
|
||||
}
|
||||
|
||||
/* The 'name' should not have any slashes in it. */
|
||||
ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, ssi_private->name,
|
||||
ssi_private);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "could not claim irq %u\n", ssi_private->irq);
|
||||
goto error_irqmap;
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
/* Are the RX and the TX clocks locked? */
|
||||
|
|
@ -739,13 +957,18 @@ static int fsl_ssi_probe(struct platform_device *pdev)
|
|||
u32 dma_events[2];
|
||||
ssi_private->ssi_on_imx = true;
|
||||
|
||||
ssi_private->clk = clk_get(&pdev->dev, NULL);
|
||||
ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(ssi_private->clk)) {
|
||||
ret = PTR_ERR(ssi_private->clk);
|
||||
dev_err(&pdev->dev, "could not get clock: %d\n", ret);
|
||||
goto error_irq;
|
||||
goto error_irqmap;
|
||||
}
|
||||
ret = clk_prepare_enable(ssi_private->clk);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
|
||||
ret);
|
||||
goto error_irqmap;
|
||||
}
|
||||
clk_prepare_enable(ssi_private->clk);
|
||||
|
||||
/*
|
||||
* We have burstsize be "fifo_depth - 2" to match the SSI
|
||||
|
|
@ -763,24 +986,38 @@ static int fsl_ssi_probe(struct platform_device *pdev)
|
|||
&ssi_private->filter_data_tx;
|
||||
ssi_private->dma_params_rx.filter_data =
|
||||
&ssi_private->filter_data_rx;
|
||||
/*
|
||||
* TODO: This is a temporary solution and should be changed
|
||||
* to use generic DMA binding later when the helplers get in.
|
||||
*/
|
||||
ret = of_property_read_u32_array(pdev->dev.of_node,
|
||||
if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
|
||||
ssi_private->use_dma) {
|
||||
/*
|
||||
* FIXME: This is a temporary solution until all
|
||||
* necessary dma drivers support the generic dma
|
||||
* bindings.
|
||||
*/
|
||||
ret = of_property_read_u32_array(pdev->dev.of_node,
|
||||
"fsl,ssi-dma-events", dma_events, 2);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "could not get dma events\n");
|
||||
goto error_clk;
|
||||
if (ret && ssi_private->use_dma) {
|
||||
dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
|
||||
goto error_clk;
|
||||
}
|
||||
}
|
||||
|
||||
shared = of_device_is_compatible(of_get_parent(np),
|
||||
"fsl,spba-bus");
|
||||
|
||||
imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
|
||||
dma_events[0], shared);
|
||||
dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
|
||||
imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
|
||||
dma_events[1], shared);
|
||||
dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
|
||||
} else if (ssi_private->use_dma) {
|
||||
/* The 'name' should not have any slashes in it. */
|
||||
ret = devm_request_irq(&pdev->dev, ssi_private->irq,
|
||||
fsl_ssi_isr, 0, ssi_private->name,
|
||||
ssi_private);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "could not claim irq %u\n",
|
||||
ssi_private->irq);
|
||||
goto error_irqmap;
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialize the the device_attribute structure */
|
||||
|
|
@ -794,7 +1031,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
|
|||
if (ret) {
|
||||
dev_err(&pdev->dev, "could not create sysfs %s file\n",
|
||||
ssi_private->dev_attr.attr.name);
|
||||
goto error_irq;
|
||||
goto error_clk;
|
||||
}
|
||||
|
||||
/* Register with ASoC */
|
||||
|
|
@ -808,9 +1045,30 @@ static int fsl_ssi_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
if (ssi_private->ssi_on_imx) {
|
||||
ret = imx_pcm_dma_init(pdev);
|
||||
if (ret)
|
||||
goto error_dev;
|
||||
if (!ssi_private->use_dma) {
|
||||
|
||||
/*
|
||||
* Some boards use an incompatible codec. To get it
|
||||
* working, we are using imx-fiq-pcm-audio, that
|
||||
* can handle those codecs. DMA is not possible in this
|
||||
* situation.
|
||||
*/
|
||||
|
||||
ssi_private->fiq_params.irq = ssi_private->irq;
|
||||
ssi_private->fiq_params.base = ssi_private->ssi;
|
||||
ssi_private->fiq_params.dma_params_rx =
|
||||
&ssi_private->dma_params_rx;
|
||||
ssi_private->fiq_params.dma_params_tx =
|
||||
&ssi_private->dma_params_tx;
|
||||
|
||||
ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
|
||||
if (ret)
|
||||
goto error_dev;
|
||||
} else {
|
||||
ret = imx_pcm_dma_init(pdev);
|
||||
if (ret)
|
||||
goto error_dev;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -845,6 +1103,9 @@ static int fsl_ssi_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
done:
|
||||
if (ssi_private->imx_ac97)
|
||||
fsl_ssi_ac97_init();
|
||||
|
||||
return 0;
|
||||
|
||||
error_dai:
|
||||
|
|
@ -857,23 +1118,12 @@ error_dev:
|
|||
device_remove_file(&pdev->dev, dev_attr);
|
||||
|
||||
error_clk:
|
||||
if (ssi_private->ssi_on_imx) {
|
||||
if (ssi_private->ssi_on_imx)
|
||||
clk_disable_unprepare(ssi_private->clk);
|
||||
clk_put(ssi_private->clk);
|
||||
}
|
||||
|
||||
error_irq:
|
||||
free_irq(ssi_private->irq, ssi_private);
|
||||
|
||||
error_irqmap:
|
||||
irq_dispose_mapping(ssi_private->irq);
|
||||
|
||||
error_iomap:
|
||||
iounmap(ssi_private->ssi);
|
||||
|
||||
error_kmalloc:
|
||||
kfree(ssi_private);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -883,19 +1133,14 @@ static int fsl_ssi_remove(struct platform_device *pdev)
|
|||
|
||||
if (!ssi_private->new_binding)
|
||||
platform_device_unregister(ssi_private->pdev);
|
||||
if (ssi_private->ssi_on_imx) {
|
||||
if (ssi_private->ssi_on_imx)
|
||||
imx_pcm_dma_exit(pdev);
|
||||
clk_disable_unprepare(ssi_private->clk);
|
||||
clk_put(ssi_private->clk);
|
||||
}
|
||||
snd_soc_unregister_component(&pdev->dev);
|
||||
device_remove_file(&pdev->dev, &ssi_private->dev_attr);
|
||||
|
||||
free_irq(ssi_private->irq, ssi_private);
|
||||
irq_dispose_mapping(ssi_private->irq);
|
||||
|
||||
kfree(ssi_private);
|
||||
dev_set_drvdata(&pdev->dev, NULL);
|
||||
device_remove_file(&pdev->dev, &ssi_private->dev_attr);
|
||||
if (ssi_private->ssi_on_imx)
|
||||
clk_disable_unprepare(ssi_private->clk);
|
||||
irq_dispose_mapping(ssi_private->irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -919,6 +1164,7 @@ static struct platform_driver fsl_ssi_driver = {
|
|||
|
||||
module_platform_driver(fsl_ssi_driver);
|
||||
|
||||
MODULE_ALIAS("platform:fsl-ssi-dai");
|
||||
MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
|
||||
MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
|
|
@ -73,8 +73,11 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
|
|||
if (!buf)
|
||||
return -ENOMEM;
|
||||
|
||||
if (audmux_clk)
|
||||
clk_prepare_enable(audmux_clk);
|
||||
if (audmux_clk) {
|
||||
ret = clk_prepare_enable(audmux_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ptcr = readl(audmux_base + IMX_AUDMUX_V2_PTCR(port));
|
||||
pdcr = readl(audmux_base + IMX_AUDMUX_V2_PDCR(port));
|
||||
|
|
@ -224,14 +227,19 @@ EXPORT_SYMBOL_GPL(imx_audmux_v1_configure_port);
|
|||
int imx_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
|
||||
unsigned int pdcr)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (audmux_type != IMX31_AUDMUX)
|
||||
return -EINVAL;
|
||||
|
||||
if (!audmux_base)
|
||||
return -ENOSYS;
|
||||
|
||||
if (audmux_clk)
|
||||
clk_prepare_enable(audmux_clk);
|
||||
if (audmux_clk) {
|
||||
ret = clk_prepare_enable(audmux_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
writel(ptcr, audmux_base + IMX_AUDMUX_V2_PTCR(port));
|
||||
writel(pdcr, audmux_base + IMX_AUDMUX_V2_PDCR(port));
|
||||
|
|
@ -243,6 +251,66 @@ int imx_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(imx_audmux_v2_configure_port);
|
||||
|
||||
static int imx_audmux_parse_dt_defaults(struct platform_device *pdev,
|
||||
struct device_node *of_node)
|
||||
{
|
||||
struct device_node *child;
|
||||
|
||||
for_each_available_child_of_node(of_node, child) {
|
||||
unsigned int port;
|
||||
unsigned int ptcr = 0;
|
||||
unsigned int pdcr = 0;
|
||||
unsigned int pcr = 0;
|
||||
unsigned int val;
|
||||
int ret;
|
||||
int i = 0;
|
||||
|
||||
ret = of_property_read_u32(child, "fsl,audmux-port", &port);
|
||||
if (ret) {
|
||||
dev_warn(&pdev->dev, "Failed to get fsl,audmux-port of child node \"%s\"\n",
|
||||
child->full_name);
|
||||
continue;
|
||||
}
|
||||
if (!of_property_read_bool(child, "fsl,port-config")) {
|
||||
dev_warn(&pdev->dev, "child node \"%s\" does not have property fsl,port-config\n",
|
||||
child->full_name);
|
||||
continue;
|
||||
}
|
||||
|
||||
for (i = 0; (ret = of_property_read_u32_index(child,
|
||||
"fsl,port-config", i, &val)) == 0;
|
||||
++i) {
|
||||
if (audmux_type == IMX31_AUDMUX) {
|
||||
if (i % 2)
|
||||
pdcr |= val;
|
||||
else
|
||||
ptcr |= val;
|
||||
} else {
|
||||
pcr |= val;
|
||||
}
|
||||
}
|
||||
|
||||
if (ret != -EOVERFLOW) {
|
||||
dev_err(&pdev->dev, "Failed to read u32 at index %d of child %s\n",
|
||||
i, child->full_name);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (audmux_type == IMX31_AUDMUX) {
|
||||
if (i % 2) {
|
||||
dev_err(&pdev->dev, "One pdcr value is missing in child node %s\n",
|
||||
child->full_name);
|
||||
continue;
|
||||
}
|
||||
imx_audmux_v2_configure_port(port, ptcr, pdcr);
|
||||
} else {
|
||||
imx_audmux_v1_configure_port(port, pcr);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imx_audmux_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
|
@ -267,6 +335,8 @@ static int imx_audmux_probe(struct platform_device *pdev)
|
|||
if (audmux_type == IMX31_AUDMUX)
|
||||
audmux_debugfs_init();
|
||||
|
||||
imx_audmux_parse_dt_defaults(pdev, pdev->dev.of_node);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,57 +1,7 @@
|
|||
#ifndef __IMX_AUDMUX_H
|
||||
#define __IMX_AUDMUX_H
|
||||
|
||||
#define MX27_AUDMUX_HPCR1_SSI0 0
|
||||
#define MX27_AUDMUX_HPCR2_SSI1 1
|
||||
#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2
|
||||
#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3
|
||||
#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4
|
||||
#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5
|
||||
|
||||
#define MX31_AUDMUX_PORT1_SSI0 0
|
||||
#define MX31_AUDMUX_PORT2_SSI1 1
|
||||
#define MX31_AUDMUX_PORT3_SSI_PINS_3 2
|
||||
#define MX31_AUDMUX_PORT4_SSI_PINS_4 3
|
||||
#define MX31_AUDMUX_PORT5_SSI_PINS_5 4
|
||||
#define MX31_AUDMUX_PORT6_SSI_PINS_6 5
|
||||
#define MX31_AUDMUX_PORT7_SSI_PINS_7 6
|
||||
|
||||
#define MX51_AUDMUX_PORT1_SSI0 0
|
||||
#define MX51_AUDMUX_PORT2_SSI1 1
|
||||
#define MX51_AUDMUX_PORT3 2
|
||||
#define MX51_AUDMUX_PORT4 3
|
||||
#define MX51_AUDMUX_PORT5 4
|
||||
#define MX51_AUDMUX_PORT6 5
|
||||
#define MX51_AUDMUX_PORT7 6
|
||||
|
||||
/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
|
||||
#define IMX_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff)
|
||||
#define IMX_AUDMUX_V1_PCR_INMEN (1 << 8)
|
||||
#define IMX_AUDMUX_V1_PCR_TXRXEN (1 << 10)
|
||||
#define IMX_AUDMUX_V1_PCR_SYN (1 << 12)
|
||||
#define IMX_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13)
|
||||
#define IMX_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20)
|
||||
#define IMX_AUDMUX_V1_PCR_RCLKDIR (1 << 24)
|
||||
#define IMX_AUDMUX_V1_PCR_RFSDIR (1 << 25)
|
||||
#define IMX_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26)
|
||||
#define IMX_AUDMUX_V1_PCR_TCLKDIR (1 << 30)
|
||||
#define IMX_AUDMUX_V1_PCR_TFSDIR (1 << 31)
|
||||
|
||||
/* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */
|
||||
#define IMX_AUDMUX_V2_PTCR_TFSDIR (1 << 31)
|
||||
#define IMX_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27)
|
||||
#define IMX_AUDMUX_V2_PTCR_TCLKDIR (1 << 26)
|
||||
#define IMX_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22)
|
||||
#define IMX_AUDMUX_V2_PTCR_RFSDIR (1 << 21)
|
||||
#define IMX_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17)
|
||||
#define IMX_AUDMUX_V2_PTCR_RCLKDIR (1 << 16)
|
||||
#define IMX_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12)
|
||||
#define IMX_AUDMUX_V2_PTCR_SYN (1 << 11)
|
||||
|
||||
#define IMX_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13)
|
||||
#define IMX_AUDMUX_V2_PDCR_TXRXEN (1 << 12)
|
||||
#define IMX_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8)
|
||||
#define IMX_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff)
|
||||
#include <dt-bindings/sound/fsl-imx-audmux.h>
|
||||
|
||||
int imx_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
|
||||
|
||||
|
|
|
|||
|
|
@ -90,6 +90,7 @@ static const struct snd_soc_dapm_route imx_mc13783_routes[] = {
|
|||
|
||||
static struct snd_soc_card imx_mc13783 = {
|
||||
.name = "imx_mc13783",
|
||||
.owner = THIS_MODULE,
|
||||
.dai_link = imx_mc13783_dai_mc13783,
|
||||
.num_links = ARRAY_SIZE(imx_mc13783_dai_mc13783),
|
||||
.dapm_widgets = imx_mc13783_widget,
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <sound/core.h>
|
||||
#include <sound/pcm.h>
|
||||
|
|
@ -64,7 +65,6 @@ int imx_pcm_dma_init(struct platform_device *pdev)
|
|||
{
|
||||
return snd_dmaengine_pcm_register(&pdev->dev, &imx_dmaengine_pcm_config,
|
||||
SND_DMAENGINE_PCM_FLAG_NO_RESIDUE |
|
||||
SND_DMAENGINE_PCM_FLAG_NO_DT |
|
||||
SND_DMAENGINE_PCM_FLAG_COMPAT);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(imx_pcm_dma_init);
|
||||
|
|
@ -74,3 +74,5 @@ void imx_pcm_dma_exit(struct platform_device *pdev)
|
|||
snd_dmaengine_pcm_unregister(&pdev->dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(imx_pcm_dma_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/slab.h>
|
||||
|
||||
#include <sound/core.h>
|
||||
#include <sound/dmaengine_pcm.h>
|
||||
#include <sound/initval.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/pcm_params.h>
|
||||
|
|
@ -32,6 +33,7 @@
|
|||
#include <linux/platform_data/asoc-imx-ssi.h>
|
||||
|
||||
#include "imx-ssi.h"
|
||||
#include "imx-pcm.h"
|
||||
|
||||
struct imx_pcm_runtime_data {
|
||||
unsigned int period;
|
||||
|
|
@ -366,9 +368,9 @@ static struct snd_soc_platform_driver imx_soc_platform_fiq = {
|
|||
.pcm_free = imx_pcm_fiq_free,
|
||||
};
|
||||
|
||||
int imx_pcm_fiq_init(struct platform_device *pdev)
|
||||
int imx_pcm_fiq_init(struct platform_device *pdev,
|
||||
struct imx_pcm_fiq_params *params)
|
||||
{
|
||||
struct imx_ssi *ssi = platform_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
ret = claim_fiq(&fh);
|
||||
|
|
@ -377,15 +379,15 @@ int imx_pcm_fiq_init(struct platform_device *pdev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
mxc_set_irq_fiq(ssi->irq, 1);
|
||||
ssi_irq = ssi->irq;
|
||||
mxc_set_irq_fiq(params->irq, 1);
|
||||
ssi_irq = params->irq;
|
||||
|
||||
imx_pcm_fiq = ssi->irq;
|
||||
imx_pcm_fiq = params->irq;
|
||||
|
||||
imx_ssi_fiq_base = (unsigned long)ssi->base;
|
||||
imx_ssi_fiq_base = (unsigned long)params->base;
|
||||
|
||||
ssi->dma_params_tx.maxburst = 4;
|
||||
ssi->dma_params_rx.maxburst = 6;
|
||||
params->dma_params_tx->maxburst = 4;
|
||||
params->dma_params_rx->maxburst = 6;
|
||||
|
||||
ret = snd_soc_register_platform(&pdev->dev, &imx_soc_platform_fiq);
|
||||
if (ret)
|
||||
|
|
@ -406,3 +408,5 @@ void imx_pcm_fiq_exit(struct platform_device *pdev)
|
|||
snd_soc_unregister_platform(&pdev->dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(imx_pcm_fiq_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
|||
|
|
@ -22,17 +22,23 @@
|
|||
|
||||
static inline void
|
||||
imx_pcm_dma_params_init_data(struct imx_dma_data *dma_data,
|
||||
int dma, bool shared)
|
||||
int dma, enum sdma_peripheral_type peripheral_type)
|
||||
{
|
||||
dma_data->dma_request = dma;
|
||||
dma_data->priority = DMA_PRIO_HIGH;
|
||||
if (shared)
|
||||
dma_data->peripheral_type = IMX_DMATYPE_SSI_SP;
|
||||
else
|
||||
dma_data->peripheral_type = IMX_DMATYPE_SSI;
|
||||
dma_data->peripheral_type = peripheral_type;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SND_SOC_IMX_PCM_DMA
|
||||
struct imx_pcm_fiq_params {
|
||||
int irq;
|
||||
void __iomem *base;
|
||||
|
||||
/* Pointer to original ssi driver to setup tx rx sizes */
|
||||
struct snd_dmaengine_dai_dma_data *dma_params_rx;
|
||||
struct snd_dmaengine_dai_dma_data *dma_params_tx;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)
|
||||
int imx_pcm_dma_init(struct platform_device *pdev);
|
||||
void imx_pcm_dma_exit(struct platform_device *pdev);
|
||||
#else
|
||||
|
|
@ -46,11 +52,13 @@ static inline void imx_pcm_dma_exit(struct platform_device *pdev)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SND_SOC_IMX_PCM_FIQ
|
||||
int imx_pcm_fiq_init(struct platform_device *pdev);
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_FIQ)
|
||||
int imx_pcm_fiq_init(struct platform_device *pdev,
|
||||
struct imx_pcm_fiq_params *params);
|
||||
void imx_pcm_fiq_exit(struct platform_device *pdev);
|
||||
#else
|
||||
static inline int imx_pcm_fiq_init(struct platform_device *pdev)
|
||||
static inline int imx_pcm_fiq_init(struct platform_device *pdev,
|
||||
struct imx_pcm_fiq_params *params)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -129,8 +129,10 @@ static int imx_sgtl5000_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
data->codec_clk = devm_clk_get(&codec_dev->dev, NULL);
|
||||
if (IS_ERR(data->codec_clk))
|
||||
if (IS_ERR(data->codec_clk)) {
|
||||
ret = PTR_ERR(data->codec_clk);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
data->clk_frequency = clk_get_rate(data->codec_clk);
|
||||
|
||||
|
|
|
|||
|
|
@ -571,13 +571,13 @@ static int imx_ssi_probe(struct platform_device *pdev)
|
|||
res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
|
||||
if (res) {
|
||||
imx_pcm_dma_params_init_data(&ssi->filter_data_tx, res->start,
|
||||
false);
|
||||
IMX_DMATYPE_SSI);
|
||||
}
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
|
||||
if (res) {
|
||||
imx_pcm_dma_params_init_data(&ssi->filter_data_rx, res->start,
|
||||
false);
|
||||
IMX_DMATYPE_SSI);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, ssi);
|
||||
|
|
@ -595,7 +595,12 @@ static int imx_ssi_probe(struct platform_device *pdev)
|
|||
goto failed_register;
|
||||
}
|
||||
|
||||
ret = imx_pcm_fiq_init(pdev);
|
||||
ssi->fiq_params.irq = ssi->irq;
|
||||
ssi->fiq_params.base = ssi->base;
|
||||
ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
|
||||
ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
|
||||
|
||||
ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
|
||||
if (ret)
|
||||
goto failed_pcm_fiq;
|
||||
|
||||
|
|
|
|||
|
|
@ -209,6 +209,7 @@ struct imx_ssi {
|
|||
struct snd_dmaengine_dai_dma_data dma_params_tx;
|
||||
struct imx_dma_data filter_data_tx;
|
||||
struct imx_dma_data filter_data_rx;
|
||||
struct imx_pcm_fiq_params fiq_params;
|
||||
|
||||
int enabled;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -217,7 +217,8 @@ static int imx_wm8962_probe(struct platform_device *pdev)
|
|||
codec_dev = of_find_i2c_device_by_node(codec_np);
|
||||
if (!codec_dev || !codec_dev->driver) {
|
||||
dev_err(&pdev->dev, "failed to find codec platform device\n");
|
||||
return -EINVAL;
|
||||
ret = -EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
|
||||
|
|
|
|||
Loading…
Reference in New Issue