drm/amdgpu: Implement gfx9 patch functions for resubmission
Patch the packages including CONTEXT_CONTROL and WRITE_DATA for gfx9 during the resubmission scenario. Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.3.x
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@ -5139,9 +5139,83 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
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#endif
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lower_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
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amdgpu_ring_ib_on_emit_cntl(ring);
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amdgpu_ring_write(ring, control);
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}
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static void gfx_v9_0_ring_patch_cntl(struct amdgpu_ring *ring,
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unsigned offset)
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{
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u32 control = ring->ring[offset];
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control |= INDIRECT_BUFFER_PRE_RESUME(1);
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ring->ring[offset] = control;
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}
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static void gfx_v9_0_ring_patch_ce_meta(struct amdgpu_ring *ring,
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unsigned offset)
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{
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struct amdgpu_device *adev = ring->adev;
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void *ce_payload_cpu_addr;
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uint64_t payload_offset, payload_size;
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payload_size = sizeof(struct v9_ce_ib_state);
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if (ring->is_mes_queue) {
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payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data,
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gfx[0].gfx_meta_data) +
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offsetof(struct v9_gfx_meta_data, ce_payload);
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ce_payload_cpu_addr =
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amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset);
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} else {
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payload_offset = offsetof(struct v9_gfx_meta_data, ce_payload);
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ce_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset;
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}
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if (offset + (payload_size >> 2) <= ring->buf_mask + 1) {
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memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr, payload_size);
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} else {
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memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr,
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(ring->buf_mask + 1 - offset) << 2);
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payload_size -= (ring->buf_mask + 1 - offset) << 2;
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memcpy((void *)&ring->ring[0],
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ce_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2),
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payload_size);
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}
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}
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static void gfx_v9_0_ring_patch_de_meta(struct amdgpu_ring *ring,
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unsigned offset)
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{
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struct amdgpu_device *adev = ring->adev;
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void *de_payload_cpu_addr;
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uint64_t payload_offset, payload_size;
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payload_size = sizeof(struct v9_de_ib_state);
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if (ring->is_mes_queue) {
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payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data,
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gfx[0].gfx_meta_data) +
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offsetof(struct v9_gfx_meta_data, de_payload);
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de_payload_cpu_addr =
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amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset);
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} else {
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payload_offset = offsetof(struct v9_gfx_meta_data, de_payload);
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de_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset;
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}
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if (offset + (payload_size >> 2) <= ring->buf_mask + 1) {
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memcpy((void *)&ring->ring[offset], de_payload_cpu_addr, payload_size);
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} else {
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memcpy((void *)&ring->ring[offset], de_payload_cpu_addr,
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(ring->buf_mask + 1 - offset) << 2);
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payload_size -= (ring->buf_mask + 1 - offset) << 2;
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memcpy((void *)&ring->ring[0],
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de_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2),
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payload_size);
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}
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}
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static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
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struct amdgpu_job *job,
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struct amdgpu_ib *ib,
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@ -5337,6 +5411,8 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
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amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
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amdgpu_ring_ib_on_emit_ce(ring);
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if (resume)
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amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
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sizeof(ce_payload) >> 2);
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@ -5448,6 +5524,7 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bo
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amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
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amdgpu_ring_ib_on_emit_de(ring);
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if (resume)
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amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
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sizeof(de_payload) >> 2);
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@ -6858,6 +6935,9 @@ static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = {
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.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
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.soft_recovery = gfx_v9_0_ring_soft_recovery,
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.emit_mem_sync = gfx_v9_0_emit_mem_sync,
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.patch_cntl = gfx_v9_0_ring_patch_cntl,
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.patch_de = gfx_v9_0_ring_patch_de_meta,
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.patch_ce = gfx_v9_0_ring_patch_ce_meta,
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};
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static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
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