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ASoC: tlv320aic32x4: Ensure a minimum delay before clock stabilization 

As indicated in the datasheet, a 10ms delay must be observed after
programming the divisors.

The lack of delay prevents the codec to work properly and the playback
appears extremely slow and totally un-audible on a custom sama5 based
board.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20200911173140.29984-2-miquel.raynal@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Miquel Raynal 2020-09-11 19:31:38 +02:00 committed by Mark Brown
parent 501ef01339
commit 5b4458ebb4
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GPG Key ID: 24D68B725D5487D0
1 changed files with 8 additions and 1 deletions
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9
sound/soc/codecs/tlv320aic32x4-clk.c
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@ -230,7 +230,14 @@ static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
if (ret < 0)
return -EINVAL;
return clk_aic32x4_pll_set_muldiv(pll, &settings);
ret = clk_aic32x4_pll_set_muldiv(pll, &settings);
if (ret)
return ret;
/* 10ms is the delay to wait before the clocks are stable */
msleep(10);
return 0;
}
static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)