Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
ath.git patches for v5.10. Major changes: wcn36xx * add support wcn3680 Wi-Fi 5 devices ath11k * spectral scan support for ipq6018
This commit is contained in:
commit
5b365af4c8
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@ -1022,7 +1022,7 @@ static int ath10k_core_check_smbios(struct ath10k *ar)
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return 0;
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}
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static int ath10k_core_check_dt(struct ath10k *ar)
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int ath10k_core_check_dt(struct ath10k *ar)
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{
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struct device_node *node;
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const char *variant = NULL;
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@ -1043,6 +1043,7 @@ static int ath10k_core_check_dt(struct ath10k *ar)
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return 0;
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}
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EXPORT_SYMBOL(ath10k_core_check_dt);
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static int ath10k_download_fw(struct ath10k *ar)
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{
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@ -1437,10 +1438,17 @@ static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
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}
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if (ar->id.qmi_ids_valid) {
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scnprintf(name, name_len,
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"bus=%s,qmi-board-id=%x",
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ath10k_bus_str(ar->hif.bus),
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ar->id.qmi_board_id);
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if (with_variant && ar->id.bdf_ext[0] != '\0')
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scnprintf(name, name_len,
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"bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s",
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ath10k_bus_str(ar->hif.bus),
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ar->id.qmi_board_id, ar->id.qmi_chip_id,
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variant);
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else
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scnprintf(name, name_len,
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"bus=%s,qmi-board-id=%x",
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ath10k_bus_str(ar->hif.bus),
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ar->id.qmi_board_id);
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goto out;
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}
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@ -1076,6 +1076,7 @@ struct ath10k {
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bool bmi_ids_valid;
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bool qmi_ids_valid;
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u32 qmi_board_id;
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u32 qmi_chip_id;
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u8 bmi_board_id;
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u8 bmi_eboard_id;
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u8 bmi_chip_id;
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@ -1315,6 +1316,7 @@ int ath10k_core_register(struct ath10k *ar,
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const struct ath10k_bus_params *bus_params);
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void ath10k_core_unregister(struct ath10k *ar);
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int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type);
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int ath10k_core_check_dt(struct ath10k *ar);
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void ath10k_core_free_board_files(struct ath10k *ar);
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#endif /* _CORE_H_ */
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@ -576,6 +576,8 @@ static int ath10k_qmi_cap_send_sync_msg(struct ath10k_qmi *qmi)
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if (resp->chip_info_valid) {
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qmi->chip_info.chip_id = resp->chip_info.chip_id;
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qmi->chip_info.chip_family = resp->chip_info.chip_family;
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} else {
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qmi->chip_info.chip_id = 0xFF;
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}
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if (resp->board_info_valid)
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@ -817,12 +819,18 @@ err_setup_msa:
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static int ath10k_qmi_fetch_board_file(struct ath10k_qmi *qmi)
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{
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struct ath10k *ar = qmi->ar;
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int ret;
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ar->hif.bus = ATH10K_BUS_SNOC;
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ar->id.qmi_ids_valid = true;
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ar->id.qmi_board_id = qmi->board_info.board_id;
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ar->id.qmi_chip_id = qmi->chip_info.chip_id;
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ar->hw_params.fw.dir = WCN3990_HW_1_0_FW_DIR;
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ret = ath10k_core_check_dt(ar);
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if (ret)
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ath10k_dbg(ar, ATH10K_DBG_QMI, "DT bdf variant name not set.\n");
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return ath10k_core_fetch_board_file(qmi->ar, ATH10K_BD_IE_BOARD);
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}
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@ -18,7 +18,7 @@ ath11k-y += core.o \
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dbring.o \
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hw.o
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ath11k-$(CONFIG_ATH11K_DEBUGFS) += debug_htt_stats.o debugfs_sta.o
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ath11k-$(CONFIG_ATH11K_DEBUGFS) += debugfs.o debugfs_htt_stats.o debugfs_sta.o
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ath11k-$(CONFIG_NL80211_TESTMODE) += testmode.o
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ath11k-$(CONFIG_ATH11K_TRACING) += trace.o
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ath11k-$(CONFIG_THERMAL) += thermal.o
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@ -323,9 +323,10 @@ static void ath11k_ahb_stop(struct ath11k_base *ab)
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static int ath11k_ahb_power_up(struct ath11k_base *ab)
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{
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struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
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int ret;
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ret = rproc_boot(ab->tgt_rproc);
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ret = rproc_boot(ab_ahb->tgt_rproc);
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if (ret)
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ath11k_err(ab, "failed to boot the remote processor Q6\n");
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@ -334,7 +335,9 @@ static int ath11k_ahb_power_up(struct ath11k_base *ab)
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static void ath11k_ahb_power_down(struct ath11k_base *ab)
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{
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rproc_shutdown(ab->tgt_rproc);
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struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
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rproc_shutdown(ab_ahb->tgt_rproc);
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}
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static void ath11k_ahb_init_qmi_ce_config(struct ath11k_base *ab)
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@ -600,6 +603,28 @@ static const struct ath11k_hif_ops ath11k_ahb_hif_ops = {
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.power_up = ath11k_ahb_power_up,
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};
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static int ath11k_core_get_rproc(struct ath11k_base *ab)
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{
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struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
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struct device *dev = ab->dev;
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struct rproc *prproc;
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phandle rproc_phandle;
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if (of_property_read_u32(dev->of_node, "qcom,rproc", &rproc_phandle)) {
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ath11k_err(ab, "failed to get q6_rproc handle\n");
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return -ENOENT;
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}
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prproc = rproc_get_by_phandle(rproc_phandle);
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if (!prproc) {
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ath11k_err(ab, "failed to get rproc\n");
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return -EINVAL;
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}
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ab_ahb->tgt_rproc = prproc;
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return 0;
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}
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static int ath11k_ahb_probe(struct platform_device *pdev)
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{
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struct ath11k_base *ab;
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@ -626,7 +651,9 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
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return ret;
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}
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ab = ath11k_core_alloc(&pdev->dev, 0, ATH11K_BUS_AHB, &ath11k_ahb_bus_params);
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ab = ath11k_core_alloc(&pdev->dev, sizeof(struct ath11k_ahb),
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ATH11K_BUS_AHB,
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&ath11k_ahb_bus_params);
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if (!ab) {
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dev_err(&pdev->dev, "failed to allocate ath11k base\n");
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return -ENOMEM;
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@ -655,6 +682,12 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
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ath11k_ahb_init_qmi_ce_config(ab);
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ret = ath11k_core_get_rproc(ab);
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if (ret) {
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ath11k_err(ab, "failed to get rproc: %d\n", ret);
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goto err_ce_free;
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}
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ret = ath11k_core_init(ab);
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if (ret) {
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ath11k_err(ab, "failed to init core: %d\n", ret);
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@ -685,12 +718,16 @@ err_core_free:
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static int ath11k_ahb_remove(struct platform_device *pdev)
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{
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struct ath11k_base *ab = platform_get_drvdata(pdev);
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unsigned long left;
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reinit_completion(&ab->driver_recovery);
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if (test_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags))
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wait_for_completion_timeout(&ab->driver_recovery,
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ATH11K_AHB_RECOVERY_TIMEOUT);
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if (test_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags)) {
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left = wait_for_completion_timeout(&ab->driver_recovery,
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ATH11K_AHB_RECOVERY_TIMEOUT);
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if (!left)
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ath11k_warn(ab, "failed to receive recovery response completion\n");
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}
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set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
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cancel_work_sync(&ab->restart_work);
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@ -10,4 +10,12 @@
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#define ATH11K_AHB_RECOVERY_TIMEOUT (3 * HZ)
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struct ath11k_base;
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struct ath11k_ahb {
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struct rproc *tgt_rproc;
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};
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static inline struct ath11k_ahb *ath11k_ahb_priv(struct ath11k_base *ab)
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{
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return (struct ath11k_ahb *)ab->drv_priv;
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}
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#endif
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@ -57,6 +57,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
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.vdev_start_delay = false,
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.htt_peer_map_v2 = true,
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.tcl_0_only = false,
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.spectral_fft_sz = 2,
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},
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{
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.hw_rev = ATH11K_HW_IPQ6018_HW10,
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@ -86,6 +87,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
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.vdev_start_delay = false,
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.htt_peer_map_v2 = true,
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.tcl_0_only = false,
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.spectral_fft_sz = 4,
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},
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{
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.name = "qca6390 hw2.0",
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@ -115,6 +117,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
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.vdev_start_delay = true,
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.htt_peer_map_v2 = false,
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.tcl_0_only = true,
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.spectral_fft_sz = 0,
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},
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};
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@ -412,7 +415,7 @@ static int ath11k_core_soc_create(struct ath11k_base *ab)
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return ret;
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}
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ret = ath11k_debug_soc_create(ab);
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ret = ath11k_debugfs_soc_create(ab);
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if (ret) {
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ath11k_err(ab, "failed to create ath11k debugfs\n");
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goto err_qmi_deinit;
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@ -427,7 +430,7 @@ static int ath11k_core_soc_create(struct ath11k_base *ab)
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return 0;
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err_debugfs_reg:
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ath11k_debug_soc_destroy(ab);
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ath11k_debugfs_soc_destroy(ab);
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err_qmi_deinit:
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ath11k_qmi_deinit_service(ab);
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return ret;
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@ -435,7 +438,7 @@ err_qmi_deinit:
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static void ath11k_core_soc_destroy(struct ath11k_base *ab)
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{
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ath11k_debug_soc_destroy(ab);
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ath11k_debugfs_soc_destroy(ab);
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ath11k_dp_free(ab);
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ath11k_reg_free(ab);
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ath11k_qmi_deinit_service(ab);
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@ -445,7 +448,7 @@ static int ath11k_core_pdev_create(struct ath11k_base *ab)
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{
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int ret;
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ret = ath11k_debug_pdev_create(ab);
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ret = ath11k_debugfs_pdev_create(ab);
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if (ret) {
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ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret);
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return ret;
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@ -485,7 +488,7 @@ err_dp_pdev_free:
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err_mac_unregister:
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ath11k_mac_unregister(ab);
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err_pdev_debug:
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ath11k_debug_pdev_destroy(ab);
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ath11k_debugfs_pdev_destroy(ab);
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return ret;
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}
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@ -497,7 +500,7 @@ static void ath11k_core_pdev_destroy(struct ath11k_base *ab)
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ath11k_mac_unregister(ab);
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ath11k_hif_irq_disable(ab);
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ath11k_dp_pdev_free(ab);
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ath11k_debug_pdev_destroy(ab);
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ath11k_debugfs_pdev_destroy(ab);
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}
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static int ath11k_core_start(struct ath11k_base *ab,
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@ -842,43 +845,10 @@ int ath11k_core_pre_init(struct ath11k_base *ab)
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}
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EXPORT_SYMBOL(ath11k_core_pre_init);
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static int ath11k_core_get_rproc(struct ath11k_base *ab)
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{
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struct device *dev = ab->dev;
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struct rproc *prproc;
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phandle rproc_phandle;
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if (!IS_ENABLED(CONFIG_REMOTEPROC))
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return 0;
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if (ab->bus_params.mhi_support)
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return 0;
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if (of_property_read_u32(dev->of_node, "qcom,rproc", &rproc_phandle)) {
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ath11k_err(ab, "failed to get q6_rproc handle\n");
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return -ENOENT;
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}
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prproc = rproc_get_by_phandle(rproc_phandle);
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if (!prproc) {
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ath11k_err(ab, "failed to get rproc\n");
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return -EINVAL;
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}
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ab->tgt_rproc = prproc;
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return 0;
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}
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int ath11k_core_init(struct ath11k_base *ab)
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{
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int ret;
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ret = ath11k_core_get_rproc(ab);
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if (ret) {
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ath11k_err(ab, "failed to get rproc: %d\n", ret);
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return ret;
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}
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ret = ath11k_core_soc_create(ab);
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if (ret) {
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ath11k_err(ab, "failed to create soc core: %d\n", ret);
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|
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@ -648,7 +648,6 @@ struct ath11k_base {
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struct ath11k_qmi qmi;
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struct ath11k_wmi_base wmi_ab;
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struct completion fw_ready;
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struct rproc *tgt_rproc;
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int num_radios;
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/* HW channel counters frequency value in hertz common to all MACs */
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u32 cc_freq_hz;
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File diff suppressed because it is too large
Load Diff
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@ -6,11 +6,8 @@
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#ifndef _ATH11K_DEBUG_H_
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#define _ATH11K_DEBUG_H_
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#include "hal_tx.h"
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#include "trace.h"
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#define ATH11K_TX_POWER_MAX_VAL 70
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#define ATH11K_TX_POWER_MIN_VAL 0
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#include "debugfs.h"
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enum ath11k_debug_mask {
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ATH11K_DBG_AHB = 0x00000001,
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@ -31,98 +28,6 @@ enum ath11k_debug_mask {
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ATH11K_DBG_ANY = 0xffffffff,
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};
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/* htt_dbg_ext_stats_type */
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enum ath11k_dbg_htt_ext_stats_type {
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ATH11K_DBG_HTT_EXT_STATS_RESET = 0,
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ATH11K_DBG_HTT_EXT_STATS_PDEV_TX = 1,
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ATH11K_DBG_HTT_EXT_STATS_PDEV_RX = 2,
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ATH11K_DBG_HTT_EXT_STATS_PDEV_TX_HWQ = 3,
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ATH11K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4,
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ATH11K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5,
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ATH11K_DBG_HTT_EXT_STATS_PDEV_TQM = 6,
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ATH11K_DBG_HTT_EXT_STATS_TQM_CMDQ = 7,
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ATH11K_DBG_HTT_EXT_STATS_TX_DE_INFO = 8,
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ATH11K_DBG_HTT_EXT_STATS_PDEV_TX_RATE = 9,
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ATH11K_DBG_HTT_EXT_STATS_PDEV_RX_RATE = 10,
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ATH11K_DBG_HTT_EXT_STATS_PEER_INFO = 11,
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ATH11K_DBG_HTT_EXT_STATS_TX_SELFGEN_INFO = 12,
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ATH11K_DBG_HTT_EXT_STATS_TX_MU_HWQ = 13,
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ATH11K_DBG_HTT_EXT_STATS_RING_IF_INFO = 14,
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ATH11K_DBG_HTT_EXT_STATS_SRNG_INFO = 15,
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ATH11K_DBG_HTT_EXT_STATS_SFM_INFO = 16,
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ATH11K_DBG_HTT_EXT_STATS_PDEV_TX_MU = 17,
|
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ATH11K_DBG_HTT_EXT_STATS_ACTIVE_PEERS_LIST = 18,
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ATH11K_DBG_HTT_EXT_STATS_PDEV_CCA_STATS = 19,
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ATH11K_DBG_HTT_EXT_STATS_TWT_SESSIONS = 20,
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ATH11K_DBG_HTT_EXT_STATS_REO_RESOURCE_STATS = 21,
|
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ATH11K_DBG_HTT_EXT_STATS_TX_SOUNDING_INFO = 22,
|
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ATH11K_DBG_HTT_EXT_STATS_PDEV_OBSS_PD_STATS = 23,
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ATH11K_DBG_HTT_EXT_STATS_RING_BACKPRESSURE_STATS = 24,
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|
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/* keep this last */
|
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ATH11K_DBG_HTT_NUM_EXT_STATS,
|
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};
|
||||
|
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struct debug_htt_stats_req {
|
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bool done;
|
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u8 pdev_id;
|
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u8 type;
|
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u8 peer_addr[ETH_ALEN];
|
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struct completion cmpln;
|
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u32 buf_len;
|
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u8 buf[];
|
||||
};
|
||||
|
||||
struct ath_pktlog_hdr {
|
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u16 flags;
|
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u16 missed_cnt;
|
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u16 log_type;
|
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u16 size;
|
||||
u32 timestamp;
|
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u32 type_specific_data;
|
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u8 payload[];
|
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};
|
||||
|
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#define ATH11K_HTT_PEER_STATS_RESET BIT(16)
|
||||
|
||||
#define ATH11K_HTT_STATS_BUF_SIZE (1024 * 512)
|
||||
#define ATH11K_FW_STATS_BUF_SIZE (1024 * 1024)
|
||||
|
||||
enum ath11k_pktlog_filter {
|
||||
ATH11K_PKTLOG_RX = 0x000000001,
|
||||
ATH11K_PKTLOG_TX = 0x000000002,
|
||||
ATH11K_PKTLOG_RCFIND = 0x000000004,
|
||||
ATH11K_PKTLOG_RCUPDATE = 0x000000008,
|
||||
ATH11K_PKTLOG_EVENT_SMART_ANT = 0x000000020,
|
||||
ATH11K_PKTLOG_EVENT_SW = 0x000000040,
|
||||
ATH11K_PKTLOG_ANY = 0x00000006f,
|
||||
};
|
||||
|
||||
enum ath11k_pktlog_mode {
|
||||
ATH11K_PKTLOG_MODE_LITE = 1,
|
||||
ATH11K_PKTLOG_MODE_FULL = 2,
|
||||
};
|
||||
|
||||
enum ath11k_pktlog_enum {
|
||||
ATH11K_PKTLOG_TYPE_TX_CTRL = 1,
|
||||
ATH11K_PKTLOG_TYPE_TX_STAT = 2,
|
||||
ATH11K_PKTLOG_TYPE_TX_MSDU_ID = 3,
|
||||
ATH11K_PKTLOG_TYPE_RX_STAT = 5,
|
||||
ATH11K_PKTLOG_TYPE_RC_FIND = 6,
|
||||
ATH11K_PKTLOG_TYPE_RC_UPDATE = 7,
|
||||
ATH11K_PKTLOG_TYPE_TX_VIRT_ADDR = 8,
|
||||
ATH11K_PKTLOG_TYPE_RX_CBF = 10,
|
||||
ATH11K_PKTLOG_TYPE_RX_STATBUF = 22,
|
||||
ATH11K_PKTLOG_TYPE_PPDU_STATS = 23,
|
||||
ATH11K_PKTLOG_TYPE_LITE_RX = 24,
|
||||
};
|
||||
|
||||
enum ath11k_dbg_aggr_mode {
|
||||
ATH11K_DBG_AGGR_MODE_AUTO,
|
||||
ATH11K_DBG_AGGR_MODE_MANUAL,
|
||||
ATH11K_DBG_AGGR_MODE_MAX,
|
||||
};
|
||||
|
||||
__printf(2, 3) void ath11k_info(struct ath11k_base *ab, const char *fmt, ...);
|
||||
__printf(2, 3) void ath11k_err(struct ath11k_base *ab, const char *fmt, ...);
|
||||
__printf(2, 3) void ath11k_warn(struct ath11k_base *ab, const char *fmt, ...);
|
||||
|
@ -153,153 +58,6 @@ static inline void ath11k_dbg_dump(struct ath11k_base *ab,
|
|||
}
|
||||
#endif /* CONFIG_ATH11K_DEBUG */
|
||||
|
||||
#ifdef CONFIG_ATH11K_DEBUGFS
|
||||
int ath11k_debug_soc_create(struct ath11k_base *ab);
|
||||
void ath11k_debug_soc_destroy(struct ath11k_base *ab);
|
||||
int ath11k_debug_pdev_create(struct ath11k_base *ab);
|
||||
void ath11k_debug_pdev_destroy(struct ath11k_base *ab);
|
||||
int ath11k_debug_register(struct ath11k *ar);
|
||||
void ath11k_debug_unregister(struct ath11k *ar);
|
||||
void ath11k_dbg_htt_ext_stats_handler(struct ath11k_base *ab,
|
||||
struct sk_buff *skb);
|
||||
void ath11k_debug_fw_stats_process(struct ath11k_base *ab, struct sk_buff *skb);
|
||||
|
||||
void ath11k_debug_fw_stats_init(struct ath11k *ar);
|
||||
int ath11k_dbg_htt_stats_req(struct ath11k *ar);
|
||||
|
||||
static inline bool ath11k_debug_is_pktlog_lite_mode_enabled(struct ath11k *ar)
|
||||
{
|
||||
return (ar->debug.pktlog_mode == ATH11K_PKTLOG_MODE_LITE);
|
||||
}
|
||||
|
||||
static inline bool ath11k_debug_is_pktlog_rx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return (!ar->debug.pktlog_peer_valid && ar->debug.pktlog_mode);
|
||||
}
|
||||
|
||||
static inline bool ath11k_debug_is_pktlog_peer_valid(struct ath11k *ar, u8 *addr)
|
||||
{
|
||||
return (ar->debug.pktlog_peer_valid && ar->debug.pktlog_mode &&
|
||||
ether_addr_equal(addr, ar->debug.pktlog_peer_addr));
|
||||
}
|
||||
|
||||
static inline int ath11k_debug_is_extd_tx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return ar->debug.extd_tx_stats;
|
||||
}
|
||||
|
||||
static inline int ath11k_debug_is_extd_rx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return ar->debug.extd_rx_stats;
|
||||
}
|
||||
|
||||
static inline int ath11k_debug_rx_filter(struct ath11k *ar)
|
||||
{
|
||||
return ar->debug.rx_filter;
|
||||
}
|
||||
|
||||
void ath11k_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta, struct dentry *dir);
|
||||
void
|
||||
ath11k_accumulate_per_peer_tx_stats(struct ath11k_sta *arsta,
|
||||
struct ath11k_per_peer_tx_stats *peer_stats,
|
||||
u8 legacy_rate_idx);
|
||||
void ath11k_update_per_peer_stats_from_txcompl(struct ath11k *ar,
|
||||
struct sk_buff *msdu,
|
||||
struct hal_tx_status *ts);
|
||||
#else
|
||||
static inline int ath11k_debug_soc_create(struct ath11k_base *ab)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void ath11k_debug_soc_destroy(struct ath11k_base *ab)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int ath11k_debug_pdev_create(struct ath11k_base *ab)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void ath11k_debug_pdev_destroy(struct ath11k_base *ab)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int ath11k_debug_register(struct ath11k *ar)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void ath11k_debug_unregister(struct ath11k *ar)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void ath11k_dbg_htt_ext_stats_handler(struct ath11k_base *ab,
|
||||
struct sk_buff *skb)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void ath11k_debug_fw_stats_process(struct ath11k_base *ab,
|
||||
struct sk_buff *skb)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void ath11k_debug_fw_stats_init(struct ath11k *ar)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int ath11k_debug_is_extd_tx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int ath11k_debug_is_extd_rx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int ath11k_dbg_htt_stats_req(struct ath11k *ar)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline bool ath11k_debug_is_pktlog_lite_mode_enabled(struct ath11k *ar)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool ath11k_debug_is_pktlog_rx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool ath11k_debug_is_pktlog_peer_valid(struct ath11k *ar, u8 *addr)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline int ath11k_debug_rx_filter(struct ath11k *ar)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void
|
||||
ath11k_accumulate_per_peer_tx_stats(struct ath11k_sta *arsta,
|
||||
struct ath11k_per_peer_tx_stats *peer_stats,
|
||||
u8 legacy_rate_idx)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void
|
||||
ath11k_update_per_peer_stats_from_txcompl(struct ath11k *ar,
|
||||
struct sk_buff *msdu,
|
||||
struct hal_tx_status *ts)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MAC80211_DEBUGFS*/
|
||||
|
||||
#define ath11k_dbg(ar, dbg_mask, fmt, ...) \
|
||||
do { \
|
||||
if (ath11k_debug_mask & dbg_mask) \
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,227 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
|
||||
/*
|
||||
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _ATH11K_DEBUGFS_H_
|
||||
#define _ATH11K_DEBUGFS_H_
|
||||
|
||||
#include "hal_tx.h"
|
||||
|
||||
#define ATH11K_TX_POWER_MAX_VAL 70
|
||||
#define ATH11K_TX_POWER_MIN_VAL 0
|
||||
|
||||
/* htt_dbg_ext_stats_type */
|
||||
enum ath11k_dbg_htt_ext_stats_type {
|
||||
ATH11K_DBG_HTT_EXT_STATS_RESET = 0,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PDEV_TX = 1,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PDEV_RX = 2,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PDEV_TX_HWQ = 3,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PDEV_TQM = 6,
|
||||
ATH11K_DBG_HTT_EXT_STATS_TQM_CMDQ = 7,
|
||||
ATH11K_DBG_HTT_EXT_STATS_TX_DE_INFO = 8,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PDEV_TX_RATE = 9,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PDEV_RX_RATE = 10,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PEER_INFO = 11,
|
||||
ATH11K_DBG_HTT_EXT_STATS_TX_SELFGEN_INFO = 12,
|
||||
ATH11K_DBG_HTT_EXT_STATS_TX_MU_HWQ = 13,
|
||||
ATH11K_DBG_HTT_EXT_STATS_RING_IF_INFO = 14,
|
||||
ATH11K_DBG_HTT_EXT_STATS_SRNG_INFO = 15,
|
||||
ATH11K_DBG_HTT_EXT_STATS_SFM_INFO = 16,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PDEV_TX_MU = 17,
|
||||
ATH11K_DBG_HTT_EXT_STATS_ACTIVE_PEERS_LIST = 18,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PDEV_CCA_STATS = 19,
|
||||
ATH11K_DBG_HTT_EXT_STATS_TWT_SESSIONS = 20,
|
||||
ATH11K_DBG_HTT_EXT_STATS_REO_RESOURCE_STATS = 21,
|
||||
ATH11K_DBG_HTT_EXT_STATS_TX_SOUNDING_INFO = 22,
|
||||
ATH11K_DBG_HTT_EXT_STATS_PDEV_OBSS_PD_STATS = 23,
|
||||
ATH11K_DBG_HTT_EXT_STATS_RING_BACKPRESSURE_STATS = 24,
|
||||
|
||||
/* keep this last */
|
||||
ATH11K_DBG_HTT_NUM_EXT_STATS,
|
||||
};
|
||||
|
||||
struct debug_htt_stats_req {
|
||||
bool done;
|
||||
u8 pdev_id;
|
||||
u8 type;
|
||||
u8 peer_addr[ETH_ALEN];
|
||||
struct completion cmpln;
|
||||
u32 buf_len;
|
||||
u8 buf[];
|
||||
};
|
||||
|
||||
struct ath_pktlog_hdr {
|
||||
u16 flags;
|
||||
u16 missed_cnt;
|
||||
u16 log_type;
|
||||
u16 size;
|
||||
u32 timestamp;
|
||||
u32 type_specific_data;
|
||||
u8 payload[];
|
||||
};
|
||||
|
||||
#define ATH11K_HTT_PEER_STATS_RESET BIT(16)
|
||||
|
||||
#define ATH11K_HTT_STATS_BUF_SIZE (1024 * 512)
|
||||
#define ATH11K_FW_STATS_BUF_SIZE (1024 * 1024)
|
||||
|
||||
enum ath11k_pktlog_filter {
|
||||
ATH11K_PKTLOG_RX = 0x000000001,
|
||||
ATH11K_PKTLOG_TX = 0x000000002,
|
||||
ATH11K_PKTLOG_RCFIND = 0x000000004,
|
||||
ATH11K_PKTLOG_RCUPDATE = 0x000000008,
|
||||
ATH11K_PKTLOG_EVENT_SMART_ANT = 0x000000020,
|
||||
ATH11K_PKTLOG_EVENT_SW = 0x000000040,
|
||||
ATH11K_PKTLOG_ANY = 0x00000006f,
|
||||
};
|
||||
|
||||
enum ath11k_pktlog_mode {
|
||||
ATH11K_PKTLOG_MODE_LITE = 1,
|
||||
ATH11K_PKTLOG_MODE_FULL = 2,
|
||||
};
|
||||
|
||||
enum ath11k_pktlog_enum {
|
||||
ATH11K_PKTLOG_TYPE_TX_CTRL = 1,
|
||||
ATH11K_PKTLOG_TYPE_TX_STAT = 2,
|
||||
ATH11K_PKTLOG_TYPE_TX_MSDU_ID = 3,
|
||||
ATH11K_PKTLOG_TYPE_RX_STAT = 5,
|
||||
ATH11K_PKTLOG_TYPE_RC_FIND = 6,
|
||||
ATH11K_PKTLOG_TYPE_RC_UPDATE = 7,
|
||||
ATH11K_PKTLOG_TYPE_TX_VIRT_ADDR = 8,
|
||||
ATH11K_PKTLOG_TYPE_RX_CBF = 10,
|
||||
ATH11K_PKTLOG_TYPE_RX_STATBUF = 22,
|
||||
ATH11K_PKTLOG_TYPE_PPDU_STATS = 23,
|
||||
ATH11K_PKTLOG_TYPE_LITE_RX = 24,
|
||||
};
|
||||
|
||||
enum ath11k_dbg_aggr_mode {
|
||||
ATH11K_DBG_AGGR_MODE_AUTO,
|
||||
ATH11K_DBG_AGGR_MODE_MANUAL,
|
||||
ATH11K_DBG_AGGR_MODE_MAX,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ATH11K_DEBUGFS
|
||||
int ath11k_debugfs_soc_create(struct ath11k_base *ab);
|
||||
void ath11k_debugfs_soc_destroy(struct ath11k_base *ab);
|
||||
int ath11k_debugfs_pdev_create(struct ath11k_base *ab);
|
||||
void ath11k_debugfs_pdev_destroy(struct ath11k_base *ab);
|
||||
int ath11k_debugfs_register(struct ath11k *ar);
|
||||
void ath11k_debugfs_unregister(struct ath11k *ar);
|
||||
void ath11k_debugfs_fw_stats_process(struct ath11k_base *ab, struct sk_buff *skb);
|
||||
|
||||
void ath11k_debugfs_fw_stats_init(struct ath11k *ar);
|
||||
|
||||
static inline bool ath11k_debugfs_is_pktlog_lite_mode_enabled(struct ath11k *ar)
|
||||
{
|
||||
return (ar->debug.pktlog_mode == ATH11K_PKTLOG_MODE_LITE);
|
||||
}
|
||||
|
||||
static inline bool ath11k_debugfs_is_pktlog_rx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return (!ar->debug.pktlog_peer_valid && ar->debug.pktlog_mode);
|
||||
}
|
||||
|
||||
static inline bool ath11k_debugfs_is_pktlog_peer_valid(struct ath11k *ar, u8 *addr)
|
||||
{
|
||||
return (ar->debug.pktlog_peer_valid && ar->debug.pktlog_mode &&
|
||||
ether_addr_equal(addr, ar->debug.pktlog_peer_addr));
|
||||
}
|
||||
|
||||
static inline int ath11k_debugfs_is_extd_tx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return ar->debug.extd_tx_stats;
|
||||
}
|
||||
|
||||
static inline int ath11k_debugfs_is_extd_rx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return ar->debug.extd_rx_stats;
|
||||
}
|
||||
|
||||
static inline int ath11k_debugfs_rx_filter(struct ath11k *ar)
|
||||
{
|
||||
return ar->debug.rx_filter;
|
||||
}
|
||||
|
||||
#else
|
||||
static inline int ath11k_debugfs_soc_create(struct ath11k_base *ab)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void ath11k_debugfs_soc_destroy(struct ath11k_base *ab)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int ath11k_debugfs_pdev_create(struct ath11k_base *ab)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void ath11k_debugfs_pdev_destroy(struct ath11k_base *ab)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int ath11k_debugfs_register(struct ath11k *ar)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void ath11k_debugfs_unregister(struct ath11k *ar)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void ath11k_dbg_htt_ext_stats_handler(struct ath11k_base *ab,
|
||||
struct sk_buff *skb)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void ath11k_debugfs_fw_stats_process(struct ath11k_base *ab,
|
||||
struct sk_buff *skb)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void ath11k_debugfs_fw_stats_init(struct ath11k *ar)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int ath11k_debugfs_is_extd_tx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int ath11k_debugfs_is_extd_rx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int ath11k_debugfs_htt_stats_req(struct ath11k *ar)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline bool ath11k_debugfs_is_pktlog_lite_mode_enabled(struct ath11k *ar)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool ath11k_debugfs_is_pktlog_rx_stats_enabled(struct ath11k *ar)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool ath11k_debugfs_is_pktlog_peer_valid(struct ath11k *ar, u8 *addr)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline int ath11k_debugfs_rx_filter(struct ath11k *ar)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MAC80211_DEBUGFS*/
|
||||
|
||||
#endif /* _ATH11K_DEBUGFS_H_ */
|
|
@ -8,7 +8,7 @@
|
|||
#include "dp_tx.h"
|
||||
#include "dp_rx.h"
|
||||
#include "debug.h"
|
||||
#include "debug_htt_stats.h"
|
||||
#include "debugfs_htt_stats.h"
|
||||
|
||||
#define HTT_DBG_OUT(buf, len, fmt, ...) \
|
||||
scnprintf(buf, len, fmt "\n", ##__VA_ARGS__)
|
||||
|
@ -4253,8 +4253,8 @@ static int ath11k_dbg_htt_ext_stats_parse(struct ath11k_base *ab,
|
|||
return 0;
|
||||
}
|
||||
|
||||
void ath11k_dbg_htt_ext_stats_handler(struct ath11k_base *ab,
|
||||
struct sk_buff *skb)
|
||||
void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab,
|
||||
struct sk_buff *skb)
|
||||
{
|
||||
struct ath11k_htt_extd_stats_msg *msg;
|
||||
struct debug_htt_stats_req *stats_req;
|
||||
|
@ -4402,7 +4402,7 @@ static int ath11k_prep_htt_stats_cfg_params(struct ath11k *ar, u8 type,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int ath11k_dbg_htt_stats_req(struct ath11k *ar)
|
||||
int ath11k_debugfs_htt_stats_req(struct ath11k *ar)
|
||||
{
|
||||
struct debug_htt_stats_req *stats_req = ar->debug.htt_stats.stats_req;
|
||||
u8 type = stats_req->type;
|
||||
|
@ -4476,7 +4476,7 @@ static int ath11k_open_htt_stats(struct inode *inode, struct file *file)
|
|||
ar->debug.htt_stats.stats_req = stats_req;
|
||||
stats_req->type = type;
|
||||
|
||||
ret = ath11k_dbg_htt_stats_req(ar);
|
||||
ret = ath11k_debugfs_htt_stats_req(ar);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
|
@ -4586,7 +4586,7 @@ static const struct file_operations fops_htt_stats_reset = {
|
|||
.llseek = default_llseek,
|
||||
};
|
||||
|
||||
void ath11k_debug_htt_stats_init(struct ath11k *ar)
|
||||
void ath11k_debugfs_htt_stats_init(struct ath11k *ar)
|
||||
{
|
||||
spin_lock_init(&ar->debug.htt_stats.lock);
|
||||
debugfs_create_file("htt_stats_type", 0600, ar->debug.debugfs_pdev,
|
|
@ -1660,8 +1660,6 @@ struct htt_pdev_obss_pd_stats_tlv {
|
|||
u32 num_obss_tx_ppdu_failure;
|
||||
};
|
||||
|
||||
void ath11k_debug_htt_stats_init(struct ath11k *ar);
|
||||
|
||||
struct htt_ring_backpressure_stats_tlv {
|
||||
u32 pdev_id;
|
||||
u32 current_head_idx;
|
||||
|
@ -1687,4 +1685,9 @@ struct htt_ring_backpressure_stats_tlv {
|
|||
u32 backpressure_hist[5];
|
||||
};
|
||||
|
||||
void ath11k_debugfs_htt_stats_init(struct ath11k *ar);
|
||||
void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab,
|
||||
struct sk_buff *skb);
|
||||
int ath11k_debugfs_htt_stats_req(struct ath11k *ar);
|
||||
|
||||
#endif
|
|
@ -5,16 +5,16 @@
|
|||
|
||||
#include <linux/vmalloc.h>
|
||||
|
||||
#include "debugfs_sta.h"
|
||||
#include "core.h"
|
||||
#include "peer.h"
|
||||
#include "debug.h"
|
||||
#include "dp_tx.h"
|
||||
#include "debug_htt_stats.h"
|
||||
#include "debugfs_htt_stats.h"
|
||||
|
||||
void
|
||||
ath11k_accumulate_per_peer_tx_stats(struct ath11k_sta *arsta,
|
||||
struct ath11k_per_peer_tx_stats *peer_stats,
|
||||
u8 legacy_rate_idx)
|
||||
void ath11k_debugfs_sta_add_tx_stats(struct ath11k_sta *arsta,
|
||||
struct ath11k_per_peer_tx_stats *peer_stats,
|
||||
u8 legacy_rate_idx)
|
||||
{
|
||||
struct rate_info *txrate = &arsta->txrate;
|
||||
struct ath11k_htt_tx_stats *tx_stats;
|
||||
|
@ -125,9 +125,9 @@ ath11k_accumulate_per_peer_tx_stats(struct ath11k_sta *arsta,
|
|||
tx_stats->tx_duration += peer_stats->duration;
|
||||
}
|
||||
|
||||
void ath11k_update_per_peer_stats_from_txcompl(struct ath11k *ar,
|
||||
struct sk_buff *msdu,
|
||||
struct hal_tx_status *ts)
|
||||
void ath11k_debugfs_sta_update_txcompl(struct ath11k *ar,
|
||||
struct sk_buff *msdu,
|
||||
struct hal_tx_status *ts)
|
||||
{
|
||||
struct ath11k_base *ab = ar->ab;
|
||||
struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
|
||||
|
@ -200,7 +200,8 @@ void ath11k_update_per_peer_stats_from_txcompl(struct ath11k *ar,
|
|||
arsta->txrate.nss = arsta->last_txrate.nss;
|
||||
arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
|
||||
|
||||
ath11k_accumulate_per_peer_tx_stats(arsta, peer_stats, rate_idx);
|
||||
ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
|
||||
|
||||
err_out:
|
||||
spin_unlock_bh(&ab->base_lock);
|
||||
rcu_read_unlock();
|
||||
|
@ -428,7 +429,7 @@ ath11k_dbg_sta_open_htt_peer_stats(struct inode *inode, struct file *file)
|
|||
ar->debug.htt_stats.stats_req = stats_req;
|
||||
stats_req->type = ATH11K_DBG_HTT_EXT_STATS_PEER_INFO;
|
||||
memcpy(stats_req->peer_addr, sta->addr, ETH_ALEN);
|
||||
ret = ath11k_dbg_htt_stats_req(ar);
|
||||
ret = ath11k_debugfs_htt_stats_req(ar);
|
||||
mutex_unlock(&ar->conf_mutex);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
@ -820,15 +821,15 @@ static const struct file_operations fops_htt_peer_stats_reset = {
|
|||
.llseek = default_llseek,
|
||||
};
|
||||
|
||||
void ath11k_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta, struct dentry *dir)
|
||||
void ath11k_debugfs_sta_op_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta, struct dentry *dir)
|
||||
{
|
||||
struct ath11k *ar = hw->priv;
|
||||
|
||||
if (ath11k_debug_is_extd_tx_stats_enabled(ar))
|
||||
if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
|
||||
debugfs_create_file("tx_stats", 0400, dir, sta,
|
||||
&fops_tx_stats);
|
||||
if (ath11k_debug_is_extd_rx_stats_enabled(ar))
|
||||
if (ath11k_debugfs_is_extd_rx_stats_enabled(ar))
|
||||
debugfs_create_file("rx_stats", 0400, dir, sta,
|
||||
&fops_rx_stats);
|
||||
|
||||
|
|
|
@ -0,0 +1,44 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause-Clear */
|
||||
/*
|
||||
* Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _ATH11K_DEBUGFS_STA_H_
|
||||
#define _ATH11K_DEBUGFS_STA_H_
|
||||
|
||||
#include <net/mac80211.h>
|
||||
|
||||
#include "core.h"
|
||||
#include "hal_tx.h"
|
||||
|
||||
#ifdef CONFIG_ATH11K_DEBUGFS
|
||||
|
||||
void ath11k_debugfs_sta_op_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta, struct dentry *dir);
|
||||
void ath11k_debugfs_sta_add_tx_stats(struct ath11k_sta *arsta,
|
||||
struct ath11k_per_peer_tx_stats *peer_stats,
|
||||
u8 legacy_rate_idx);
|
||||
void ath11k_debugfs_sta_update_txcompl(struct ath11k *ar,
|
||||
struct sk_buff *msdu,
|
||||
struct hal_tx_status *ts);
|
||||
|
||||
#else /* CONFIG_ATH11K_DEBUGFS */
|
||||
|
||||
#define ath11k_debugfs_sta_op_add NULL
|
||||
|
||||
static inline void
|
||||
ath11k_debugfs_sta_add_tx_stats(struct ath11k_sta *arsta,
|
||||
struct ath11k_per_peer_tx_stats *peer_stats,
|
||||
u8 legacy_rate_idx)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void ath11k_debugfs_sta_update_txcompl(struct ath11k *ar,
|
||||
struct sk_buff *msdu,
|
||||
struct hal_tx_status *ts)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ATH11K_DEBUGFS */
|
||||
|
||||
#endif /* _ATH11K_DEBUGFS_STA_H_ */
|
|
@ -832,7 +832,7 @@ void ath11k_dp_pdev_free(struct ath11k_base *ab)
|
|||
for (i = 0; i < ab->num_radios; i++) {
|
||||
ar = ab->pdevs[i].ar;
|
||||
ath11k_dp_rx_pdev_free(ab, i);
|
||||
ath11k_debug_unregister(ar);
|
||||
ath11k_debugfs_unregister(ar);
|
||||
ath11k_dp_rx_pdev_mon_detach(ar);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -9,6 +9,8 @@
|
|||
#include <crypto/hash.h>
|
||||
#include "core.h"
|
||||
#include "debug.h"
|
||||
#include "debugfs_htt_stats.h"
|
||||
#include "debugfs_sta.h"
|
||||
#include "hal_desc.h"
|
||||
#include "hw.h"
|
||||
#include "dp_rx.h"
|
||||
|
@ -1433,9 +1435,8 @@ ath11k_update_per_peer_tx_stats(struct ath11k *ar,
|
|||
HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
|
||||
HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
|
||||
|
||||
if (ath11k_debug_is_extd_tx_stats_enabled(ar))
|
||||
ath11k_accumulate_per_peer_tx_stats(arsta,
|
||||
peer_stats, rate_idx);
|
||||
if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
|
||||
ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
|
||||
}
|
||||
|
||||
spin_unlock_bh(&ab->base_lock);
|
||||
|
@ -1511,7 +1512,7 @@ static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
|
|||
goto exit;
|
||||
}
|
||||
|
||||
if (ath11k_debug_is_pktlog_lite_mode_enabled(ar))
|
||||
if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
|
||||
trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
|
||||
|
||||
ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
|
||||
|
@ -1658,7 +1659,7 @@ void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
|
|||
ath11k_htt_pull_ppdu_stats(ab, skb);
|
||||
break;
|
||||
case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
|
||||
ath11k_dbg_htt_ext_stats_handler(ab, skb);
|
||||
ath11k_debugfs_htt_ext_stats_handler(ab, skb);
|
||||
break;
|
||||
case HTT_T2H_MSG_TYPE_PKTLOG:
|
||||
ath11k_htt_pktlog(ab, skb);
|
||||
|
@ -2909,7 +2910,7 @@ int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
|
|||
memset(&ppdu_info, 0, sizeof(ppdu_info));
|
||||
ppdu_info.peer_id = HAL_INVALID_PEERID;
|
||||
|
||||
if (ath11k_debug_is_pktlog_rx_stats_enabled(ar))
|
||||
if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar))
|
||||
trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE);
|
||||
|
||||
hal_status = ath11k_hal_rx_parse_mon_status(ab, &ppdu_info, skb);
|
||||
|
@ -2937,7 +2938,7 @@ int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
|
|||
arsta = (struct ath11k_sta *)peer->sta->drv_priv;
|
||||
ath11k_dp_rx_update_peer_stats(arsta, &ppdu_info);
|
||||
|
||||
if (ath11k_debug_is_pktlog_peer_valid(ar, peer->addr))
|
||||
if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
|
||||
trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE);
|
||||
|
||||
spin_unlock_bh(&ab->base_lock);
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
#include "core.h"
|
||||
#include "dp_tx.h"
|
||||
#include "debug.h"
|
||||
#include "debugfs_sta.h"
|
||||
#include "hw.h"
|
||||
#include "peer.h"
|
||||
|
||||
|
@ -457,7 +458,7 @@ static void ath11k_dp_tx_complete_msdu(struct ath11k *ar,
|
|||
(info->flags & IEEE80211_TX_CTL_NO_ACK))
|
||||
info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
|
||||
|
||||
if (ath11k_debug_is_extd_tx_stats_enabled(ar)) {
|
||||
if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) {
|
||||
if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) {
|
||||
if (ar->last_ppdu_id == 0) {
|
||||
ar->last_ppdu_id = ts->ppdu_id;
|
||||
|
@ -465,12 +466,12 @@ static void ath11k_dp_tx_complete_msdu(struct ath11k *ar,
|
|||
ar->cached_ppdu_id == ar->last_ppdu_id) {
|
||||
ar->cached_ppdu_id = ar->last_ppdu_id;
|
||||
ar->cached_stats.is_ampdu = true;
|
||||
ath11k_update_per_peer_stats_from_txcompl(ar, msdu, ts);
|
||||
ath11k_debugfs_sta_update_txcompl(ar, msdu, ts);
|
||||
memset(&ar->cached_stats, 0,
|
||||
sizeof(struct ath11k_per_peer_tx_stats));
|
||||
} else {
|
||||
ar->cached_stats.is_ampdu = false;
|
||||
ath11k_update_per_peer_stats_from_txcompl(ar, msdu, ts);
|
||||
ath11k_debugfs_sta_update_txcompl(ar, msdu, ts);
|
||||
memset(&ar->cached_stats, 0,
|
||||
sizeof(struct ath11k_per_peer_tx_stats));
|
||||
}
|
||||
|
|
|
@ -50,15 +50,6 @@ static struct sk_buff *ath11k_htc_build_tx_ctrl_skb(void *ab)
|
|||
return skb;
|
||||
}
|
||||
|
||||
static inline void ath11k_htc_restore_tx_skb(struct ath11k_htc *htc,
|
||||
struct sk_buff *skb)
|
||||
{
|
||||
struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb);
|
||||
|
||||
dma_unmap_single(htc->ab->dev, skb_cb->paddr, skb->len, DMA_TO_DEVICE);
|
||||
skb_pull(skb, sizeof(struct ath11k_htc_hdr));
|
||||
}
|
||||
|
||||
static void ath11k_htc_prepare_tx_skb(struct ath11k_htc_ep *ep,
|
||||
struct sk_buff *skb)
|
||||
{
|
||||
|
|
|
@ -74,7 +74,6 @@ static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab,
|
|||
config->beacon_tx_offload_max_vdev = 0x2;
|
||||
config->num_multicast_filter_entries = 0x20;
|
||||
config->num_wow_filters = 0x16;
|
||||
config->num_keep_alive_pattern = 0x1;
|
||||
config->num_keep_alive_pattern = 0;
|
||||
}
|
||||
|
||||
|
@ -104,7 +103,12 @@ static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab,
|
|||
config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
|
||||
config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
|
||||
config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
|
||||
config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
|
||||
|
||||
if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
|
||||
config->rx_decap_mode = TARGET_DECAP_MODE_RAW;
|
||||
else
|
||||
config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
|
||||
|
||||
config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
|
||||
config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
|
||||
config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
|
||||
|
|
|
@ -155,6 +155,7 @@ struct ath11k_hw_params {
|
|||
bool vdev_start_delay;
|
||||
bool htt_peer_map_v2;
|
||||
bool tcl_0_only;
|
||||
u8 spectral_fft_sz;
|
||||
};
|
||||
|
||||
struct ath11k_hw_ops {
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include "dp_rx.h"
|
||||
#include "testmode.h"
|
||||
#include "peer.h"
|
||||
#include "debugfs_sta.h"
|
||||
|
||||
#define CHAN2G(_channel, _freq, _flags) { \
|
||||
.band = NL80211_BAND_2GHZ, \
|
||||
|
@ -2967,7 +2968,7 @@ static int ath11k_mac_station_add(struct ath11k *ar,
|
|||
ath11k_dbg(ab, ATH11K_DBG_MAC, "Added peer: %pM for VDEV: %d\n",
|
||||
sta->addr, arvif->vdev_id);
|
||||
|
||||
if (ath11k_debug_is_extd_tx_stats_enabled(ar)) {
|
||||
if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) {
|
||||
arsta->tx_stats = kzalloc(sizeof(*arsta->tx_stats), GFP_KERNEL);
|
||||
if (!arsta->tx_stats) {
|
||||
ret = -ENOMEM;
|
||||
|
@ -4101,7 +4102,7 @@ static int ath11k_mac_config_mon_status_default(struct ath11k *ar, bool enable)
|
|||
|
||||
if (enable) {
|
||||
tlv_filter = ath11k_mac_mon_status_filter_default;
|
||||
tlv_filter.rx_filter = ath11k_debug_rx_filter(ar);
|
||||
tlv_filter.rx_filter = ath11k_debugfs_rx_filter(ar);
|
||||
}
|
||||
|
||||
for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
|
||||
|
@ -5867,7 +5868,7 @@ static const struct ieee80211_ops ath11k_ops = {
|
|||
.sta_statistics = ath11k_mac_op_sta_statistics,
|
||||
CFG80211_TESTMODE_CMD(ath11k_tm_cmd)
|
||||
#ifdef CONFIG_ATH11K_DEBUGFS
|
||||
.sta_add_debugfs = ath11k_sta_add_debugfs,
|
||||
.sta_add_debugfs = ath11k_debugfs_sta_op_add,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
@ -6226,7 +6227,7 @@ static int __ath11k_mac_register(struct ath11k *ar)
|
|||
goto err_free;
|
||||
}
|
||||
|
||||
ret = ath11k_debug_register(ar);
|
||||
ret = ath11k_debugfs_register(ar);
|
||||
if (ret) {
|
||||
ath11k_err(ar->ab, "debugfs registration failed: %d\n", ret);
|
||||
goto err_free;
|
||||
|
|
|
@ -17,8 +17,6 @@
|
|||
#define ATH11K_SPECTRAL_ATH11K_MIN_IB_BINS 32
|
||||
#define ATH11K_SPECTRAL_ATH11K_MAX_IB_BINS 256
|
||||
|
||||
#define ATH11K_SPECTRAL_SAMPLE_FFT_BIN_MASK 0xFF
|
||||
|
||||
#define ATH11K_SPECTRAL_SCAN_COUNT_MAX 4095
|
||||
|
||||
/* Max channel computed by sum of 2g and 5g band channels */
|
||||
|
@ -557,16 +555,16 @@ static u8 ath11k_spectral_get_max_exp(s8 max_index, u8 max_magnitude,
|
|||
return max_exp;
|
||||
}
|
||||
|
||||
static void ath11k_spectral_parse_16bit_fft(u8 *outbins, u8 *inbins, int num_bins)
|
||||
static void ath11k_spectral_parse_fft(u8 *outbins, u8 *inbins, int num_bins, u8 fft_sz)
|
||||
{
|
||||
int i;
|
||||
__le16 *data = (__le16 *)inbins;
|
||||
int i, j;
|
||||
|
||||
i = 0;
|
||||
j = 0;
|
||||
while (i < num_bins) {
|
||||
outbins[i] = (__le16_to_cpu(data[i])) &
|
||||
ATH11K_SPECTRAL_SAMPLE_FFT_BIN_MASK;
|
||||
outbins[i] = inbins[j];
|
||||
i++;
|
||||
j += fft_sz;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -588,6 +586,12 @@ int ath11k_spectral_process_fft(struct ath11k *ar,
|
|||
|
||||
lockdep_assert_held(&ar->spectral.lock);
|
||||
|
||||
if (!ab->hw_params.spectral_fft_sz) {
|
||||
ath11k_warn(ab, "invalid bin size type for hw rev %d\n",
|
||||
ab->hw_rev);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
tlv = (struct spectral_tlv *)data;
|
||||
tlv_len = FIELD_GET(SPECTRAL_TLV_HDR_LEN, __le32_to_cpu(tlv->header));
|
||||
/* convert Dword into bytes */
|
||||
|
@ -649,9 +653,8 @@ int ath11k_spectral_process_fft(struct ath11k *ar,
|
|||
freq = summary->meta.freq2;
|
||||
fft_sample->freq2 = __cpu_to_be16(freq);
|
||||
|
||||
ath11k_spectral_parse_16bit_fft(fft_sample->data,
|
||||
fft_report->bins,
|
||||
num_bins);
|
||||
ath11k_spectral_parse_fft(fft_sample->data, fft_report->bins, num_bins,
|
||||
ab->hw_params.spectral_fft_sz);
|
||||
|
||||
fft_sample->max_exp = ath11k_spectral_get_max_exp(fft_sample->max_index,
|
||||
search.peak_mag,
|
||||
|
@ -959,6 +962,9 @@ int ath11k_spectral_init(struct ath11k_base *ab)
|
|||
ab->wmi_ab.svc_map))
|
||||
return 0;
|
||||
|
||||
if (!ab->hw_params.spectral_fft_sz)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < ab->num_radios; i++) {
|
||||
ar = ab->pdevs[i].ar;
|
||||
sp = &ar->spectral;
|
||||
|
|
|
@ -3342,55 +3342,6 @@ int ath11k_wmi_cmd_init(struct ath11k_base *ab)
|
|||
memset(&init_param, 0, sizeof(init_param));
|
||||
memset(&config, 0, sizeof(config));
|
||||
|
||||
config.num_vdevs = ab->num_radios * TARGET_NUM_VDEVS;
|
||||
|
||||
if (ab->num_radios == 2) {
|
||||
config.num_peers = TARGET_NUM_PEERS(DBS);
|
||||
config.num_tids = TARGET_NUM_TIDS(DBS);
|
||||
} else if (ab->num_radios == 3) {
|
||||
config.num_peers = TARGET_NUM_PEERS(DBS_SBS);
|
||||
config.num_tids = TARGET_NUM_TIDS(DBS_SBS);
|
||||
} else {
|
||||
/* Control should not reach here */
|
||||
config.num_peers = TARGET_NUM_PEERS(SINGLE);
|
||||
config.num_tids = TARGET_NUM_TIDS(SINGLE);
|
||||
}
|
||||
config.num_offload_peers = TARGET_NUM_OFFLD_PEERS;
|
||||
config.num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS;
|
||||
config.num_peer_keys = TARGET_NUM_PEER_KEYS;
|
||||
config.ast_skid_limit = TARGET_AST_SKID_LIMIT;
|
||||
config.tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
|
||||
config.rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1;
|
||||
config.rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI;
|
||||
config.rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI;
|
||||
config.rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI;
|
||||
config.rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI;
|
||||
config.rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI;
|
||||
|
||||
if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
|
||||
config.rx_decap_mode = TARGET_DECAP_MODE_RAW;
|
||||
|
||||
config.scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS;
|
||||
config.bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV;
|
||||
config.roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV;
|
||||
config.roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES;
|
||||
config.num_mcast_groups = TARGET_NUM_MCAST_GROUPS;
|
||||
config.num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS;
|
||||
config.mcast2ucast_mode = TARGET_MCAST2UCAST_MODE;
|
||||
config.tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE;
|
||||
config.num_wds_entries = TARGET_NUM_WDS_ENTRIES;
|
||||
config.dma_burst_size = TARGET_DMA_BURST_SIZE;
|
||||
config.rx_skip_defrag_timeout_dup_detection_check =
|
||||
TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
|
||||
config.vow_config = TARGET_VOW_CONFIG;
|
||||
config.gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV;
|
||||
config.num_msdu_desc = TARGET_NUM_MSDU_DESC;
|
||||
config.beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD;
|
||||
config.rx_batchmode = TARGET_RX_BATCHMODE;
|
||||
config.peer_map_unmap_v2_support = 1;
|
||||
config.twt_ap_pdev_count = ab->num_radios;
|
||||
config.twt_ap_sta_count = 1000;
|
||||
|
||||
ab->hw_params.hw_ops->wmi_init_config(ab, &config);
|
||||
|
||||
memcpy(&wmi_sc->wlan_resource_config, &config, sizeof(config));
|
||||
|
@ -6301,7 +6252,7 @@ static void ath11k_peer_assoc_conf_event(struct ath11k_base *ab, struct sk_buff
|
|||
|
||||
static void ath11k_update_stats_event(struct ath11k_base *ab, struct sk_buff *skb)
|
||||
{
|
||||
ath11k_debug_fw_stats_process(ab, skb);
|
||||
ath11k_debugfs_fw_stats_process(ab, skb);
|
||||
}
|
||||
|
||||
/* PDEV_CTL_FAILSAFE_CHECK_EVENT is received from FW when the frequency scanned
|
||||
|
|
|
@ -161,33 +161,14 @@ static int reg_show(struct seq_file *seq, void *p)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct seq_operations register_seq_ops = {
|
||||
static const struct seq_operations registers_sops = {
|
||||
.start = reg_start,
|
||||
.next = reg_next,
|
||||
.stop = reg_stop,
|
||||
.show = reg_show
|
||||
};
|
||||
|
||||
static int open_file_registers(struct inode *inode, struct file *file)
|
||||
{
|
||||
struct seq_file *s;
|
||||
int res;
|
||||
res = seq_open(file, ®ister_seq_ops);
|
||||
if (res == 0) {
|
||||
s = file->private_data;
|
||||
s->private = inode->i_private;
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
static const struct file_operations fops_registers = {
|
||||
.open = open_file_registers,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = seq_release,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
DEFINE_SEQ_ATTRIBUTE(registers);
|
||||
|
||||
/* debugfs: beacons */
|
||||
|
||||
|
@ -1005,7 +986,7 @@ ath5k_debug_init_device(struct ath5k_hw *ah)
|
|||
return;
|
||||
|
||||
debugfs_create_file("debug", 0600, phydir, ah, &fops_debug);
|
||||
debugfs_create_file("registers", 0400, phydir, ah, &fops_registers);
|
||||
debugfs_create_file("registers", 0400, phydir, ah, ®isters_fops);
|
||||
debugfs_create_file("beacon", 0600, phydir, ah, &fops_beacon);
|
||||
debugfs_create_file("reset", 0200, phydir, ah, &fops_reset);
|
||||
debugfs_create_file("antenna", 0600, phydir, ah, &fops_antenna);
|
||||
|
|
|
@ -2639,6 +2639,11 @@ int ath6kl_wmi_delete_pstream_cmd(struct wmi *wmi, u8 if_idx, u8 traffic_class,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (tsid >= 16) {
|
||||
ath6kl_err("invalid tsid: %d\n", tsid);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
skb = ath6kl_wmi_get_new_buf(sizeof(*cmd));
|
||||
if (!skb)
|
||||
return -ENOMEM;
|
||||
|
|
|
@ -449,10 +449,19 @@ static void hif_usb_stop(void *hif_handle)
|
|||
spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
|
||||
|
||||
/* The pending URBs have to be canceled. */
|
||||
spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
|
||||
list_for_each_entry_safe(tx_buf, tx_buf_tmp,
|
||||
&hif_dev->tx.tx_pending, list) {
|
||||
usb_get_urb(tx_buf->urb);
|
||||
spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
|
||||
usb_kill_urb(tx_buf->urb);
|
||||
list_del(&tx_buf->list);
|
||||
usb_free_urb(tx_buf->urb);
|
||||
kfree(tx_buf->buf);
|
||||
kfree(tx_buf);
|
||||
spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
|
||||
}
|
||||
spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
|
||||
|
||||
usb_kill_anchored_urbs(&hif_dev->mgmt_submitted);
|
||||
}
|
||||
|
@ -762,27 +771,37 @@ static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev)
|
|||
struct tx_buf *tx_buf = NULL, *tx_buf_tmp = NULL;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
|
||||
list_for_each_entry_safe(tx_buf, tx_buf_tmp,
|
||||
&hif_dev->tx.tx_buf, list) {
|
||||
usb_get_urb(tx_buf->urb);
|
||||
spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
|
||||
usb_kill_urb(tx_buf->urb);
|
||||
list_del(&tx_buf->list);
|
||||
usb_free_urb(tx_buf->urb);
|
||||
kfree(tx_buf->buf);
|
||||
kfree(tx_buf);
|
||||
spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
|
||||
}
|
||||
spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
|
||||
|
||||
spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
|
||||
hif_dev->tx.flags |= HIF_USB_TX_FLUSH;
|
||||
spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
|
||||
|
||||
spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
|
||||
list_for_each_entry_safe(tx_buf, tx_buf_tmp,
|
||||
&hif_dev->tx.tx_pending, list) {
|
||||
usb_get_urb(tx_buf->urb);
|
||||
spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
|
||||
usb_kill_urb(tx_buf->urb);
|
||||
list_del(&tx_buf->list);
|
||||
usb_free_urb(tx_buf->urb);
|
||||
kfree(tx_buf->buf);
|
||||
kfree(tx_buf);
|
||||
spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
|
||||
}
|
||||
spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
|
||||
|
||||
usb_kill_anchored_urbs(&hif_dev->mgmt_submitted);
|
||||
}
|
||||
|
|
|
@ -726,7 +726,129 @@ enum pe_stats_mask {
|
|||
#define WCN36XX_HAL_CFG_AP_LINK_MONITOR_TIMEOUT 102
|
||||
#define WCN36XX_HAL_CFG_BTC_DWELL_TIME_MULTIPLIER 103
|
||||
#define WCN36XX_HAL_CFG_ENABLE_TDLS_OXYGEN_MODE 104
|
||||
#define WCN36XX_HAL_CFG_MAX_PARAMS 105
|
||||
#define WCN36XX_HAL_CFG_ENABLE_NAT_KEEP_ALIVE_FILTER 105
|
||||
#define WCN36XX_HAL_CFG_ENABLE_SAP_OBSS_PROT 106
|
||||
#define WCN36XX_HAL_CFG_PSPOLL_DATA_RECEP_TIMEOUT 107
|
||||
#define WCN36XX_HAL_CFG_TDLS_PUAPSD_BUFFER_STA_CAPABLE 108
|
||||
#define WCN36XX_HAL_CFG_TDLS_PUAPSD_MASK 109
|
||||
#define WCN36XX_HAL_CFG_TDLS_PUAPSD_INACTIVITY_TIME 110
|
||||
#define WCN36XX_HAL_CFG_TDLS_PUAPSD_RX_FRAME_THRESHOLD 111
|
||||
#define WCN36XX_HAL_CFG_ANTENNA_DIVERSITY 112
|
||||
#define WCN36XX_HAL_CFG_ATH_DISABLE 113
|
||||
#define WCN36XX_HAL_CFG_FLEXCONNECT_POWER_FACTOR 114
|
||||
#define WCN36XX_HAL_CFG_ENABLE_ADAPTIVE_RX_DRAIN 115
|
||||
#define WCN36XX_HAL_CFG_TDLS_OFF_CHANNEL_CAPABLE 116
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V1_WAN_FREQ 117
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V1_WLAN_FREQ 118
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V1_CONFIG 119
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V1_CONFIG2 120
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V2_WAN_FREQ 121
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V2_WLAN_FREQ 122
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V2_CONFIG 123
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V2_CONFIG2 124
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V3_WAN_FREQ 125
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V3_WLAN_FREQ 126
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V3_CONFIG 127
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V3_CONFIG2 128
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V4_WAN_FREQ 129
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V4_WLAN_FREQ 130
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V4_CONFIG 131
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V4_CONFIG2 132
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V5_WAN_FREQ 133
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V5_WLAN_FREQ 134
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V5_CONFIG 135
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V5_CONFIG2 136
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V6_WAN_FREQ 137
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V6_WLAN_FREQ 138
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V6_CONFIG 139
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V6_CONFIG2 140
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V7_WAN_FREQ 141
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V7_WLAN_FREQ 142
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V7_CONFIG 143
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V7_CONFIG2 144
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V8_WAN_FREQ 145
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V8_WLAN_FREQ 146
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V8_CONFIG 147
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V8_CONFIG2 148
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V9_WAN_FREQ 149
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V9_WLAN_FREQ 150
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V9_CONFIG 151
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V9_CONFIG2 152
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V10_WAN_FREQ 153
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V10_WLAN_FREQ 154
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V10_CONFIG 155
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_V10_CONFIG2 156
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_MODEM_BACKOFF 157
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG1 158
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG2 159
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG3 160
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG4 161
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG5 162
|
||||
#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG6 163
|
||||
#define WCN36XX_HAL_CFG_SAR_POWER_BACKOFF 164
|
||||
#define WCN36XX_HAL_CFG_GO_LINK_MONITOR_TIMEOUT 165
|
||||
#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_ACTIVE_WLAN_LEN 166
|
||||
#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_ACTIVE_BT_LEN 167
|
||||
#define WCN36XX_HAL_CFG_BTC_SAP_STATIC_OPP_ACTIVE_WLAN_LEN 168
|
||||
#define WCN36XX_HAL_CFG_BTC_SAP_STATIC_OPP_ACTIVE_BT_LEN 169
|
||||
#define WCN36XX_HAL_CFG_RMC_FIXED_RATE 170
|
||||
#define WCN36XX_HAL_CFG_ASD_PROBE_INTERVAL 171
|
||||
#define WCN36XX_HAL_CFG_ASD_TRIGGER_THRESHOLD 172
|
||||
#define WCN36XX_HAL_CFG_ASD_RTT_RSSI_HYST_THRESHOLD 173
|
||||
#define WCN36XX_HAL_CFG_BTC_CTS2S_ON_STA_DURING_SCO 174
|
||||
#define WCN36XX_HAL_CFG_SHORT_PREAMBLE 175
|
||||
#define WCN36XX_HAL_CFG_SHORT_SLOT_TIME 176
|
||||
#define WCN36XX_HAL_CFG_DELAYED_BA 177
|
||||
#define WCN36XX_HAL_CFG_IMMEDIATE_BA 178
|
||||
#define WCN36XX_HAL_CFG_DOT11_MODE 179
|
||||
#define WCN36XX_HAL_CFG_HT_CAPS 180
|
||||
#define WCN36XX_HAL_CFG_AMPDU_PARAMS 181
|
||||
#define WCN36XX_HAL_CFG_TX_BF_INFO 182
|
||||
#define WCN36XX_HAL_CFG_ASC_CAP_INFO 183
|
||||
#define WCN36XX_HAL_CFG_EXT_HT_CAPS 184
|
||||
#define WCN36XX_HAL_CFG_QOS_ENABLED 185
|
||||
#define WCN36XX_HAL_CFG_WME_ENABLED 186
|
||||
#define WCN36XX_HAL_CFG_WSM_ENABLED 187
|
||||
#define WCN36XX_HAL_CFG_WMM_ENABLED 188
|
||||
#define WCN36XX_HAL_CFG_UAPSD_PER_AC_BITMASK 189
|
||||
#define WCN36XX_HAL_CFG_MCS_RATES 190
|
||||
#define WCN36XX_HAL_CFG_VHT_CAPS 191
|
||||
#define WCN36XX_HAL_CFG_VHT_RX_SUPP_MCS 192
|
||||
#define WCN36XX_HAL_CFG_VHT_TX_SUPP_MCS 193
|
||||
#define WCN36XX_HAL_CFG_RA_FILTER_ENABLE 194
|
||||
#define WCN36XX_HAL_CFG_RA_RATE_LIMIT_INTERVAL 195
|
||||
#define WCN36XX_HAL_CFG_BTC_FATAL_HID_NSNIFF_BLK 196
|
||||
#define WCN36XX_HAL_CFG_BTC_CRITICAL_HID_NSNIFF_BLK 197
|
||||
#define WCN36XX_HAL_CFG_BTC_DYN_A2DP_TX_QUEUE_THOLD 198
|
||||
#define WCN36XX_HAL_CFG_BTC_DYN_OPP_TX_QUEUE_THOLD 199
|
||||
#define WCN36XX_HAL_CFG_LINK_FAIL_TIMEOUT 200
|
||||
#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_SP 201
|
||||
#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_RX_CNT 202
|
||||
#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_TX_CNT 203
|
||||
#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_RX_CNT_MEAS_WINDOW 204
|
||||
#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_TX_CNT_MEAS_WINDOW 205
|
||||
#define WCN36XX_HAL_CFG_MAX_PSPOLL_IN_WMM_UAPSD_PS_MODE 206
|
||||
#define WCN36XX_HAL_CFG_MAX_UAPSD_INACTIVITY_INTERVALS 207
|
||||
#define WCN36XX_HAL_CFG_ENABLE_DYNAMIC_WMMPS 208
|
||||
#define WCN36XX_HAL_CFG_BURST_MODE_BE_TXOP_VALUE 209
|
||||
#define WCN36XX_HAL_CFG_ENABLE_DYNAMIC_RA_START_RATE 210
|
||||
#define WCN36XX_HAL_CFG_BTC_FAST_WLAN_CONN_PREF 211
|
||||
#define WCN36XX_HAL_CFG_ENABLE_RTSCTS_HTVHT 212
|
||||
#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_IDLE_WLAN_LEN 213
|
||||
#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_IDLE_BT_LEN 214
|
||||
#define WCN36XX_HAL_CFG_LINK_FAIL_TX_CNT 215
|
||||
#define WCN36XX_HAL_CFG_TOGGLE_ARP_BDRATES 216
|
||||
#define WCN36XX_HAL_CFG_OPTIMIZE_CA_EVENT 217
|
||||
#define WCN36XX_HAL_CFG_EXT_SCAN_CONC_MODE 218
|
||||
#define WCN36XX_HAL_CFG_BAR_WAKEUP_HOST_DISABLE 219
|
||||
#define WCN36XX_HAL_CFG_SAR_BOFFSET_CORRECTION_ENABLE 220
|
||||
#define WCN36XX_HAL_CFG_UNITS_OF_BCN_WAIT_TIME 221
|
||||
#define WCN36XX_HAL_CFG_CONS_BCNMISS_COUNT 222
|
||||
#define WCN36XX_HAL_CFG_BTC_DISABLE_WLAN_LINK_CRITICAL 223
|
||||
#define WCN36XX_HAL_CFG_DISABLE_SCAN_DURING_SCO 224
|
||||
#define WCN36XX_HAL_CFG_TRIGGER_NULLFRAME_BEFORE_HB 225
|
||||
#define WCN36XX_HAL_CFG_ENABLE_POWERSAVE_OFFLOAD 226
|
||||
#define WCN36XX_HAL_CFG_MAX_PARAMS 227
|
||||
|
||||
/* Specify the starting bitrate, 11B and 11A/G rates can be specified in
|
||||
* multiples of 0.5 So for 5.5 mbps => 11. for MCS 0 - 7 rates, Bit 7 should
|
||||
|
@ -1592,9 +1714,15 @@ struct wcn36xx_hal_config_sta_params_v1 {
|
|||
u8 reserved:4;
|
||||
|
||||
/* These rates are the intersection of peer and self capabilities. */
|
||||
struct wcn36xx_hal_supported_rates supported_rates;
|
||||
struct wcn36xx_hal_supported_rates_v1 supported_rates;
|
||||
|
||||
u8 vht_capable;
|
||||
u8 vht_tx_channel_width_set;
|
||||
|
||||
} __packed;
|
||||
|
||||
#define WCN36XX_DIFF_STA_PARAMS_V1_NOVHT 10
|
||||
|
||||
struct wcn36xx_hal_config_sta_req_msg_v1 {
|
||||
struct wcn36xx_hal_msg_header header;
|
||||
struct wcn36xx_hal_config_sta_params_v1 sta_params;
|
||||
|
@ -2015,8 +2143,14 @@ struct wcn36xx_hal_config_bss_params_v1 {
|
|||
* "STA context"
|
||||
*/
|
||||
struct wcn36xx_hal_config_sta_params_v1 sta;
|
||||
|
||||
u8 vht_capable;
|
||||
u8 vht_tx_channel_width_set;
|
||||
|
||||
} __packed;
|
||||
|
||||
#define WCN36XX_DIFF_BSS_PARAMS_V1_NOVHT (WCN36XX_DIFF_STA_PARAMS_V1_NOVHT + 2)
|
||||
|
||||
struct wcn36xx_hal_config_bss_req_msg_v1 {
|
||||
struct wcn36xx_hal_msg_header header;
|
||||
struct wcn36xx_hal_config_bss_params_v1 bss_params;
|
||||
|
|
|
@ -39,10 +39,10 @@ MODULE_PARM_DESC(debug_mask, "Debugging mask");
|
|||
.max_power = 25, \
|
||||
}
|
||||
|
||||
#define CHAN5G(_freq, _idx) { \
|
||||
#define CHAN5G(_freq, _idx, _phy_val) { \
|
||||
.band = NL80211_BAND_5GHZ, \
|
||||
.center_freq = (_freq), \
|
||||
.hw_value = (_idx), \
|
||||
.hw_value = (_phy_val) << HW_VALUE_PHY_SHIFT | HW_VALUE_CHANNEL(_idx), \
|
||||
.max_power = 25, \
|
||||
}
|
||||
|
||||
|
@ -67,29 +67,29 @@ static struct ieee80211_channel wcn_2ghz_channels[] = {
|
|||
};
|
||||
|
||||
static struct ieee80211_channel wcn_5ghz_channels[] = {
|
||||
CHAN5G(5180, 36),
|
||||
CHAN5G(5200, 40),
|
||||
CHAN5G(5220, 44),
|
||||
CHAN5G(5240, 48),
|
||||
CHAN5G(5260, 52),
|
||||
CHAN5G(5280, 56),
|
||||
CHAN5G(5300, 60),
|
||||
CHAN5G(5320, 64),
|
||||
CHAN5G(5500, 100),
|
||||
CHAN5G(5520, 104),
|
||||
CHAN5G(5540, 108),
|
||||
CHAN5G(5560, 112),
|
||||
CHAN5G(5580, 116),
|
||||
CHAN5G(5600, 120),
|
||||
CHAN5G(5620, 124),
|
||||
CHAN5G(5640, 128),
|
||||
CHAN5G(5660, 132),
|
||||
CHAN5G(5700, 140),
|
||||
CHAN5G(5745, 149),
|
||||
CHAN5G(5765, 153),
|
||||
CHAN5G(5785, 157),
|
||||
CHAN5G(5805, 161),
|
||||
CHAN5G(5825, 165)
|
||||
CHAN5G(5180, 36, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW),
|
||||
CHAN5G(5200, 40, PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_LOW),
|
||||
CHAN5G(5220, 44, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH),
|
||||
CHAN5G(5240, 48, PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_HIGH),
|
||||
CHAN5G(5260, 52, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW),
|
||||
CHAN5G(5280, 56, PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_LOW),
|
||||
CHAN5G(5300, 60, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH),
|
||||
CHAN5G(5320, 64, PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_HIGH),
|
||||
CHAN5G(5500, 100, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW),
|
||||
CHAN5G(5520, 104, PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_LOW),
|
||||
CHAN5G(5540, 108, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH),
|
||||
CHAN5G(5560, 112, PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_HIGH),
|
||||
CHAN5G(5580, 116, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW),
|
||||
CHAN5G(5600, 120, PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_LOW),
|
||||
CHAN5G(5620, 124, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH),
|
||||
CHAN5G(5640, 128, PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_HIGH),
|
||||
CHAN5G(5660, 132, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW),
|
||||
CHAN5G(5700, 140, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH),
|
||||
CHAN5G(5745, 149, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW),
|
||||
CHAN5G(5765, 153, PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_LOW),
|
||||
CHAN5G(5785, 157, PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH),
|
||||
CHAN5G(5805, 161, PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_HIGH),
|
||||
CHAN5G(5825, 165, 0)
|
||||
};
|
||||
|
||||
#define RATE(_bitrate, _hw_rate, _flags) { \
|
||||
|
@ -766,7 +766,16 @@ static void wcn36xx_update_allowed_rates(struct ieee80211_sta *sta,
|
|||
sta->ht_cap.mcs.rx_mask,
|
||||
sizeof(sta->ht_cap.mcs.rx_mask));
|
||||
}
|
||||
|
||||
if (sta->vht_cap.vht_supported) {
|
||||
sta_priv->supported_rates.op_rate_mode = STA_11ac;
|
||||
sta_priv->supported_rates.vht_rx_mcs_map =
|
||||
sta->vht_cap.vht_mcs.rx_mcs_map;
|
||||
sta_priv->supported_rates.vht_tx_mcs_map =
|
||||
sta->vht_cap.vht_mcs.tx_mcs_map;
|
||||
}
|
||||
}
|
||||
|
||||
void wcn36xx_set_default_rates(struct wcn36xx_hal_supported_rates *rates)
|
||||
{
|
||||
u16 ofdm_rates[WCN36XX_HAL_NUM_OFDM_RATES] = {
|
||||
|
@ -793,6 +802,14 @@ void wcn36xx_set_default_rates(struct wcn36xx_hal_supported_rates *rates)
|
|||
sizeof(*ofdm_rates) * WCN36XX_HAL_NUM_OFDM_RATES);
|
||||
rates->supported_mcs_set[0] = 0xFF;
|
||||
}
|
||||
|
||||
void wcn36xx_set_default_rates_v1(struct wcn36xx_hal_supported_rates_v1 *rates)
|
||||
{
|
||||
rates->op_rate_mode = STA_11ac;
|
||||
rates->vht_rx_mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9;
|
||||
rates->vht_tx_mcs_map = IEEE80211_VHT_MCS_SUPPORT_0_9;
|
||||
}
|
||||
|
||||
static void wcn36xx_bss_info_changed(struct ieee80211_hw *hw,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_bss_conf *bss_conf,
|
||||
|
@ -1184,6 +1201,35 @@ static const struct ieee80211_ops wcn36xx_ops = {
|
|||
CFG80211_TESTMODE_CMD(wcn36xx_tm_cmd)
|
||||
};
|
||||
|
||||
static void
|
||||
wcn36xx_set_ieee80211_vht_caps(struct ieee80211_sta_vht_cap *vht_cap)
|
||||
{
|
||||
vht_cap->vht_supported = true;
|
||||
|
||||
vht_cap->cap = (IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895 |
|
||||
IEEE80211_VHT_CAP_SHORT_GI_80 |
|
||||
IEEE80211_VHT_CAP_RXSTBC_1 |
|
||||
IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
|
||||
IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
|
||||
3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
|
||||
7 << IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT);
|
||||
|
||||
vht_cap->vht_mcs.rx_mcs_map =
|
||||
cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 |
|
||||
IEEE80211_VHT_MCS_NOT_SUPPORTED << 2 |
|
||||
IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
|
||||
IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
|
||||
IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
|
||||
IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
|
||||
IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
|
||||
IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
|
||||
|
||||
vht_cap->vht_mcs.rx_highest = cpu_to_le16(433);
|
||||
vht_cap->vht_mcs.tx_highest = vht_cap->vht_mcs.rx_highest;
|
||||
|
||||
vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
|
||||
}
|
||||
|
||||
static int wcn36xx_init_ieee80211(struct wcn36xx *wcn)
|
||||
{
|
||||
static const u32 cipher_suites[] = {
|
||||
|
@ -1210,6 +1256,9 @@ static int wcn36xx_init_ieee80211(struct wcn36xx *wcn)
|
|||
if (wcn->rf_id != RF_IRIS_WCN3620)
|
||||
wcn->hw->wiphy->bands[NL80211_BAND_5GHZ] = &wcn_band_5ghz;
|
||||
|
||||
if (wcn->rf_id == RF_IRIS_WCN3680)
|
||||
wcn36xx_set_ieee80211_vht_caps(&wcn_band_5ghz.vht_cap);
|
||||
|
||||
wcn->hw->wiphy->max_scan_ssids = WCN36XX_MAX_SCAN_SSIDS;
|
||||
wcn->hw->wiphy->max_scan_ie_len = WCN36XX_MAX_SCAN_IE_LEN;
|
||||
|
||||
|
|
|
@ -80,6 +80,102 @@ static struct wcn36xx_cfg_val wcn36xx_cfg_vals[] = {
|
|||
WCN36XX_CFG_VAL(ENABLE_DYNAMIC_RA_START_RATE, 133), /* MCS 5 */
|
||||
};
|
||||
|
||||
static struct wcn36xx_cfg_val wcn3680_cfg_vals[] = {
|
||||
WCN36XX_CFG_VAL(CURRENT_TX_ANTENNA, 1),
|
||||
WCN36XX_CFG_VAL(CURRENT_RX_ANTENNA, 1),
|
||||
WCN36XX_CFG_VAL(LOW_GAIN_OVERRIDE, 0),
|
||||
WCN36XX_CFG_VAL(POWER_STATE_PER_CHAIN, 785),
|
||||
WCN36XX_CFG_VAL(CAL_PERIOD, 5),
|
||||
WCN36XX_CFG_VAL(CAL_CONTROL, 1),
|
||||
WCN36XX_CFG_VAL(PROXIMITY, 0),
|
||||
WCN36XX_CFG_VAL(NETWORK_DENSITY, 3),
|
||||
WCN36XX_CFG_VAL(MAX_MEDIUM_TIME, 4096),
|
||||
WCN36XX_CFG_VAL(MAX_MPDUS_IN_AMPDU, 64),
|
||||
WCN36XX_CFG_VAL(RTS_THRESHOLD, 2347),
|
||||
WCN36XX_CFG_VAL(SHORT_RETRY_LIMIT, 15),
|
||||
WCN36XX_CFG_VAL(LONG_RETRY_LIMIT, 15),
|
||||
WCN36XX_CFG_VAL(FRAGMENTATION_THRESHOLD, 8000),
|
||||
WCN36XX_CFG_VAL(DYNAMIC_THRESHOLD_ZERO, 5),
|
||||
WCN36XX_CFG_VAL(DYNAMIC_THRESHOLD_ONE, 10),
|
||||
WCN36XX_CFG_VAL(DYNAMIC_THRESHOLD_TWO, 15),
|
||||
WCN36XX_CFG_VAL(FIXED_RATE, 0),
|
||||
WCN36XX_CFG_VAL(RETRYRATE_POLICY, 4),
|
||||
WCN36XX_CFG_VAL(RETRYRATE_SECONDARY, 0),
|
||||
WCN36XX_CFG_VAL(RETRYRATE_TERTIARY, 0),
|
||||
WCN36XX_CFG_VAL(FORCE_POLICY_PROTECTION, 5),
|
||||
WCN36XX_CFG_VAL(FIXED_RATE_MULTICAST_24GHZ, 1),
|
||||
WCN36XX_CFG_VAL(FIXED_RATE_MULTICAST_5GHZ, 5),
|
||||
WCN36XX_CFG_VAL(DEFAULT_RATE_INDEX_24GHZ, 1),
|
||||
WCN36XX_CFG_VAL(DEFAULT_RATE_INDEX_5GHZ, 5),
|
||||
WCN36XX_CFG_VAL(MAX_BA_SESSIONS, 40),
|
||||
WCN36XX_CFG_VAL(PS_DATA_INACTIVITY_TIMEOUT, 200),
|
||||
WCN36XX_CFG_VAL(PS_ENABLE_BCN_FILTER, 1),
|
||||
WCN36XX_CFG_VAL(PS_ENABLE_RSSI_MONITOR, 1),
|
||||
WCN36XX_CFG_VAL(NUM_BEACON_PER_RSSI_AVERAGE, 20),
|
||||
WCN36XX_CFG_VAL(STATS_PERIOD, 10),
|
||||
WCN36XX_CFG_VAL(CFP_MAX_DURATION, 30000),
|
||||
WCN36XX_CFG_VAL(FRAME_TRANS_ENABLED, 0),
|
||||
WCN36XX_CFG_VAL(BA_THRESHOLD_HIGH, 128),
|
||||
WCN36XX_CFG_VAL(MAX_BA_BUFFERS, 2560),
|
||||
WCN36XX_CFG_VAL(DYNAMIC_PS_POLL_VALUE, 0),
|
||||
WCN36XX_CFG_VAL(TX_PWR_CTRL_ENABLE, 1),
|
||||
WCN36XX_CFG_VAL(ENABLE_CLOSE_LOOP, 1),
|
||||
WCN36XX_CFG_VAL(ENABLE_LPWR_IMG_TRANSITION, 0),
|
||||
WCN36XX_CFG_VAL(BTC_STATIC_LEN_LE_BT, 120000),
|
||||
WCN36XX_CFG_VAL(BTC_STATIC_LEN_LE_WLAN, 30000),
|
||||
WCN36XX_CFG_VAL(MAX_ASSOC_LIMIT, 10),
|
||||
WCN36XX_CFG_VAL(ENABLE_MCC_ADAPTIVE_SCHEDULER, 0),
|
||||
WCN36XX_CFG_VAL(TDLS_PUAPSD_MASK, 0),
|
||||
WCN36XX_CFG_VAL(TDLS_PUAPSD_BUFFER_STA_CAPABLE, 1),
|
||||
WCN36XX_CFG_VAL(TDLS_PUAPSD_INACTIVITY_TIME, 0),
|
||||
WCN36XX_CFG_VAL(TDLS_PUAPSD_RX_FRAME_THRESHOLD, 10),
|
||||
WCN36XX_CFG_VAL(TDLS_OFF_CHANNEL_CAPABLE, 1),
|
||||
WCN36XX_CFG_VAL(ENABLE_ADAPTIVE_RX_DRAIN, 1),
|
||||
WCN36XX_CFG_VAL(FLEXCONNECT_POWER_FACTOR, 0),
|
||||
WCN36XX_CFG_VAL(ANTENNA_DIVERSITY, 3),
|
||||
WCN36XX_CFG_VAL(ATH_DISABLE, 0),
|
||||
WCN36XX_CFG_VAL(BTC_STATIC_OPP_WLAN_ACTIVE_WLAN_LEN, 60000),
|
||||
WCN36XX_CFG_VAL(BTC_STATIC_OPP_WLAN_ACTIVE_BT_LEN, 90000),
|
||||
WCN36XX_CFG_VAL(BTC_SAP_STATIC_OPP_ACTIVE_WLAN_LEN, 30000),
|
||||
WCN36XX_CFG_VAL(BTC_SAP_STATIC_OPP_ACTIVE_BT_LEN, 30000),
|
||||
WCN36XX_CFG_VAL(ASD_PROBE_INTERVAL, 50),
|
||||
WCN36XX_CFG_VAL(ASD_TRIGGER_THRESHOLD, -60),
|
||||
WCN36XX_CFG_VAL(ASD_RTT_RSSI_HYST_THRESHOLD, 3),
|
||||
WCN36XX_CFG_VAL(BTC_CTS2S_ON_STA_DURING_SCO, 0),
|
||||
WCN36XX_CFG_VAL(RA_FILTER_ENABLE, 0),
|
||||
WCN36XX_CFG_VAL(RA_RATE_LIMIT_INTERVAL, 60),
|
||||
WCN36XX_CFG_VAL(BTC_FATAL_HID_NSNIFF_BLK, 2),
|
||||
WCN36XX_CFG_VAL(BTC_CRITICAL_HID_NSNIFF_BLK, 1),
|
||||
WCN36XX_CFG_VAL(BTC_DYN_A2DP_TX_QUEUE_THOLD, 0),
|
||||
WCN36XX_CFG_VAL(BTC_DYN_OPP_TX_QUEUE_THOLD, 1),
|
||||
WCN36XX_CFG_VAL(MAX_UAPSD_CONSEC_SP, 10),
|
||||
WCN36XX_CFG_VAL(MAX_UAPSD_CONSEC_RX_CNT, 50),
|
||||
WCN36XX_CFG_VAL(MAX_UAPSD_CONSEC_TX_CNT, 50),
|
||||
WCN36XX_CFG_VAL(MAX_UAPSD_CONSEC_TX_CNT_MEAS_WINDOW, 500),
|
||||
WCN36XX_CFG_VAL(MAX_UAPSD_CONSEC_RX_CNT_MEAS_WINDOW, 500),
|
||||
WCN36XX_CFG_VAL(MAX_PSPOLL_IN_WMM_UAPSD_PS_MODE, 0),
|
||||
WCN36XX_CFG_VAL(MAX_UAPSD_INACTIVITY_INTERVALS, 10),
|
||||
WCN36XX_CFG_VAL(ENABLE_DYNAMIC_WMMPS, 1),
|
||||
WCN36XX_CFG_VAL(BURST_MODE_BE_TXOP_VALUE, 0),
|
||||
WCN36XX_CFG_VAL(ENABLE_DYNAMIC_RA_START_RATE, 136),
|
||||
WCN36XX_CFG_VAL(BTC_FAST_WLAN_CONN_PREF, 1),
|
||||
WCN36XX_CFG_VAL(ENABLE_RTSCTS_HTVHT, 0),
|
||||
WCN36XX_CFG_VAL(BTC_STATIC_OPP_WLAN_IDLE_WLAN_LEN, 30000),
|
||||
WCN36XX_CFG_VAL(BTC_STATIC_OPP_WLAN_IDLE_BT_LEN, 120000),
|
||||
WCN36XX_CFG_VAL(LINK_FAIL_TX_CNT, 200),
|
||||
WCN36XX_CFG_VAL(TOGGLE_ARP_BDRATES, 0),
|
||||
WCN36XX_CFG_VAL(OPTIMIZE_CA_EVENT, 0),
|
||||
WCN36XX_CFG_VAL(EXT_SCAN_CONC_MODE, 0),
|
||||
WCN36XX_CFG_VAL(BAR_WAKEUP_HOST_DISABLE, 0),
|
||||
WCN36XX_CFG_VAL(SAR_BOFFSET_CORRECTION_ENABLE, 0),
|
||||
WCN36XX_CFG_VAL(BTC_DISABLE_WLAN_LINK_CRITICAL, 5),
|
||||
WCN36XX_CFG_VAL(DISABLE_SCAN_DURING_SCO, 2),
|
||||
WCN36XX_CFG_VAL(CONS_BCNMISS_COUNT, 0),
|
||||
WCN36XX_CFG_VAL(UNITS_OF_BCN_WAIT_TIME, 0),
|
||||
WCN36XX_CFG_VAL(TRIGGER_NULLFRAME_BEFORE_HB, 0),
|
||||
WCN36XX_CFG_VAL(ENABLE_POWERSAVE_OFFLOAD, 0),
|
||||
};
|
||||
|
||||
static int put_cfg_tlv_u32(struct wcn36xx *wcn, size_t *len, u32 id, u32 value)
|
||||
{
|
||||
struct wcn36xx_hal_cfg *entry;
|
||||
|
@ -122,6 +218,7 @@ static inline u8 is_cap_supported(unsigned long caps, unsigned long flag)
|
|||
{
|
||||
return caps & flag ? 1 : 0;
|
||||
}
|
||||
|
||||
static void wcn36xx_smd_set_bss_ht_params(struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta,
|
||||
struct wcn36xx_hal_config_bss_params *bss_params)
|
||||
|
@ -146,6 +243,15 @@ static void wcn36xx_smd_set_bss_ht_params(struct ieee80211_vif *vif,
|
|||
}
|
||||
}
|
||||
|
||||
static void
|
||||
wcn36xx_smd_set_bss_vht_params(struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta,
|
||||
struct wcn36xx_hal_config_bss_params_v1 *bss)
|
||||
{
|
||||
if (sta && sta->vht_cap.vht_supported)
|
||||
bss->vht_capable = 1;
|
||||
}
|
||||
|
||||
static void wcn36xx_smd_set_sta_ht_params(struct ieee80211_sta *sta,
|
||||
struct wcn36xx_hal_config_sta_params *sta_params)
|
||||
{
|
||||
|
@ -174,6 +280,37 @@ static void wcn36xx_smd_set_sta_ht_params(struct ieee80211_sta *sta,
|
|||
}
|
||||
}
|
||||
|
||||
static void wcn36xx_smd_set_sta_vht_params(struct wcn36xx *wcn,
|
||||
struct ieee80211_sta *sta,
|
||||
struct wcn36xx_hal_config_sta_params_v1 *sta_params)
|
||||
{
|
||||
if (sta->vht_cap.vht_supported) {
|
||||
unsigned long caps = sta->vht_cap.cap;
|
||||
|
||||
sta_params->vht_capable = sta->vht_cap.vht_supported;
|
||||
sta_params->vht_ldpc_enabled =
|
||||
is_cap_supported(caps, IEEE80211_VHT_CAP_RXLDPC);
|
||||
if (get_feat_caps(wcn->fw_feat_caps, MU_MIMO)) {
|
||||
sta_params->vht_tx_mu_beamformee_capable =
|
||||
is_cap_supported(caps, IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
|
||||
if (sta_params->vht_tx_mu_beamformee_capable)
|
||||
sta_params->vht_tx_bf_enabled = 1;
|
||||
} else {
|
||||
sta_params->vht_tx_mu_beamformee_capable = 0;
|
||||
}
|
||||
sta_params->vht_tx_channel_width_set = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void wcn36xx_smd_set_sta_ht_ldpc_params(struct ieee80211_sta *sta,
|
||||
struct wcn36xx_hal_config_sta_params_v1 *sta_params)
|
||||
{
|
||||
if (sta->ht_cap.ht_supported) {
|
||||
sta_params->ht_ldpc_enabled =
|
||||
is_cap_supported(sta->ht_cap.cap, IEEE80211_HT_CAP_LDPC_CODING);
|
||||
}
|
||||
}
|
||||
|
||||
static void wcn36xx_smd_set_sta_default_ht_params(
|
||||
struct wcn36xx_hal_config_sta_params *sta_params)
|
||||
{
|
||||
|
@ -190,6 +327,31 @@ static void wcn36xx_smd_set_sta_default_ht_params(
|
|||
sta_params->dsss_cck_mode_40mhz = 1;
|
||||
}
|
||||
|
||||
static void wcn36xx_smd_set_sta_default_vht_params(struct wcn36xx *wcn,
|
||||
struct wcn36xx_hal_config_sta_params_v1 *sta_params)
|
||||
{
|
||||
if (wcn->rf_id == RF_IRIS_WCN3680) {
|
||||
sta_params->vht_capable = 1;
|
||||
sta_params->vht_tx_mu_beamformee_capable = 1;
|
||||
} else {
|
||||
sta_params->vht_capable = 0;
|
||||
sta_params->vht_tx_mu_beamformee_capable = 0;
|
||||
}
|
||||
|
||||
sta_params->vht_ldpc_enabled = 0;
|
||||
sta_params->vht_tx_channel_width_set = 0;
|
||||
sta_params->vht_tx_bf_enabled = 0;
|
||||
}
|
||||
|
||||
static void wcn36xx_smd_set_sta_default_ht_ldpc_params(struct wcn36xx *wcn,
|
||||
struct wcn36xx_hal_config_sta_params_v1 *sta_params)
|
||||
{
|
||||
if (wcn->rf_id == RF_IRIS_WCN3680)
|
||||
sta_params->ht_ldpc_enabled = 1;
|
||||
else
|
||||
sta_params->ht_ldpc_enabled = 0;
|
||||
}
|
||||
|
||||
static void wcn36xx_smd_set_sta_params(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta,
|
||||
|
@ -242,9 +404,10 @@ static void wcn36xx_smd_set_sta_params(struct wcn36xx *wcn,
|
|||
sta_params->aid = sta_priv->aid;
|
||||
wcn36xx_smd_set_sta_ht_params(sta, sta_params);
|
||||
memcpy(&sta_params->supported_rates, &sta_priv->supported_rates,
|
||||
sizeof(sta_priv->supported_rates));
|
||||
sizeof(struct wcn36xx_hal_supported_rates));
|
||||
} else {
|
||||
wcn36xx_set_default_rates(&sta_params->supported_rates);
|
||||
wcn36xx_set_default_rates((struct wcn36xx_hal_supported_rates *)
|
||||
&sta_params->supported_rates);
|
||||
wcn36xx_smd_set_sta_default_ht_params(sta_params);
|
||||
}
|
||||
}
|
||||
|
@ -291,14 +454,20 @@ static void init_hal_msg(struct wcn36xx_hal_msg_header *hdr,
|
|||
hdr->len = msg_size + sizeof(*hdr);
|
||||
}
|
||||
|
||||
#define INIT_HAL_MSG(msg_body, type) \
|
||||
#define __INIT_HAL_MSG(msg_body, type, version) \
|
||||
do { \
|
||||
memset(&msg_body, 0, sizeof(msg_body)); \
|
||||
msg_body.header.msg_type = type; \
|
||||
msg_body.header.msg_version = WCN36XX_HAL_MSG_VERSION0; \
|
||||
msg_body.header.msg_version = version; \
|
||||
msg_body.header.len = sizeof(msg_body); \
|
||||
} while (0) \
|
||||
|
||||
#define INIT_HAL_MSG(msg_body, type) \
|
||||
__INIT_HAL_MSG(msg_body, type, WCN36XX_HAL_MSG_VERSION0)
|
||||
|
||||
#define INIT_HAL_MSG_V1(msg_body, type) \
|
||||
__INIT_HAL_MSG(msg_body, type, WCN36XX_HAL_MSG_VERSION1)
|
||||
|
||||
#define INIT_HAL_PTT_MSG(p_msg_body, ppt_msg_len) \
|
||||
do { \
|
||||
memset(p_msg_body, 0, sizeof(*p_msg_body) + ppt_msg_len); \
|
||||
|
@ -450,6 +619,8 @@ int wcn36xx_smd_start(struct wcn36xx *wcn)
|
|||
int ret;
|
||||
int i;
|
||||
size_t len;
|
||||
int cfg_elements;
|
||||
static struct wcn36xx_cfg_val *cfg_vals;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_START_REQ);
|
||||
|
@ -462,9 +633,17 @@ int wcn36xx_smd_start(struct wcn36xx *wcn)
|
|||
body = (struct wcn36xx_hal_mac_start_req_msg *)wcn->hal_buf;
|
||||
len = body->header.len;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(wcn36xx_cfg_vals); i++) {
|
||||
ret = put_cfg_tlv_u32(wcn, &len, wcn36xx_cfg_vals[i].cfg_id,
|
||||
wcn36xx_cfg_vals[i].value);
|
||||
if (wcn->rf_id == RF_IRIS_WCN3680) {
|
||||
cfg_vals = wcn3680_cfg_vals;
|
||||
cfg_elements = ARRAY_SIZE(wcn3680_cfg_vals);
|
||||
} else {
|
||||
cfg_vals = wcn36xx_cfg_vals;
|
||||
cfg_elements = ARRAY_SIZE(wcn36xx_cfg_vals);
|
||||
}
|
||||
|
||||
for (i = 0; i < cfg_elements; i++) {
|
||||
ret = put_cfg_tlv_u32(wcn, &len, cfg_vals[i].cfg_id,
|
||||
cfg_vals[i].value);
|
||||
if (ret)
|
||||
goto out;
|
||||
}
|
||||
|
@ -694,8 +873,10 @@ int wcn36xx_smd_start_hw_scan(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
|||
|
||||
msg_body->num_channel = min_t(u8, req->n_channels,
|
||||
sizeof(msg_body->channels));
|
||||
for (i = 0; i < msg_body->num_channel; i++)
|
||||
msg_body->channels[i] = req->channels[i]->hw_value;
|
||||
for (i = 0; i < msg_body->num_channel; i++) {
|
||||
msg_body->channels[i] =
|
||||
HW_VALUE_CHANNEL(req->channels[i]->hw_value);
|
||||
}
|
||||
|
||||
msg_body->header.len -= WCN36XX_MAX_SCAN_IE_LEN;
|
||||
|
||||
|
@ -1183,6 +1364,31 @@ static void wcn36xx_smd_convert_sta_to_v1(struct wcn36xx *wcn,
|
|||
v1->p2p = orig->p2p;
|
||||
}
|
||||
|
||||
static void
|
||||
wcn36xx_smd_set_sta_params_v1(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta,
|
||||
struct wcn36xx_hal_config_sta_params_v1 *sta_par)
|
||||
{
|
||||
struct wcn36xx_sta *sta_priv = NULL;
|
||||
struct wcn36xx_hal_config_sta_params sta_par_v0;
|
||||
|
||||
wcn36xx_smd_set_sta_params(wcn, vif, sta, &sta_par_v0);
|
||||
wcn36xx_smd_convert_sta_to_v1(wcn, &sta_par_v0, sta_par);
|
||||
|
||||
if (sta) {
|
||||
sta_priv = wcn36xx_sta_to_priv(sta);
|
||||
wcn36xx_smd_set_sta_vht_params(wcn, sta, sta_par);
|
||||
wcn36xx_smd_set_sta_ht_ldpc_params(sta, sta_par);
|
||||
memcpy(&sta_par->supported_rates, &sta_priv->supported_rates,
|
||||
sizeof(sta_par->supported_rates));
|
||||
} else {
|
||||
wcn36xx_set_default_rates_v1(&sta_par->supported_rates);
|
||||
wcn36xx_smd_set_sta_default_vht_params(wcn, sta_par);
|
||||
wcn36xx_smd_set_sta_default_ht_ldpc_params(wcn, sta_par);
|
||||
}
|
||||
}
|
||||
|
||||
static int wcn36xx_smd_config_sta_rsp(struct wcn36xx *wcn,
|
||||
struct ieee80211_sta *sta,
|
||||
void *buf,
|
||||
|
@ -1217,53 +1423,69 @@ static int wcn36xx_smd_config_sta_rsp(struct wcn36xx *wcn,
|
|||
}
|
||||
|
||||
static int wcn36xx_smd_config_sta_v1(struct wcn36xx *wcn,
|
||||
const struct wcn36xx_hal_config_sta_req_msg *orig)
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta)
|
||||
{
|
||||
struct wcn36xx_hal_config_sta_req_msg_v1 msg_body;
|
||||
struct wcn36xx_hal_config_sta_params_v1 *sta = &msg_body.sta_params;
|
||||
struct wcn36xx_hal_config_sta_params_v1 *sta_params;
|
||||
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_CONFIG_STA_REQ);
|
||||
if (wcn->rf_id == RF_IRIS_WCN3680) {
|
||||
INIT_HAL_MSG_V1(msg_body, WCN36XX_HAL_CONFIG_STA_REQ);
|
||||
} else {
|
||||
INIT_HAL_MSG(msg_body, WCN36XX_HAL_CONFIG_STA_REQ);
|
||||
msg_body.header.len -= WCN36XX_DIFF_STA_PARAMS_V1_NOVHT;
|
||||
}
|
||||
|
||||
wcn36xx_smd_convert_sta_to_v1(wcn, &orig->sta_params,
|
||||
&msg_body.sta_params);
|
||||
sta_params = &msg_body.sta_params;
|
||||
|
||||
wcn36xx_smd_set_sta_params_v1(wcn, vif, sta, sta_params);
|
||||
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"hal config sta v1 action %d sta_index %d bssid_index %d bssid %pM type %d mac %pM aid %d\n",
|
||||
sta->action, sta->sta_index, sta->bssid_index,
|
||||
sta->bssid, sta->type, sta->mac, sta->aid);
|
||||
sta_params->action, sta_params->sta_index, sta_params->bssid_index,
|
||||
sta_params->bssid, sta_params->type, sta_params->mac, sta_params->aid);
|
||||
|
||||
return wcn36xx_smd_send_and_wait(wcn, msg_body.header.len);
|
||||
}
|
||||
|
||||
int wcn36xx_smd_config_sta(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta)
|
||||
static int wcn36xx_smd_config_sta_v0(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta)
|
||||
{
|
||||
struct wcn36xx_hal_config_sta_req_msg msg;
|
||||
struct wcn36xx_hal_config_sta_params *sta_params;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
INIT_HAL_MSG(msg, WCN36XX_HAL_CONFIG_STA_REQ);
|
||||
|
||||
sta_params = &msg.sta_params;
|
||||
|
||||
wcn36xx_smd_set_sta_params(wcn, vif, sta, sta_params);
|
||||
|
||||
if (!wcn36xx_is_fw_version(wcn, 1, 2, 2, 24)) {
|
||||
ret = wcn36xx_smd_config_sta_v1(wcn, &msg);
|
||||
} else {
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg);
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, msg);
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"hal config sta action %d sta_index %d bssid_index %d bssid %pM type %d mac %pM aid %d\n",
|
||||
sta_params->action, sta_params->sta_index,
|
||||
sta_params->bssid_index, sta_params->bssid,
|
||||
sta_params->type, sta_params->mac, sta_params->aid);
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"hal config sta action %d sta_index %d bssid_index %d bssid %pM type %d mac %pM aid %d\n",
|
||||
sta_params->action, sta_params->sta_index,
|
||||
sta_params->bssid_index, sta_params->bssid,
|
||||
sta_params->type, sta_params->mac, sta_params->aid);
|
||||
|
||||
return wcn36xx_smd_send_and_wait(wcn, msg.header.len);
|
||||
}
|
||||
|
||||
int wcn36xx_smd_config_sta(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta)
|
||||
{
|
||||
int ret;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
|
||||
if (!wcn36xx_is_fw_version(wcn, 1, 2, 2, 24))
|
||||
ret = wcn36xx_smd_config_sta_v1(wcn, vif, sta);
|
||||
else
|
||||
ret = wcn36xx_smd_config_sta_v0(wcn, vif, sta);
|
||||
|
||||
ret = wcn36xx_smd_send_and_wait(wcn, msg.header.len);
|
||||
}
|
||||
if (ret) {
|
||||
wcn36xx_err("Sending hal_config_sta failed\n");
|
||||
goto out;
|
||||
|
@ -1281,174 +1503,15 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int wcn36xx_smd_config_bss_v1(struct wcn36xx *wcn,
|
||||
const struct wcn36xx_hal_config_bss_req_msg *orig)
|
||||
static void wcn36xx_smd_set_bss_params(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta,
|
||||
const u8 *bssid,
|
||||
bool update,
|
||||
struct wcn36xx_hal_config_bss_params *bss)
|
||||
{
|
||||
struct wcn36xx_hal_config_bss_req_msg_v1 *msg_body;
|
||||
struct wcn36xx_hal_config_bss_params_v1 *bss;
|
||||
struct wcn36xx_hal_config_sta_params_v1 *sta;
|
||||
int ret;
|
||||
|
||||
msg_body = kzalloc(sizeof(*msg_body), GFP_KERNEL);
|
||||
if (!msg_body)
|
||||
return -ENOMEM;
|
||||
|
||||
INIT_HAL_MSG((*msg_body), WCN36XX_HAL_CONFIG_BSS_REQ);
|
||||
|
||||
bss = &msg_body->bss_params;
|
||||
sta = &bss->sta;
|
||||
|
||||
/* convert orig to v1 */
|
||||
memcpy(bss->bssid, &orig->bss_params.bssid, ETH_ALEN);
|
||||
memcpy(bss->self_mac_addr, &orig->bss_params.self_mac_addr, ETH_ALEN);
|
||||
|
||||
bss->bss_type = orig->bss_params.bss_type;
|
||||
bss->oper_mode = orig->bss_params.oper_mode;
|
||||
bss->nw_type = orig->bss_params.nw_type;
|
||||
|
||||
bss->short_slot_time_supported =
|
||||
orig->bss_params.short_slot_time_supported;
|
||||
bss->lla_coexist = orig->bss_params.lla_coexist;
|
||||
bss->llb_coexist = orig->bss_params.llb_coexist;
|
||||
bss->llg_coexist = orig->bss_params.llg_coexist;
|
||||
bss->ht20_coexist = orig->bss_params.ht20_coexist;
|
||||
bss->lln_non_gf_coexist = orig->bss_params.lln_non_gf_coexist;
|
||||
|
||||
bss->lsig_tx_op_protection_full_support =
|
||||
orig->bss_params.lsig_tx_op_protection_full_support;
|
||||
bss->rifs_mode = orig->bss_params.rifs_mode;
|
||||
bss->beacon_interval = orig->bss_params.beacon_interval;
|
||||
bss->dtim_period = orig->bss_params.dtim_period;
|
||||
bss->tx_channel_width_set = orig->bss_params.tx_channel_width_set;
|
||||
bss->oper_channel = orig->bss_params.oper_channel;
|
||||
bss->ext_channel = orig->bss_params.ext_channel;
|
||||
|
||||
bss->reserved = orig->bss_params.reserved;
|
||||
|
||||
memcpy(&bss->ssid, &orig->bss_params.ssid,
|
||||
sizeof(orig->bss_params.ssid));
|
||||
|
||||
bss->action = orig->bss_params.action;
|
||||
bss->rateset = orig->bss_params.rateset;
|
||||
bss->ht = orig->bss_params.ht;
|
||||
bss->obss_prot_enabled = orig->bss_params.obss_prot_enabled;
|
||||
bss->rmf = orig->bss_params.rmf;
|
||||
bss->ht_oper_mode = orig->bss_params.ht_oper_mode;
|
||||
bss->dual_cts_protection = orig->bss_params.dual_cts_protection;
|
||||
|
||||
bss->max_probe_resp_retry_limit =
|
||||
orig->bss_params.max_probe_resp_retry_limit;
|
||||
bss->hidden_ssid = orig->bss_params.hidden_ssid;
|
||||
bss->proxy_probe_resp = orig->bss_params.proxy_probe_resp;
|
||||
bss->edca_params_valid = orig->bss_params.edca_params_valid;
|
||||
|
||||
memcpy(&bss->acbe, &orig->bss_params.acbe,
|
||||
sizeof(orig->bss_params.acbe));
|
||||
memcpy(&bss->acbk, &orig->bss_params.acbk,
|
||||
sizeof(orig->bss_params.acbk));
|
||||
memcpy(&bss->acvi, &orig->bss_params.acvi,
|
||||
sizeof(orig->bss_params.acvi));
|
||||
memcpy(&bss->acvo, &orig->bss_params.acvo,
|
||||
sizeof(orig->bss_params.acvo));
|
||||
|
||||
bss->ext_set_sta_key_param_valid =
|
||||
orig->bss_params.ext_set_sta_key_param_valid;
|
||||
|
||||
memcpy(&bss->ext_set_sta_key_param,
|
||||
&orig->bss_params.ext_set_sta_key_param,
|
||||
sizeof(orig->bss_params.acvo));
|
||||
|
||||
bss->wcn36xx_hal_persona = orig->bss_params.wcn36xx_hal_persona;
|
||||
bss->spectrum_mgt_enable = orig->bss_params.spectrum_mgt_enable;
|
||||
bss->tx_mgmt_power = orig->bss_params.tx_mgmt_power;
|
||||
bss->max_tx_power = orig->bss_params.max_tx_power;
|
||||
|
||||
wcn36xx_smd_convert_sta_to_v1(wcn, &orig->bss_params.sta, sta);
|
||||
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, (*msg_body));
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"hal config bss v1 bssid %pM self_mac_addr %pM bss_type %d oper_mode %d nw_type %d\n",
|
||||
bss->bssid, bss->self_mac_addr, bss->bss_type,
|
||||
bss->oper_mode, bss->nw_type);
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"- sta bssid %pM action %d sta_index %d bssid_index %d aid %d type %d mac %pM\n",
|
||||
sta->bssid, sta->action, sta->sta_index,
|
||||
sta->bssid_index, sta->aid, sta->type, sta->mac);
|
||||
|
||||
ret = wcn36xx_smd_send_and_wait(wcn, msg_body->header.len);
|
||||
kfree(msg_body);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static int wcn36xx_smd_config_bss_rsp(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta,
|
||||
void *buf,
|
||||
size_t len)
|
||||
{
|
||||
struct wcn36xx_hal_config_bss_rsp_msg *rsp;
|
||||
struct wcn36xx_hal_config_bss_rsp_params *params;
|
||||
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
|
||||
|
||||
if (len < sizeof(*rsp))
|
||||
return -EINVAL;
|
||||
|
||||
rsp = (struct wcn36xx_hal_config_bss_rsp_msg *)buf;
|
||||
params = &rsp->bss_rsp_params;
|
||||
|
||||
if (params->status != WCN36XX_FW_MSG_RESULT_SUCCESS) {
|
||||
wcn36xx_warn("hal config bss response failure: %d\n",
|
||||
params->status);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"hal config bss rsp status %d bss_idx %d dpu_desc_index %d"
|
||||
" sta_idx %d self_idx %d bcast_idx %d mac %pM"
|
||||
" power %d ucast_dpu_signature %d\n",
|
||||
params->status, params->bss_index, params->dpu_desc_index,
|
||||
params->bss_sta_index, params->bss_self_sta_index,
|
||||
params->bss_bcast_sta_idx, params->mac,
|
||||
params->tx_mgmt_power, params->ucast_dpu_signature);
|
||||
|
||||
vif_priv->bss_index = params->bss_index;
|
||||
|
||||
if (sta) {
|
||||
struct wcn36xx_sta *sta_priv = wcn36xx_sta_to_priv(sta);
|
||||
sta_priv->bss_sta_index = params->bss_sta_index;
|
||||
sta_priv->bss_dpu_desc_index = params->dpu_desc_index;
|
||||
}
|
||||
|
||||
vif_priv->self_ucast_dpu_sign = params->ucast_dpu_signature;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int wcn36xx_smd_config_bss(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta, const u8 *bssid,
|
||||
bool update)
|
||||
{
|
||||
struct wcn36xx_hal_config_bss_req_msg *msg;
|
||||
struct wcn36xx_hal_config_bss_params *bss;
|
||||
struct wcn36xx_hal_config_sta_params *sta_params;
|
||||
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
|
||||
int ret;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
msg = kzalloc(sizeof(*msg), GFP_KERNEL);
|
||||
if (!msg) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
INIT_HAL_MSG((*msg), WCN36XX_HAL_CONFIG_BSS_REQ);
|
||||
|
||||
bss = &msg->bss_params;
|
||||
sta_params = &bss->sta;
|
||||
|
||||
WARN_ON(is_zero_ether_addr(bssid));
|
||||
|
||||
memcpy(&bss->bssid, bssid, ETH_ALEN);
|
||||
|
@ -1502,7 +1565,6 @@ int wcn36xx_smd_config_bss(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
|||
bss->ext_channel = IEEE80211_HT_PARAM_CHA_SEC_NONE;
|
||||
|
||||
bss->reserved = 0;
|
||||
wcn36xx_smd_set_sta_params(wcn, vif, sta, sta_params);
|
||||
|
||||
/* wcn->ssid is only valid in AP and IBSS mode */
|
||||
bss->ssid.length = vif_priv->ssid.length;
|
||||
|
@ -1527,6 +1589,154 @@ int wcn36xx_smd_config_bss(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
|||
bss->action = update;
|
||||
|
||||
vif_priv->bss_type = bss->bss_type;
|
||||
}
|
||||
|
||||
static int wcn36xx_smd_config_bss_v1(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta_80211,
|
||||
const u8 *bssid,
|
||||
bool update)
|
||||
{
|
||||
struct wcn36xx_hal_config_bss_req_msg_v1 *msg_body;
|
||||
struct wcn36xx_hal_config_bss_params_v1 *bss;
|
||||
struct wcn36xx_hal_config_bss_params bss_v0;
|
||||
struct wcn36xx_hal_config_sta_params_v1 *sta;
|
||||
struct cfg80211_chan_def *chandef;
|
||||
int ret;
|
||||
|
||||
msg_body = kzalloc(sizeof(*msg_body), GFP_KERNEL);
|
||||
if (!msg_body)
|
||||
return -ENOMEM;
|
||||
|
||||
if (wcn->rf_id == RF_IRIS_WCN3680) {
|
||||
INIT_HAL_MSG_V1((*msg_body), WCN36XX_HAL_CONFIG_BSS_REQ);
|
||||
} else {
|
||||
INIT_HAL_MSG((*msg_body), WCN36XX_HAL_CONFIG_BSS_REQ);
|
||||
msg_body->header.len -= WCN36XX_DIFF_BSS_PARAMS_V1_NOVHT;
|
||||
}
|
||||
|
||||
bss = &msg_body->bss_params;
|
||||
sta = &bss->sta;
|
||||
|
||||
memset(&bss_v0, 0x00, sizeof(bss_v0));
|
||||
wcn36xx_smd_set_bss_params(wcn, vif, sta_80211, bssid, update, &bss_v0);
|
||||
wcn36xx_smd_set_sta_params_v1(wcn, vif, sta_80211, sta);
|
||||
|
||||
/* convert orig to v1 */
|
||||
memcpy(bss->bssid, &bss_v0.bssid, ETH_ALEN);
|
||||
memcpy(bss->self_mac_addr, &bss_v0.self_mac_addr, ETH_ALEN);
|
||||
|
||||
bss->bss_type = bss_v0.bss_type;
|
||||
bss->oper_mode = bss_v0.oper_mode;
|
||||
bss->nw_type = bss_v0.nw_type;
|
||||
|
||||
bss->short_slot_time_supported =
|
||||
bss_v0.short_slot_time_supported;
|
||||
bss->lla_coexist = bss_v0.lla_coexist;
|
||||
bss->llb_coexist = bss_v0.llb_coexist;
|
||||
bss->llg_coexist = bss_v0.llg_coexist;
|
||||
bss->ht20_coexist = bss_v0.ht20_coexist;
|
||||
bss->lln_non_gf_coexist = bss_v0.lln_non_gf_coexist;
|
||||
|
||||
bss->lsig_tx_op_protection_full_support =
|
||||
bss_v0.lsig_tx_op_protection_full_support;
|
||||
bss->rifs_mode = bss_v0.rifs_mode;
|
||||
bss->beacon_interval = bss_v0.beacon_interval;
|
||||
bss->dtim_period = bss_v0.dtim_period;
|
||||
bss->tx_channel_width_set = bss_v0.tx_channel_width_set;
|
||||
bss->oper_channel = bss_v0.oper_channel;
|
||||
|
||||
if (wcn->hw->conf.chandef.width == NL80211_CHAN_WIDTH_80) {
|
||||
chandef = &wcn->hw->conf.chandef;
|
||||
bss->ext_channel = HW_VALUE_PHY(chandef->chan->hw_value);
|
||||
} else {
|
||||
bss->ext_channel = bss_v0.ext_channel;
|
||||
}
|
||||
|
||||
bss->reserved = bss_v0.reserved;
|
||||
|
||||
memcpy(&bss->ssid, &bss_v0.ssid,
|
||||
sizeof(bss_v0.ssid));
|
||||
|
||||
bss->action = bss_v0.action;
|
||||
bss->rateset = bss_v0.rateset;
|
||||
bss->ht = bss_v0.ht;
|
||||
bss->obss_prot_enabled = bss_v0.obss_prot_enabled;
|
||||
bss->rmf = bss_v0.rmf;
|
||||
bss->ht_oper_mode = bss_v0.ht_oper_mode;
|
||||
bss->dual_cts_protection = bss_v0.dual_cts_protection;
|
||||
|
||||
bss->max_probe_resp_retry_limit =
|
||||
bss_v0.max_probe_resp_retry_limit;
|
||||
bss->hidden_ssid = bss_v0.hidden_ssid;
|
||||
bss->proxy_probe_resp = bss_v0.proxy_probe_resp;
|
||||
bss->edca_params_valid = bss_v0.edca_params_valid;
|
||||
|
||||
memcpy(&bss->acbe, &bss_v0.acbe,
|
||||
sizeof(bss_v0.acbe));
|
||||
memcpy(&bss->acbk, &bss_v0.acbk,
|
||||
sizeof(bss_v0.acbk));
|
||||
memcpy(&bss->acvi, &bss_v0.acvi,
|
||||
sizeof(bss_v0.acvi));
|
||||
memcpy(&bss->acvo, &bss_v0.acvo,
|
||||
sizeof(bss_v0.acvo));
|
||||
|
||||
bss->ext_set_sta_key_param_valid =
|
||||
bss_v0.ext_set_sta_key_param_valid;
|
||||
|
||||
memcpy(&bss->ext_set_sta_key_param,
|
||||
&bss_v0.ext_set_sta_key_param,
|
||||
sizeof(bss_v0.acvo));
|
||||
|
||||
bss->wcn36xx_hal_persona = bss_v0.wcn36xx_hal_persona;
|
||||
bss->spectrum_mgt_enable = bss_v0.spectrum_mgt_enable;
|
||||
bss->tx_mgmt_power = bss_v0.tx_mgmt_power;
|
||||
bss->max_tx_power = bss_v0.max_tx_power;
|
||||
|
||||
wcn36xx_smd_set_bss_vht_params(vif, sta_80211, bss);
|
||||
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, (*msg_body));
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"hal config bss v1 bssid %pM self_mac_addr %pM bss_type %d oper_mode %d nw_type %d\n",
|
||||
bss->bssid, bss->self_mac_addr, bss->bss_type,
|
||||
bss->oper_mode, bss->nw_type);
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"- sta bssid %pM action %d sta_index %d bssid_index %d aid %d type %d mac %pM\n",
|
||||
sta->bssid, sta->action, sta->sta_index,
|
||||
sta->bssid_index, sta->aid, sta->type, sta->mac);
|
||||
|
||||
ret = wcn36xx_smd_send_and_wait(wcn, msg_body->header.len);
|
||||
kfree(msg_body);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int wcn36xx_smd_config_bss_v0(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta,
|
||||
const u8 *bssid,
|
||||
bool update)
|
||||
{
|
||||
struct wcn36xx_hal_config_bss_req_msg *msg;
|
||||
struct wcn36xx_hal_config_bss_params *bss;
|
||||
struct wcn36xx_hal_config_sta_params *sta_params;
|
||||
int ret;
|
||||
|
||||
msg = kzalloc(sizeof(*msg), GFP_KERNEL);
|
||||
if (!msg)
|
||||
return -ENOMEM;
|
||||
|
||||
INIT_HAL_MSG((*msg), WCN36XX_HAL_CONFIG_BSS_REQ);
|
||||
|
||||
bss = &msg->bss_params;
|
||||
sta_params = &bss->sta;
|
||||
|
||||
wcn36xx_smd_set_bss_params(wcn, vif, sta, bssid, update, bss);
|
||||
wcn36xx_smd_set_sta_params(wcn, vif, sta, sta_params);
|
||||
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, (*msg));
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"hal config bss bssid %pM self_mac_addr %pM bss_type %d oper_mode %d nw_type %d\n",
|
||||
|
@ -1540,13 +1750,69 @@ int wcn36xx_smd_config_bss(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
|||
sta_params->aid, sta_params->type,
|
||||
sta_params->mac);
|
||||
|
||||
if (!wcn36xx_is_fw_version(wcn, 1, 2, 2, 24)) {
|
||||
ret = wcn36xx_smd_config_bss_v1(wcn, msg);
|
||||
} else {
|
||||
PREPARE_HAL_BUF(wcn->hal_buf, (*msg));
|
||||
ret = wcn36xx_smd_send_and_wait(wcn, msg->header.len);
|
||||
kfree(msg);
|
||||
|
||||
ret = wcn36xx_smd_send_and_wait(wcn, msg->header.len);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int wcn36xx_smd_config_bss_rsp(struct wcn36xx *wcn,
|
||||
struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta,
|
||||
void *buf,
|
||||
size_t len)
|
||||
{
|
||||
struct wcn36xx_hal_config_bss_rsp_msg *rsp;
|
||||
struct wcn36xx_hal_config_bss_rsp_params *params;
|
||||
struct wcn36xx_vif *vif_priv = wcn36xx_vif_to_priv(vif);
|
||||
|
||||
if (len < sizeof(*rsp))
|
||||
return -EINVAL;
|
||||
|
||||
rsp = (struct wcn36xx_hal_config_bss_rsp_msg *)buf;
|
||||
params = &rsp->bss_rsp_params;
|
||||
|
||||
if (params->status != WCN36XX_FW_MSG_RESULT_SUCCESS) {
|
||||
wcn36xx_warn("hal config bss response failure: %d\n",
|
||||
params->status);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
wcn36xx_dbg(WCN36XX_DBG_HAL,
|
||||
"hal config bss rsp status %d bss_idx %d dpu_desc_index %d"
|
||||
" sta_idx %d self_idx %d bcast_idx %d mac %pM"
|
||||
" power %d ucast_dpu_signature %d\n",
|
||||
params->status, params->bss_index, params->dpu_desc_index,
|
||||
params->bss_sta_index, params->bss_self_sta_index,
|
||||
params->bss_bcast_sta_idx, params->mac,
|
||||
params->tx_mgmt_power, params->ucast_dpu_signature);
|
||||
|
||||
vif_priv->bss_index = params->bss_index;
|
||||
|
||||
if (sta) {
|
||||
struct wcn36xx_sta *sta_priv = wcn36xx_sta_to_priv(sta);
|
||||
sta_priv->bss_sta_index = params->bss_sta_index;
|
||||
sta_priv->bss_dpu_desc_index = params->dpu_desc_index;
|
||||
}
|
||||
|
||||
vif_priv->self_ucast_dpu_sign = params->ucast_dpu_signature;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int wcn36xx_smd_config_bss(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
||||
struct ieee80211_sta *sta, const u8 *bssid,
|
||||
bool update)
|
||||
{
|
||||
int ret;
|
||||
|
||||
mutex_lock(&wcn->hal_mutex);
|
||||
|
||||
if (!wcn36xx_is_fw_version(wcn, 1, 2, 2, 24))
|
||||
ret = wcn36xx_smd_config_bss_v1(wcn, vif, sta, bssid, update);
|
||||
else
|
||||
ret = wcn36xx_smd_config_bss_v0(wcn, vif, sta, bssid, update);
|
||||
|
||||
if (ret) {
|
||||
wcn36xx_err("Sending hal_config_bss failed\n");
|
||||
goto out;
|
||||
|
@ -1556,12 +1822,10 @@ int wcn36xx_smd_config_bss(struct wcn36xx *wcn, struct ieee80211_vif *vif,
|
|||
sta,
|
||||
wcn->hal_buf,
|
||||
wcn->hal_rsp_len);
|
||||
if (ret) {
|
||||
if (ret)
|
||||
wcn36xx_err("hal_config_bss response failed err=%d\n", ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
kfree(msg);
|
||||
mutex_unlock(&wcn->hal_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
@ -1928,6 +2192,7 @@ out:
|
|||
mutex_unlock(&wcn->hal_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int wcn36xx_smd_set_power_params(struct wcn36xx *wcn, bool ignore_dtim)
|
||||
{
|
||||
struct wcn36xx_hal_set_power_params_req_msg msg_body;
|
||||
|
@ -1957,6 +2222,7 @@ out:
|
|||
mutex_unlock(&wcn->hal_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Notice: This function should be called after associated, or else it
|
||||
* will be invalid
|
||||
*/
|
||||
|
@ -2636,6 +2902,7 @@ static void wcn36xx_ind_smd_work(struct work_struct *work)
|
|||
kfree(hal_ind_msg);
|
||||
}
|
||||
}
|
||||
|
||||
int wcn36xx_smd_open(struct wcn36xx *wcn)
|
||||
{
|
||||
wcn->hal_ind_wq = create_freezable_workqueue("wcn36xx_smd_ind");
|
||||
|
|
|
@ -83,7 +83,11 @@ enum wcn36xx_ampdu_state {
|
|||
WCN36XX_AMPDU_OPERATIONAL,
|
||||
};
|
||||
|
||||
#define WCN36XX_HW_CHANNEL(__wcn) (__wcn->hw->conf.chandef.chan->hw_value)
|
||||
#define HW_VALUE_PHY_SHIFT 8
|
||||
#define HW_VALUE_PHY(hw_value) ((hw_value) >> HW_VALUE_PHY_SHIFT)
|
||||
#define HW_VALUE_CHANNEL(hw_value) ((hw_value) & 0xFF)
|
||||
#define WCN36XX_HW_CHANNEL(__wcn)\
|
||||
HW_VALUE_CHANNEL(__wcn->hw->conf.chandef.chan->hw_value)
|
||||
#define WCN36XX_BAND(__wcn) (__wcn->hw->conf.chandef.chan->band)
|
||||
#define WCN36XX_CENTER_FREQ(__wcn) (__wcn->hw->conf.chandef.chan->center_freq)
|
||||
#define WCN36XX_LISTEN_INTERVAL(__wcn) (__wcn->hw->conf.listen_interval)
|
||||
|
@ -169,7 +173,7 @@ struct wcn36xx_sta {
|
|||
u8 bss_dpu_desc_index;
|
||||
bool is_data_encrypted;
|
||||
/* Rates */
|
||||
struct wcn36xx_hal_supported_rates supported_rates;
|
||||
struct wcn36xx_hal_supported_rates_v1 supported_rates;
|
||||
|
||||
spinlock_t ampdu_lock; /* protects next two fields */
|
||||
enum wcn36xx_ampdu_state ampdu_state[16];
|
||||
|
@ -271,6 +275,7 @@ static inline bool wcn36xx_is_fw_version(struct wcn36xx *wcn,
|
|||
wcn->fw_revision == revision);
|
||||
}
|
||||
void wcn36xx_set_default_rates(struct wcn36xx_hal_supported_rates *rates);
|
||||
void wcn36xx_set_default_rates_v1(struct wcn36xx_hal_supported_rates_v1 *rates);
|
||||
|
||||
static inline
|
||||
struct ieee80211_sta *wcn36xx_priv_to_sta(struct wcn36xx_sta *sta_priv)
|
||||
|
|
Loading…
Reference in New Issue