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spi: spi-mtk-nor: improve device table for adding more capabilities 

Define a structure for adding more capabilities.
Add a item extra_dummy_bit for new SoCs, due to design changed.

Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
Signed-off-by: Zhen Zhang <zhen.zhang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220118142820.2729-3-guochun.mao@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Guochun Mao 2022-01-18 22:28:18 +08:00 committed by Mark Brown
parent 66fda8bdc3
commit 5b177234e9
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 39 additions and 9 deletions
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48
drivers/spi/spi-mtk-nor.c
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@ -95,6 +95,17 @@
#define CLK_TO_US(sp, clkcnt) DIV_ROUND_UP(clkcnt, sp->spi_freq / 1000000)
struct mtk_nor_caps {
u8 dma_bits;
/* extra_dummy_bit is adding for the IP of new SoCs.
* Some new SoCs modify the timing of fetching registers' values
* and IDs of nor flash, they need a extra_dummy_bit which can add
* more clock cycles for fetching data.
*/
u8 extra_dummy_bit;
};
struct mtk_nor {
struct spi_controller *ctlr;
struct device *dev;
@ -109,6 +120,7 @@ struct mtk_nor {
bool has_irq;
bool high_dma;
struct completion op_done;
const struct mtk_nor_caps *caps;
};
static inline void mtk_nor_rmw(struct mtk_nor *sp, u32 reg, u32 set, u32 clr)
@ -554,7 +566,12 @@ static int mtk_nor_spi_mem_prg(struct mtk_nor *sp, const struct spi_mem_op *op)
}
// trigger op
writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
if (rx_len)
writel(prg_len * BITS_PER_BYTE + sp->caps->extra_dummy_bit,
sp->base + MTK_NOR_REG_PRG_CNT);
else
writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
ret = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_PROGRAM,
prg_len * BITS_PER_BYTE);
if (ret)
@ -743,9 +760,19 @@ static const struct spi_controller_mem_ops mtk_nor_mem_ops = {
.exec_op = mtk_nor_exec_op
};
const struct mtk_nor_caps mtk_nor_caps_mt8173 = {
.dma_bits = 32,
.extra_dummy_bit = 0,
};
const struct mtk_nor_caps mtk_nor_caps_mt8192 = {
.dma_bits = 36,
.extra_dummy_bit = 0,
};
static const struct of_device_id mtk_nor_match[] = {
{ .compatible = "mediatek,mt8192-nor", .data = (void *)36 },
{ .compatible = "mediatek,mt8173-nor", .data = (void *)32 },
{ .compatible = "mediatek,mt8173-nor", .data = &mtk_nor_caps_mt8173 },
{ .compatible = "mediatek,mt8192-nor", .data = &mtk_nor_caps_mt8192 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_nor_match);
@ -754,10 +781,10 @@ static int mtk_nor_probe(struct platform_device *pdev)
{
struct spi_controller *ctlr;
struct mtk_nor *sp;
struct mtk_nor_caps *caps;
void __iomem *base;
struct clk *spi_clk, *ctlr_clk, *axi_clk;
int ret, irq;
unsigned long dma_bits;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@ -775,10 +802,12 @@ static int mtk_nor_probe(struct platform_device *pdev)
if (IS_ERR(axi_clk))
return PTR_ERR(axi_clk);
dma_bits = (unsigned long)of_device_get_match_data(&pdev->dev);
if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits))) {
dev_err(&pdev->dev, "failed to set dma mask(%lu)\n", dma_bits);
return -EINVAL;
caps = (struct mtk_nor_caps *)of_device_get_match_data(&pdev->dev);
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(caps->dma_bits));
if (ret) {
dev_err(&pdev->dev, "failed to set dma mask(%u)\n", caps->dma_bits);
return ret;
}
ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
@ -808,7 +837,8 @@ static int mtk_nor_probe(struct platform_device *pdev)
sp->spi_clk = spi_clk;
sp->ctlr_clk = ctlr_clk;
sp->axi_clk = axi_clk;
sp->high_dma = (dma_bits > 32);
sp->caps = caps;
sp->high_dma = caps->dma_bits > 32;
sp->buffer = dmam_alloc_coherent(&pdev->dev,
MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
&sp->buffer_dma, GFP_KERNEL);