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drm/i915/gen9: Extend dmc debug mask to include cores 

Cores need to be included into the debug mask. We don't exactly
know what it does but the spec says it must be enabled. So obey.

v2: Cores should be only set for BXT (Imre, Art)

Cc: Imre Deak <imre.deak@intel.com>
Cc: Runyan, Arthur J <arthur.j.runyan@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1455877564-5128-1-git-send-email-mika.kuoppala@intel.com
This commit is contained in:
Mika Kuoppala 2016-02-19 12:26:04 +02:00 committed by Imre Deak
parent 779cb5d3dd
commit 5b076889f6
2 changed files with 11 additions and 6 deletions
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1
drivers/gpu/drm/i915/i915_reg.h
View File

@ -7568,6 +7568,7 @@ enum skl_disp_power_wells {
#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
#define DC_STATE_DEBUG _MMIO(0x45520) #define DC_STATE_DEBUG _MMIO(0x45520)
#define DC_STATE_DEBUG_MASK_CORES (1<<0)
#define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1) #define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,

16
drivers/gpu/drm/i915/intel_runtime_pm.c
View File

@ -456,15 +456,19 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
*/ */
} }
static void gen9_set_dc_state_debugmask_memory_up( static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
struct drm_i915_private *dev_priv)
{ {
uint32_t val; uint32_t val, mask;
mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
if (IS_BROXTON(dev_priv))
mask |= DC_STATE_DEBUG_MASK_CORES;
/* The below bit doesn't need to be cleared ever afterwards */ /* The below bit doesn't need to be cleared ever afterwards */
val = I915_READ(DC_STATE_DEBUG); val = I915_READ(DC_STATE_DEBUG);
if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { if ((val & mask) != mask) {
val |= DC_STATE_DEBUG_MASK_MEMORY_UP; val |= mask;
I915_WRITE(DC_STATE_DEBUG, val); I915_WRITE(DC_STATE_DEBUG, val);
POSTING_READ(DC_STATE_DEBUG); POSTING_READ(DC_STATE_DEBUG);
} }
@ -526,7 +530,7 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
state = DC_STATE_EN_UPTO_DC5; state = DC_STATE_EN_UPTO_DC5;
if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK) if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
gen9_set_dc_state_debugmask_memory_up(dev_priv); gen9_set_dc_state_debugmask(dev_priv);
val = I915_READ(DC_STATE_EN); val = I915_READ(DC_STATE_EN);
DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",