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MIPS: cevt-r4k: Offset the value used to clear compare interrupt 

In c0_compare_int_usable we clear compare interrupt by write value
just read out from counter to compare register.

However sometimes if those all instructions are graduated together
then it's possible that at the time compare register is written, the
counter haven't progressed, thus the interrupt is triggered again.

It also applies to QEMU that instructions is executed significantly
faster then counter.

Offset the value used to clear interrupt by one to prevent that happen.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Jiaxun Yang 2023-02-27 18:46:14 +00:00 committed by Thomas Bogendoerfer
parent fea8826d5f
commit 5ae7e037de
1 changed files with 2 additions and 2 deletions
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4
arch/mips/kernel/cevt-r4k.c
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@ -200,7 +200,7 @@ int c0_compare_int_usable(void)
*/
if (c0_compare_int_pending()) {
cnt = read_c0_count();
write_c0_compare(cnt);
write_c0_compare(cnt - 1);
back_to_back_c0_hazard();
while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
if (!c0_compare_int_pending())
@ -228,7 +228,7 @@ int c0_compare_int_usable(void)
if (!c0_compare_int_pending())
return 0;
cnt = read_c0_count();
write_c0_compare(cnt);
write_c0_compare(cnt - 1);
back_to_back_c0_hazard();
while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
if (!c0_compare_int_pending())