ARC: mm: PAE40 support
This is the first working implementation of 40-bit physical address extension on ARCv2. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
parent
25d464183c
commit
5a364c2a17
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@ -453,6 +453,21 @@ config HIGHMEM
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kernel. Enable this to potentially allow access to rest of 2G and PAE
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in future
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config ARC_HAS_PAE40
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bool "Support for the 40-bit Physical Address Extension"
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default n
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depends on ISA_ARCV2
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select HIGHMEM
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help
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Enable access to physical memory beyond 4G, only supported on
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ARC cores with 40 bit Physical Addressing support
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config ARCH_PHYS_ADDR_T_64BIT
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def_bool ARC_HAS_PAE40
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config ARCH_DMA_ADDR_T_64BIT
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bool
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config ARC_CURR_IN_REG
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bool "Dedicate Register r25 for current_task pointer"
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default y
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@ -65,6 +65,7 @@ extern int ioc_exists;
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#if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4)
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#define ARC_REG_IC_PTAG 0x1E
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#endif
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#define ARC_REG_IC_PTAG_HI 0x1F
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/* Bit val in IC_CTRL */
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#define IC_CTRL_CACHE_DISABLE 0x1
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@ -77,6 +78,7 @@ extern int ioc_exists;
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#define ARC_REG_DC_FLSH 0x4B
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#define ARC_REG_DC_FLDL 0x4C
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#define ARC_REG_DC_PTAG 0x5C
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#define ARC_REG_DC_PTAG_HI 0x5F
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/* Bit val in DC_CTRL */
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#define DC_CTRL_INV_MODE_FLUSH 0x40
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@ -24,6 +24,7 @@
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#if (CONFIG_ARC_MMU_VER < 4)
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#define ARC_REG_TLBPD0 0x405
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#define ARC_REG_TLBPD1 0x406
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#define ARC_REG_TLBPD1HI 0 /* Dummy: allows code sharing with ARC700 */
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#define ARC_REG_TLBINDEX 0x407
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#define ARC_REG_TLBCOMMAND 0x408
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#define ARC_REG_PID 0x409
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@ -31,6 +32,7 @@
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#else
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#define ARC_REG_TLBPD0 0x460
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#define ARC_REG_TLBPD1 0x461
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#define ARC_REG_TLBPD1HI 0x463
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#define ARC_REG_TLBINDEX 0x464
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#define ARC_REG_TLBCOMMAND 0x465
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#define ARC_REG_PID 0x468
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@ -83,6 +85,11 @@ void arc_mmu_init(void);
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extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
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void read_decode_mmu_bcr(void);
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static inline int is_pae40_enabled(void)
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{
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return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
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}
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#endif /* !__ASSEMBLY__ */
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#endif
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@ -56,7 +56,11 @@ typedef struct {
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#else /* !STRICT_MM_TYPECHECKS */
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#ifdef CONFIG_ARC_HAS_PAE40
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typedef unsigned long long pte_t;
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#else
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typedef unsigned long pte_t;
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#endif
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typedef unsigned long pgd_t;
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typedef unsigned long pgprot_t;
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@ -49,7 +49,7 @@ pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t ptep)
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static inline int __get_order_pgd(void)
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{
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return get_order(PTRS_PER_PGD * 4);
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return get_order(PTRS_PER_PGD * sizeof(pgd_t));
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}
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static inline pgd_t *pgd_alloc(struct mm_struct *mm)
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@ -87,7 +87,7 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
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static inline int __get_order_pte(void)
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{
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return get_order(PTRS_PER_PTE * 4);
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return get_order(PTRS_PER_PTE * sizeof(pte_t));
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}
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static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
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@ -110,7 +110,7 @@ pte_alloc_one(struct mm_struct *mm, unsigned long address)
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pte_pg = (pgtable_t)__get_free_pages(GFP_KERNEL | __GFP_REPEAT, __get_order_pte());
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if (!pte_pg)
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return 0;
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memzero((void *)pte_pg, PTRS_PER_PTE * 4);
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memzero((void *)pte_pg, PTRS_PER_PTE * sizeof(pte_t));
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page = virt_to_page(pte_pg);
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if (!pgtable_page_ctor(page)) {
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__free_page(page);
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@ -134,7 +134,12 @@
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/* Masks for actual TLB "PD"s */
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#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT | _PAGE_HW_SZ)
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#define PTE_BITS_RWX (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)
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#ifdef CONFIG_ARC_HAS_PAE40
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#define PTE_BITS_NON_RWX_IN_PD1 (0xff00000000 | PAGE_MASK | _PAGE_CACHEABLE)
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#else
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#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE)
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#endif
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/**************************************************************************
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* Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
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@ -272,7 +277,8 @@ static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
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#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
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#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
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#define pfn_pte(pfn, prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
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#define pfn_pte(pfn, prot) (__pte(((pte_t)(pfn) << PAGE_SHIFT) | \
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pgprot_val(prot)))
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#define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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/*
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@ -253,6 +253,10 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
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}
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}
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/*
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* For ARC700 MMUv3 I-cache and D-cache flushes
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* Also reused for HS38 aliasing I-cache configuration
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*/
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static inline
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void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
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unsigned long sz, const int op)
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@ -289,6 +293,16 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
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if (full_page)
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write_aux_reg(aux_tag, paddr);
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/*
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* This is technically for MMU v4, using the MMU v3 programming model
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* Special work for HS38 aliasing I-cache configuratino with PAE40
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* - upper 8 bits of paddr need to be written into PTAG_HI
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* - (and needs to be written before the lower 32 bits)
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* Note that PTAG_HI is hoisted outside the line loop
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*/
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if (is_pae40_enabled() && op == OP_INV_IC)
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write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
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while (num_lines-- > 0) {
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if (!full_page) {
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write_aux_reg(aux_tag, paddr);
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@ -301,11 +315,17 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
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}
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/*
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* In HS38x (MMU v4), although icache is VIPT, only paddr is needed for cache
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* maintenance ops (in IVIL reg), as long as icache doesn't alias.
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* In HS38x (MMU v4), I-cache is VIPT (can alias), D-cache is PIPT
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* Here's how cache ops are implemented
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*
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* For Aliasing icache, vaddr is also needed (in IVIL), while paddr is
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* specified in PTAG (similar to MMU v3)
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* - D-cache: only paddr needed (in DC_IVDL/DC_FLDL)
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* - I-cache Non Aliasing: Despite VIPT, only paddr needed (in IC_IVIL)
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* - I-cache Aliasing: Both vaddr and paddr needed (in IC_IVIL, IC_PTAG
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* respectively, similar to MMU v3 programming model, hence
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* __cache_line_loop_v3() is used)
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*
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* If PAE40 is enabled, independent of aliasing considerations, the higher bits
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* needs to be written into PTAG_HI
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*/
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static inline
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void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
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@ -335,6 +355,22 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
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num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
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/*
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* For HS38 PAE40 configuration
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* - upper 8 bits of paddr need to be written into PTAG_HI
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* - (and needs to be written before the lower 32 bits)
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*/
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if (is_pae40_enabled()) {
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if (cacheop == OP_INV_IC)
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/*
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* Non aliasing I-cache in HS38,
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* aliasing I-cache handled in __cache_line_loop_v3()
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*/
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write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
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else
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write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
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}
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while (num_lines-- > 0) {
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write_aux_reg(aux_cmd, paddr);
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paddr += L1_CACHE_BYTES;
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@ -109,6 +109,10 @@ DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
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static inline void __tlb_entry_erase(void)
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{
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write_aux_reg(ARC_REG_TLBPD1, 0);
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if (is_pae40_enabled())
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write_aux_reg(ARC_REG_TLBPD1HI, 0);
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write_aux_reg(ARC_REG_TLBPD0, 0);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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}
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@ -182,7 +186,7 @@ static void utlb_invalidate(void)
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}
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static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
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static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
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{
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unsigned int idx;
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@ -225,10 +229,14 @@ static void tlb_entry_erase(unsigned int vaddr_n_asid)
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBDeleteEntry);
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}
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static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
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static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
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{
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write_aux_reg(ARC_REG_TLBPD0, pd0);
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write_aux_reg(ARC_REG_TLBPD1, pd1);
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if (is_pae40_enabled())
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write_aux_reg(ARC_REG_TLBPD1HI, (u64)pd1 >> 32);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBInsertEntry);
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}
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@ -249,6 +257,10 @@ noinline void local_flush_tlb_all(void)
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/* Load PD0 and PD1 with template for a Blank Entry */
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write_aux_reg(ARC_REG_TLBPD1, 0);
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if (is_pae40_enabled())
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write_aux_reg(ARC_REG_TLBPD1HI, 0);
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write_aux_reg(ARC_REG_TLBPD0, 0);
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for (entry = 0; entry < num_tlb; entry++) {
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@ -503,7 +515,8 @@ void create_tlb(struct vm_area_struct *vma, unsigned long vaddr, pte_t *ptep)
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{
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unsigned long flags;
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unsigned int asid_or_sasid, rwx;
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unsigned long pd0, pd1;
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unsigned long pd0;
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pte_t pd1;
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/*
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* create_tlb() assumes that current->mm == vma->mm, since
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@ -785,10 +798,11 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
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IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE));
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n += scnprintf(buf + n, len - n,
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"MMU [v%x]\t: %dK PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d\n",
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"MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d %s%s\n",
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p_mmu->ver, p_mmu->pg_sz_k, super_pg,
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p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways,
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p_mmu->u_dtlb, p_mmu->u_itlb);
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p_mmu->u_dtlb, p_mmu->u_itlb,
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IS_AVAIL2(p_mmu->pae, "PAE40 ", CONFIG_ARC_HAS_PAE40));
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return buf;
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}
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@ -821,6 +835,9 @@ void arc_mmu_init(void)
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panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n",
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(unsigned long)TO_MB(HPAGE_PMD_SIZE));
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if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)
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panic("Hardware doesn't support PAE40\n");
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/* Enable the MMU */
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write_aux_reg(ARC_REG_PID, MMU_ENABLE);
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@ -223,12 +223,16 @@ ex_saved_reg1:
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; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
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; (3) z = (pgtbl + y * 4)
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#ifdef CONFIG_ARC_HAS_PAE40
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#define PTE_SIZE_LOG 3 /* 8 == 2 ^ 3 */
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#else
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#define PTE_SIZE_LOG 2 /* 4 == 2 ^ 2 */
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#endif
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; multiply in step (3) above avoided by shifting lesser in step (1)
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lsr r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG )
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and r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG )
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ld.aw r0, [r1, r0] ; r0: PTE
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ld.aw r0, [r1, r0] ; r0: PTE (lower word only for PAE40)
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; r1: PTE ptr
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2:
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@ -247,6 +251,7 @@ ex_saved_reg1:
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;-----------------------------------------------------------------
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; Convert Linux PTE entry into TLB entry
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; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
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; (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])
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; IN: r0 = PTE, r1 = ptr to PTE
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.macro CONV_PTE_TO_TLB
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@ -259,6 +264,10 @@ ex_saved_reg1:
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or r3, r3, r2
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sr r3, [ARC_REG_TLBPD1] ; paddr[31..13] | Kr Kw Kx Ur Uw Ux | C
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#ifdef CONFIG_ARC_HAS_PAE40
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ld r3, [r1, 4] ; paddr[39..32]
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sr r3, [ARC_REG_TLBPD1HI]
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#endif
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and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
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