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Revert "drm/amdgpu: switch to golden tsc registers for raven/raven2" 

This reverts commit f03eb1d26c.

This results in inconsistent timing reported via asynchronous
GPU queries.

Link: https://lists.freedesktop.org/archives/amd-gfx/2023-May/093731.html
Cc: Jesse.Zhang@amd.com
Cc: michel@daenzer.net
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2023-06-02 14:37:13 -04:00
parent f9bfc9fff2
commit 5a03159ab7
1 changed files with 0 additions and 40 deletions
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40
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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@ -149,16 +149,6 @@ MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin");
#define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir 0x0026
#define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1 #define mmGOLDEN_TSC_COUNT_LOWER_Renoir_BASE_IDX 1
#define mmGOLDEN_TSC_COUNT_UPPER_Raven 0x007a
#define mmGOLDEN_TSC_COUNT_UPPER_Raven_BASE_IDX 0
#define mmGOLDEN_TSC_COUNT_LOWER_Raven 0x007b
#define mmGOLDEN_TSC_COUNT_LOWER_Raven_BASE_IDX 0
#define mmGOLDEN_TSC_COUNT_UPPER_Raven2 0x0068
#define mmGOLDEN_TSC_COUNT_UPPER_Raven2_BASE_IDX 0
#define mmGOLDEN_TSC_COUNT_LOWER_Raven2 0x0069
#define mmGOLDEN_TSC_COUNT_LOWER_Raven2_BASE_IDX 0
enum ta_ras_gfx_subblock { enum ta_ras_gfx_subblock {
/*CPC*/ /*CPC*/
TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
@ -4022,36 +4012,6 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
preempt_enable(); preempt_enable();
clock = clock_lo | (clock_hi << 32ULL); clock = clock_lo | (clock_hi << 32ULL);
break; break;
case IP_VERSION(9, 1, 0):
preempt_disable();
clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven);
/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over
* roughly every 42 seconds.
*/
if (hi_check != clock_hi) {
clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven);
clock_hi = hi_check;
}
preempt_enable();
clock = clock_lo | (clock_hi << 32ULL);
break;
case IP_VERSION(9, 2, 2):
preempt_disable();
clock_hi = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
hi_check = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_UPPER_Raven2);
/* The PWR TSC clock frequency is 100MHz, which sets 32-bit carry over
* roughly every 42 seconds.
*/
if (hi_check != clock_hi) {
clock_lo = RREG32_SOC15_NO_KIQ(PWR, 0, mmGOLDEN_TSC_COUNT_LOWER_Raven2);
clock_hi = hi_check;
}
preempt_enable();
clock = clock_lo | (clock_hi << 32ULL);
break;
default: default:
amdgpu_gfx_off_ctrl(adev, false); amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->gfx.gpu_clock_mutex); mutex_lock(&adev->gfx.gpu_clock_mutex);