ARM: dts: imx7ulp: Move usdhc clocks assignment to board DT
usdhc's clock rate is different according to different devices connected, so clock rate assignment should be placed in board DT according to different devices connected on each usdhc port. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
parent
f2c03b89c6
commit
59cf149667
|
@ -77,6 +77,8 @@
|
|||
};
|
||||
|
||||
&usdhc0 {
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc0>;
|
||||
cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
|
||||
|
|
|
@ -223,8 +223,6 @@
|
|||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&pcc2 IMX7ULP_CLK_USDHC0>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
|
@ -239,8 +237,6 @@
|
|||
<&scg1 IMX7ULP_CLK_NIC1_DIV>,
|
||||
<&pcc2 IMX7ULP_CLK_USDHC1>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
|
||||
assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
|
||||
bus-width = <4>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
|
|
Loading…
Reference in New Issue