drm/exynos/hdmi: expose HDMI-PHY clock as pipeline clock
HDMI-PHY clock should be accessible from other components in the pipeline. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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2e726dc4b4
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59b62d3c8b
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@ -146,6 +146,7 @@ struct hdmi_context {
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struct clk **clk_muxes;
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struct clk **clk_muxes;
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struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)];
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struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)];
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struct regulator *reg_hdmi_en;
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struct regulator *reg_hdmi_en;
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struct exynos_drm_clk phy_clk;
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};
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};
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static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
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static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
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@ -1445,7 +1446,6 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
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static void hdmi_conf_apply(struct hdmi_context *hdata)
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static void hdmi_conf_apply(struct hdmi_context *hdata)
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{
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{
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hdmiphy_conf_apply(hdata);
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hdmi_start(hdata, false);
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hdmi_start(hdata, false);
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hdmi_conf_init(hdata);
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hdmi_conf_init(hdata);
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hdmi_audio_init(hdata);
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hdmi_audio_init(hdata);
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@ -1478,10 +1478,8 @@ static void hdmi_set_refclk(struct hdmi_context *hdata, bool on)
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SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0);
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SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0);
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}
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}
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static void hdmi_enable(struct drm_encoder *encoder)
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static void hdmiphy_enable(struct hdmi_context *hdata)
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{
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{
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struct hdmi_context *hdata = encoder_to_hdmi(encoder);
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if (hdata->powered)
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if (hdata->powered)
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return;
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return;
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@ -1497,11 +1495,40 @@ static void hdmi_enable(struct drm_encoder *encoder)
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hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN);
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hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN);
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hdmi_conf_apply(hdata);
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hdmiphy_conf_apply(hdata);
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hdata->powered = true;
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hdata->powered = true;
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}
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}
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static void hdmiphy_disable(struct hdmi_context *hdata)
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{
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if (!hdata->powered)
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return;
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hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
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hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN);
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hdmi_set_refclk(hdata, false);
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regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
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PMU_HDMI_PHY_ENABLE_BIT, 0);
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regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk);
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pm_runtime_put_sync(hdata->dev);
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hdata->powered = false;
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}
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static void hdmi_enable(struct drm_encoder *encoder)
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{
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struct hdmi_context *hdata = encoder_to_hdmi(encoder);
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hdmiphy_enable(hdata);
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hdmi_conf_apply(hdata);
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}
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static void hdmi_disable(struct drm_encoder *encoder)
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static void hdmi_disable(struct drm_encoder *encoder)
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{
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{
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struct hdmi_context *hdata = encoder_to_hdmi(encoder);
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struct hdmi_context *hdata = encoder_to_hdmi(encoder);
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@ -1525,22 +1552,9 @@ static void hdmi_disable(struct drm_encoder *encoder)
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if (funcs && funcs->disable)
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if (funcs && funcs->disable)
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(*funcs->disable)(crtc);
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(*funcs->disable)(crtc);
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hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
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cancel_delayed_work(&hdata->hotplug_work);
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cancel_delayed_work(&hdata->hotplug_work);
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hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN);
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hdmiphy_disable(hdata);
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hdmi_set_refclk(hdata, false);
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regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
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PMU_HDMI_PHY_ENABLE_BIT, 0);
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regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk);
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pm_runtime_put_sync(hdata->dev);
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hdata->powered = false;
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}
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}
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static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = {
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static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = {
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@ -1625,6 +1639,17 @@ static int hdmi_clk_init(struct hdmi_context *hdata)
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}
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}
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static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable)
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{
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struct hdmi_context *hdata = container_of(clk, struct hdmi_context,
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phy_clk);
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if (enable)
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hdmiphy_enable(hdata);
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else
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hdmiphy_disable(hdata);
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}
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static int hdmi_resources_init(struct hdmi_context *hdata)
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static int hdmi_resources_init(struct hdmi_context *hdata)
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{
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{
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struct device *dev = hdata->dev;
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struct device *dev = hdata->dev;
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@ -1710,6 +1735,10 @@ static int hdmi_bind(struct device *dev, struct device *master, void *data)
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if (pipe < 0)
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if (pipe < 0)
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return pipe;
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return pipe;
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hdata->phy_clk.enable = hdmiphy_clk_enable;
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exynos_drm_crtc_from_pipe(drm_dev, pipe)->pipe_clk = &hdata->phy_clk;
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encoder->possible_crtcs = 1 << pipe;
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encoder->possible_crtcs = 1 << pipe;
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DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
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DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
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