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drm/amd/display: Change Min fclk to 1.2Ghz 

[Why]
Some nightly tests are failing since the new value for fclk is a
bit too low. Also, a new test for the maximum downscale case was
needed.

[How]
Updated the default value for fclk to be 1.2GHz.

Signed-off-by: Tyler DiBattista <tyler.dibattista@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tyler DiBattista 2019-04-01 15:20:44 -04:00 committed by Alex Deucher
parent 6c5be4ac63
commit 5940ff3941
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
View File

@ -249,8 +249,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
bool safe_to_lower)
{
struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
/* Min fclk = 1GHz since all the extra scemi logic seems to run off of it */
int fclk_adj = new_clocks->fclk_khz > 1000000 ? new_clocks->fclk_khz : 1000000;
/* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;