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arm64: dts: imx8: add mu5/6 node 

Add mu5/6 for i.MX8QXP/QM, these two mu will be used for
communicating with general purpose Cortex-M4 cores.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Peng Fan 2022-01-11 14:20:13 +08:00 committed by Shawn Guo
parent 75e4493e88
commit 591de9fb73
3 changed files with 32 additions and 0 deletions
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16
arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
View File

@ -141,6 +141,22 @@ lsio_subsys: bus@5d000000 {
status = "disabled";
};
lsio_mu5: mailbox@5d200000 {
reg = <0x5d200000 0x10000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_MU_5A>;
status = "disabled";
};
lsio_mu6: mailbox@5d210000 {
reg = <0x5d210000 0x10000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_MU_6A>;
status = "disabled";
};
lsio_mu13: mailbox@5d280000 {
reg = <0x5d280000 0x10000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;

8
arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
View File

@ -56,6 +56,14 @@
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu5 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu6 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};
&lsio_mu13 {
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
};

8
arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
View File

@ -56,6 +56,14 @@
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
&lsio_mu5 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
&lsio_mu6 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};
&lsio_mu13 {
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
};