drm/nouveau/mpeg: remove dependence on namedb/engctx lookup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
a65955e19e
commit
590801c1a3
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@ -24,9 +24,6 @@
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#include "nv31.h"
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#include <core/client.h>
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#include <core/handle.h>
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#include <engine/fifo.h>
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#include <subdev/instmem.h>
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#include <subdev/fb.h>
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#include <subdev/timer.h>
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@ -58,44 +55,58 @@ nv31_mpeg_object_ctor(struct nvkm_object *parent,
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return 0;
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}
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static int
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nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
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static bool
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nv31_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
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{
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struct nv31_mpeg *mpeg = (void *)object->engine;
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struct nvkm_device *device = mpeg->base.engine.subdev.device;
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struct nvkm_instmem *imem = device->imem;
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u32 inst = *(u32 *)arg << 4;
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u32 dma0 = imem->func->rd32(imem, inst + 0);
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u32 dma1 = imem->func->rd32(imem, inst + 4);
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u32 dma2 = imem->func->rd32(imem, inst + 8);
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u32 inst = data << 4;
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u32 dma0 = nvkm_rd32(device, 0x700000 + inst);
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u32 dma1 = nvkm_rd32(device, 0x700004 + inst);
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u32 dma2 = nvkm_rd32(device, 0x700008 + inst);
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u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
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u32 size = dma1 + 1;
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/* only allow linear DMA objects */
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if (!(dma0 & 0x00002000))
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return -EINVAL;
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return false;
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if (mthd == 0x0190) {
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/* DMA_CMD */
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nvkm_mask(device, 0x00b300, 0x00010000, (dma0 & 0x00030000) ? 0x00010000 : 0);
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nvkm_mask(device, 0x00b300, 0x00010000,
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(dma0 & 0x00030000) ? 0x00010000 : 0);
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nvkm_wr32(device, 0x00b334, base);
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nvkm_wr32(device, 0x00b324, size);
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} else
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if (mthd == 0x01a0) {
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/* DMA_DATA */
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nvkm_mask(device, 0x00b300, 0x00020000, (dma0 & 0x00030000) ? 0x00020000 : 0);
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nvkm_mask(device, 0x00b300, 0x00020000,
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(dma0 & 0x00030000) ? 0x00020000 : 0);
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nvkm_wr32(device, 0x00b360, base);
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nvkm_wr32(device, 0x00b364, size);
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} else {
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/* DMA_IMAGE, VRAM only */
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if (dma0 & 0x00030000)
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return -EINVAL;
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return false;
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nvkm_wr32(device, 0x00b370, base);
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nvkm_wr32(device, 0x00b374, size);
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}
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return 0;
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return true;
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}
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static bool
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nv31_mpeg_mthd(struct nv31_mpeg *mpeg, u32 mthd, u32 data)
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{
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struct nvkm_device *device = mpeg->base.engine.subdev.device;
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switch (mthd) {
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case 0x190:
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case 0x1a0:
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case 0x1b0:
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return mpeg->mthd_dma(device, mthd, data);
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default:
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break;
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}
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return false;
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}
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struct nvkm_ofuncs
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@ -108,17 +119,9 @@ nv31_mpeg_ofuncs = {
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.wr32 = _nvkm_gpuobj_wr32,
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};
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static struct nvkm_omthds
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nv31_mpeg_omthds[] = {
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{ 0x0190, 0x0190, nv31_mpeg_mthd_dma },
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{ 0x01a0, 0x01a0, nv31_mpeg_mthd_dma },
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{ 0x01b0, 0x01b0, nv31_mpeg_mthd_dma },
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{}
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};
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struct nvkm_oclass
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nv31_mpeg_sclass[] = {
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{ 0x3174, &nv31_mpeg_ofuncs, nv31_mpeg_omthds },
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{ 0x3174, &nv31_mpeg_ofuncs },
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{}
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};
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@ -149,6 +152,7 @@ nv31_mpeg_context_ctor(struct nvkm_object *parent,
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*pobject = NULL;
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return -EBUSY;
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}
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chan->fifo = nvkm_fifo_chan(parent);
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mpeg->chan = chan;
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spin_unlock_irqrestore(&nv_engine(mpeg)->lock, flags);
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return 0;
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@ -199,9 +203,6 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
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{
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struct nv31_mpeg *mpeg = (void *)subdev;
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struct nvkm_device *device = mpeg->base.engine.subdev.device;
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struct nvkm_fifo *fifo = device->fifo;
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struct nvkm_handle *handle;
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struct nvkm_object *engctx;
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u32 stat = nvkm_rd32(device, 0x00b100);
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u32 type = nvkm_rd32(device, 0x00b230);
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u32 mthd = nvkm_rd32(device, 0x00b234);
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@ -209,8 +210,7 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
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u32 show = stat;
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unsigned long flags;
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spin_lock_irqsave(&nv_engine(mpeg)->lock, flags);
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engctx = nv_object(mpeg->chan);
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spin_lock_irqsave(&mpeg->base.engine.lock, flags);
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if (stat & 0x01000000) {
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/* happens on initial binding of the object */
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@ -219,11 +219,9 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
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show &= ~0x01000000;
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}
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if (type == 0x00000010 && engctx) {
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handle = nvkm_handle_get_class(engctx, 0x3174);
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if (handle && !nv_call(handle->object, mthd, data))
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if (type == 0x00000010) {
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if (!nv31_mpeg_mthd(mpeg, mthd, data))
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show &= ~0x01000000;
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nvkm_handle_put(handle);
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}
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}
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@ -232,11 +230,12 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev)
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if (show) {
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nvkm_error(subdev, "ch %d [%s] %08x %08x %08x %08x\n",
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fifo->chid(fifo, engctx),
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nvkm_client_name(engctx), stat, type, mthd, data);
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mpeg->chan ? mpeg->chan->fifo->chid : -1,
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nvkm_client_name(mpeg->chan),
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stat, type, mthd, data);
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}
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spin_unlock_irqrestore(&nv_engine(mpeg)->lock, flags);
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spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
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}
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static int
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@ -252,6 +251,7 @@ nv31_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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if (ret)
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return ret;
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mpeg->mthd_dma = nv31_mpeg_mthd_dma;
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nv_subdev(mpeg)->unit = 0x00000002;
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nv_subdev(mpeg)->intr = nv31_mpeg_intr;
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nv_engine(mpeg)->cclass = &nv31_mpeg_cclass;
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@ -1,13 +1,16 @@
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#ifndef __NV31_MPEG_H__
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#define __NV31_MPEG_H__
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#include <engine/mpeg.h>
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#include <engine/fifo.h>
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struct nv31_mpeg_chan {
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struct nvkm_object base;
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struct nvkm_fifo_chan *fifo;
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};
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struct nv31_mpeg {
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struct nvkm_mpeg base;
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struct nv31_mpeg_chan *chan;
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bool (*mthd_dma)(struct nvkm_device *, u32 mthd, u32 data);
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};
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#endif
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@ -29,13 +29,11 @@
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* MPEG object classes
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******************************************************************************/
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static int
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nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
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bool
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nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
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{
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struct nv31_mpeg *mpeg = (void *)object->engine;
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struct nvkm_device *device = mpeg->base.engine.subdev.device;
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struct nvkm_instmem *imem = device->imem;
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u32 inst = *(u32 *)arg << 4;
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u32 inst = data << 4;
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u32 dma0 = imem->func->rd32(imem, inst + 0);
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u32 dma1 = imem->func->rd32(imem, inst + 4);
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u32 dma2 = imem->func->rd32(imem, inst + 8);
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@ -44,7 +42,7 @@ nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
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/* only allow linear DMA objects */
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if (!(dma0 & 0x00002000))
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return -EINVAL;
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return false;
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if (mthd == 0x0190) {
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/* DMA_CMD */
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@ -60,26 +58,18 @@ nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len)
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} else {
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/* DMA_IMAGE, VRAM only */
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if (dma0 & 0x00030000)
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return -EINVAL;
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return false;
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nvkm_wr32(device, 0x00b370, base);
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nvkm_wr32(device, 0x00b374, size);
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}
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return 0;
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return true;
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}
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static struct nvkm_omthds
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nv40_mpeg_omthds[] = {
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{ 0x0190, 0x0190, nv40_mpeg_mthd_dma },
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{ 0x01a0, 0x01a0, nv40_mpeg_mthd_dma },
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{ 0x01b0, 0x01b0, nv40_mpeg_mthd_dma },
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{}
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};
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struct nvkm_oclass
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nv40_mpeg_sclass[] = {
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{ 0x3174, &nv31_mpeg_ofuncs, nv40_mpeg_omthds },
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{ 0x3174, &nv31_mpeg_ofuncs },
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{}
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};
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@ -116,6 +106,7 @@ nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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if (ret)
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return ret;
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mpeg->mthd_dma = nv40_mpeg_mthd_dma;
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nv_subdev(mpeg)->unit = 0x00000002;
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nv_subdev(mpeg)->intr = nv40_mpeg_intr;
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nv_engine(mpeg)->cclass = &nv31_mpeg_cclass;
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@ -24,24 +24,47 @@
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#include <engine/mpeg.h>
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#include <core/client.h>
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#include <core/handle.h>
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#include <engine/fifo.h>
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struct nv44_mpeg {
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struct nvkm_mpeg base;
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struct list_head chan;
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};
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struct nv44_mpeg_chan {
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struct nvkm_mpeg_chan base;
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struct nvkm_fifo_chan *fifo;
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u32 inst;
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struct list_head head;
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};
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bool nv40_mpeg_mthd_dma(struct nvkm_device *, u32, u32);
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/*******************************************************************************
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* PMPEG context
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******************************************************************************/
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static void
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nv44_mpeg_context_dtor(struct nvkm_object *object)
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{
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struct nv44_mpeg_chan *chan = (void *)object;
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struct nv44_mpeg *mpeg = (void *)object->engine;
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unsigned long flags;
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spin_lock_irqsave(&mpeg->base.engine.lock, flags);
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list_del(&chan->head);
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spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
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nvkm_mpeg_context_destroy(&chan->base);
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}
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static int
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nv44_mpeg_context_ctor(struct nvkm_object *parent,
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struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv44_mpeg *mpeg = (void *)engine;
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struct nv44_mpeg_chan *chan;
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unsigned long flags;
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int ret;
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ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 264 * 4,
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@ -50,6 +73,12 @@ nv44_mpeg_context_ctor(struct nvkm_object *parent,
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if (ret)
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return ret;
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spin_lock_irqsave(&mpeg->base.engine.lock, flags);
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chan->fifo = nvkm_fifo_chan(parent);
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chan->inst = chan->base.base.gpuobj.addr;
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list_add(&chan->head, &mpeg->chan);
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spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
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nvkm_kmap(&chan->base.base.gpuobj);
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nvkm_wo32(&chan->base.base.gpuobj, 0x78, 0x02001ec1);
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nvkm_done(&chan->base.base.gpuobj);
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@ -77,7 +106,7 @@ nv44_mpeg_cclass = {
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.handle = NV_ENGCTX(MPEG, 0x44),
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = nv44_mpeg_context_ctor,
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.dtor = _nvkm_mpeg_context_dtor,
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.dtor = nv44_mpeg_context_dtor,
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.init = _nvkm_mpeg_context_init,
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.fini = nv44_mpeg_context_fini,
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.rd32 = _nvkm_mpeg_context_rd32,
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@ -89,25 +118,45 @@ nv44_mpeg_cclass = {
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* PMPEG engine/subdev functions
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******************************************************************************/
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static bool
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nv44_mpeg_mthd(struct nvkm_device *device, u32 mthd, u32 data)
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{
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switch (mthd) {
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case 0x190:
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case 0x1a0:
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case 0x1b0:
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return nv40_mpeg_mthd_dma(device, mthd, data);
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default:
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break;
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}
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return false;
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}
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static void
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nv44_mpeg_intr(struct nvkm_subdev *subdev)
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{
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struct nvkm_mpeg *mpeg = (void *)subdev;
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struct nvkm_device *device = mpeg->engine.subdev.device;
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struct nvkm_fifo *fifo = device->fifo;
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struct nvkm_engine *engine = nv_engine(subdev);
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struct nvkm_object *engctx;
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struct nvkm_handle *handle;
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struct nv44_mpeg *mpeg = (void *)subdev;
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struct nv44_mpeg_chan *temp, *chan = NULL;
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struct nvkm_device *device = mpeg->base.engine.subdev.device;
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unsigned long flags;
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u32 inst = nvkm_rd32(device, 0x00b318) & 0x000fffff;
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u32 stat = nvkm_rd32(device, 0x00b100);
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u32 type = nvkm_rd32(device, 0x00b230);
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u32 mthd = nvkm_rd32(device, 0x00b234);
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u32 data = nvkm_rd32(device, 0x00b238);
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u32 show = stat;
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int chid;
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int chid = -1;
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engctx = nvkm_engctx_get(engine, inst);
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chid = fifo->chid(fifo, engctx);
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spin_lock_irqsave(&mpeg->base.engine.lock, flags);
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list_for_each_entry(temp, &mpeg->chan, head) {
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if (temp->inst >> 4 == inst) {
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chan = temp;
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chid = chan->fifo->chid;
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list_del(&chan->head);
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list_add(&chan->head, &mpeg->chan);
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break;
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}
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}
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if (stat & 0x01000000) {
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/* happens on initial binding of the object */
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@ -117,10 +166,8 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
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}
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if (type == 0x00000010) {
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handle = nvkm_handle_get_class(engctx, 0x3174);
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if (handle && !nv_call(handle->object, mthd, data))
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if (!nv44_mpeg_mthd(subdev->device, mthd, data))
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show &= ~0x01000000;
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nvkm_handle_put(handle);
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}
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}
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@ -128,13 +175,12 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev)
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nvkm_wr32(device, 0x00b230, 0x00000001);
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if (show) {
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nvkm_error(subdev,
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"ch %d [%08x %s] %08x %08x %08x %08x\n",
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chid, inst << 4, nvkm_client_name(engctx), stat,
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type, mthd, data);
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nvkm_error(subdev, "ch %d [%08x %s] %08x %08x %08x %08x\n",
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chid, inst << 4, nvkm_client_name(chan),
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stat, type, mthd, data);
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}
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nvkm_engctx_put(engctx);
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spin_unlock_irqrestore(&mpeg->base.engine.lock, flags);
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}
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static void
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@ -158,7 +204,7 @@ nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nvkm_mpeg *mpeg;
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struct nv44_mpeg *mpeg;
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int ret;
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ret = nvkm_mpeg_create(parent, engine, oclass, &mpeg);
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@ -166,6 +212,8 @@ nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
INIT_LIST_HEAD(&mpeg->chan);
|
||||
|
||||
nv_subdev(mpeg)->unit = 0x00000002;
|
||||
nv_subdev(mpeg)->intr = nv44_mpeg_me_intr;
|
||||
nv_engine(mpeg)->cclass = &nv44_mpeg_cclass;
|
||||
|
|
|
|||
Loading…
Reference in New Issue