drm/amdgpu: cleanup sync_seq handling

Not used any more without semaphores

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König 2016-01-18 15:16:53 +01:00 committed by Alex Deucher
parent 046c12c67b
commit 5907a0d8af
3 changed files with 13 additions and 90 deletions

View File

@ -388,7 +388,7 @@ struct amdgpu_fence_driver {
uint64_t gpu_addr; uint64_t gpu_addr;
volatile uint32_t *cpu_addr; volatile uint32_t *cpu_addr;
/* sync_seq is protected by ring emission lock */ /* sync_seq is protected by ring emission lock */
uint64_t sync_seq[AMDGPU_MAX_RINGS]; uint64_t sync_seq;
atomic64_t last_seq; atomic64_t last_seq;
bool initialized; bool initialized;
struct amdgpu_irq_src *irq_src; struct amdgpu_irq_src *irq_src;
@ -441,11 +441,6 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
struct amdgpu_ring *ring);
void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
struct amdgpu_ring *ring);
/* /*
* TTM. * TTM.
*/ */

View File

@ -107,7 +107,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
if ((*fence) == NULL) { if ((*fence) == NULL) {
return -ENOMEM; return -ENOMEM;
} }
(*fence)->seq = ++ring->fence_drv.sync_seq[ring->idx]; (*fence)->seq = ++ring->fence_drv.sync_seq;
(*fence)->ring = ring; (*fence)->ring = ring;
(*fence)->owner = owner; (*fence)->owner = owner;
fence_init(&(*fence)->base, &amdgpu_fence_ops, fence_init(&(*fence)->base, &amdgpu_fence_ops,
@ -171,7 +171,7 @@ static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
*/ */
last_seq = atomic64_read(&ring->fence_drv.last_seq); last_seq = atomic64_read(&ring->fence_drv.last_seq);
do { do {
last_emitted = ring->fence_drv.sync_seq[ring->idx]; last_emitted = ring->fence_drv.sync_seq;
seq = amdgpu_fence_read(ring); seq = amdgpu_fence_read(ring);
seq |= last_seq & 0xffffffff00000000LL; seq |= last_seq & 0xffffffff00000000LL;
if (seq < last_seq) { if (seq < last_seq) {
@ -274,7 +274,7 @@ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
bool signaled = false; bool signaled = false;
BUG_ON(!ring); BUG_ON(!ring);
if (seq > ring->fence_drv.sync_seq[ring->idx]) if (seq > ring->fence_drv.sync_seq)
return -EINVAL; return -EINVAL;
if (atomic64_read(&ring->fence_drv.last_seq) >= seq) if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
@ -304,7 +304,7 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
{ {
uint64_t seq = atomic64_read(&ring->fence_drv.last_seq) + 1ULL; uint64_t seq = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
if (seq >= ring->fence_drv.sync_seq[ring->idx]) if (seq >= ring->fence_drv.sync_seq)
return -ENOENT; return -ENOENT;
return amdgpu_fence_ring_wait_seq(ring, seq); return amdgpu_fence_ring_wait_seq(ring, seq);
@ -322,7 +322,7 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
*/ */
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
{ {
uint64_t seq = ring->fence_drv.sync_seq[ring->idx]; uint64_t seq = ring->fence_drv.sync_seq;
if (!seq) if (!seq)
return 0; return 0;
@ -347,7 +347,7 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
* but it's ok to report slightly wrong fence count here. * but it's ok to report slightly wrong fence count here.
*/ */
amdgpu_fence_process(ring); amdgpu_fence_process(ring);
emitted = ring->fence_drv.sync_seq[ring->idx] emitted = ring->fence_drv.sync_seq
- atomic64_read(&ring->fence_drv.last_seq); - atomic64_read(&ring->fence_drv.last_seq);
/* to avoid 32bits warp around */ /* to avoid 32bits warp around */
if (emitted > 0x10000000) if (emitted > 0x10000000)
@ -356,68 +356,6 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
return (unsigned)emitted; return (unsigned)emitted;
} }
/**
* amdgpu_fence_need_sync - do we need a semaphore
*
* @fence: amdgpu fence object
* @dst_ring: which ring to check against
*
* Check if the fence needs to be synced against another ring
* (all asics). If so, we need to emit a semaphore.
* Returns true if we need to sync with another ring, false if
* not.
*/
bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
struct amdgpu_ring *dst_ring)
{
struct amdgpu_fence_driver *fdrv;
if (!fence)
return false;
if (fence->ring == dst_ring)
return false;
/* we are protected by the ring mutex */
fdrv = &dst_ring->fence_drv;
if (fence->seq <= fdrv->sync_seq[fence->ring->idx])
return false;
return true;
}
/**
* amdgpu_fence_note_sync - record the sync point
*
* @fence: amdgpu fence object
* @dst_ring: which ring to check against
*
* Note the sequence number at which point the fence will
* be synced with the requested ring (all asics).
*/
void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
struct amdgpu_ring *dst_ring)
{
struct amdgpu_fence_driver *dst, *src;
unsigned i;
if (!fence)
return;
if (fence->ring == dst_ring)
return;
/* we are protected by the ring mutex */
src = &fence->ring->fence_drv;
dst = &dst_ring->fence_drv;
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
if (i == dst_ring->idx)
continue;
dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
}
}
/** /**
* amdgpu_fence_driver_start_ring - make the fence driver * amdgpu_fence_driver_start_ring - make the fence driver
* ready for use on the requested ring. * ready for use on the requested ring.
@ -471,14 +409,12 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
*/ */
int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
{ {
int i, r;
long timeout; long timeout;
int r;
ring->fence_drv.cpu_addr = NULL; ring->fence_drv.cpu_addr = NULL;
ring->fence_drv.gpu_addr = 0; ring->fence_drv.gpu_addr = 0;
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) ring->fence_drv.sync_seq = 0;
ring->fence_drv.sync_seq[i] = 0;
atomic64_set(&ring->fence_drv.last_seq, 0); atomic64_set(&ring->fence_drv.last_seq, 0);
ring->fence_drv.initialized = false; ring->fence_drv.initialized = false;
@ -650,7 +586,7 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
if (!ring || !ring->fence_drv.initialized) if (!ring || !ring->fence_drv.initialized)
continue; continue;
amdgpu_fence_write(ring, ring->fence_drv.sync_seq[i]); amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
} }
} }
@ -780,7 +716,7 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
struct drm_info_node *node = (struct drm_info_node *)m->private; struct drm_info_node *node = (struct drm_info_node *)m->private;
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
struct amdgpu_device *adev = dev->dev_private; struct amdgpu_device *adev = dev->dev_private;
int i, j; int i;
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
struct amdgpu_ring *ring = adev->rings[i]; struct amdgpu_ring *ring = adev->rings[i];
@ -793,15 +729,7 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
seq_printf(m, "Last signaled fence 0x%016llx\n", seq_printf(m, "Last signaled fence 0x%016llx\n",
(unsigned long long)atomic64_read(&ring->fence_drv.last_seq)); (unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
seq_printf(m, "Last emitted 0x%016llx\n", seq_printf(m, "Last emitted 0x%016llx\n",
ring->fence_drv.sync_seq[i]); ring->fence_drv.sync_seq);
for (j = 0; j < AMDGPU_MAX_RINGS; ++j) {
struct amdgpu_ring *other = adev->rings[j];
if (i != j && other && other->fence_drv.initialized &&
ring->fence_drv.sync_seq[j])
seq_printf(m, "Last sync to ring %d 0x%016llx\n",
j, ring->fence_drv.sync_seq[j]);
}
} }
return 0; return 0;
} }

View File

@ -4766,7 +4766,7 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
unsigned vm_id, uint64_t pd_addr) unsigned vm_id, uint64_t pd_addr)
{ {
int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
uint32_t seq = ring->fence_drv.sync_seq[ring->idx]; uint32_t seq = ring->fence_drv.sync_seq;
uint64_t addr = ring->fence_drv.gpu_addr; uint64_t addr = ring->fence_drv.gpu_addr;
amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));