drm/amdgpu: cleanup sync_seq handling
Not used any more without semaphores Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -388,7 +388,7 @@ struct amdgpu_fence_driver {
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uint64_t gpu_addr;
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uint64_t gpu_addr;
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volatile uint32_t *cpu_addr;
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volatile uint32_t *cpu_addr;
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/* sync_seq is protected by ring emission lock */
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/* sync_seq is protected by ring emission lock */
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uint64_t sync_seq[AMDGPU_MAX_RINGS];
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uint64_t sync_seq;
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atomic64_t last_seq;
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atomic64_t last_seq;
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bool initialized;
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bool initialized;
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struct amdgpu_irq_src *irq_src;
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struct amdgpu_irq_src *irq_src;
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@ -441,11 +441,6 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
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int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
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int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
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unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
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unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
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bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
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struct amdgpu_ring *ring);
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void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
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struct amdgpu_ring *ring);
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/*
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/*
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* TTM.
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* TTM.
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*/
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*/
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@ -107,7 +107,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
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if ((*fence) == NULL) {
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if ((*fence) == NULL) {
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return -ENOMEM;
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return -ENOMEM;
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}
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}
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(*fence)->seq = ++ring->fence_drv.sync_seq[ring->idx];
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(*fence)->seq = ++ring->fence_drv.sync_seq;
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(*fence)->ring = ring;
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(*fence)->ring = ring;
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(*fence)->owner = owner;
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(*fence)->owner = owner;
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fence_init(&(*fence)->base, &amdgpu_fence_ops,
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fence_init(&(*fence)->base, &amdgpu_fence_ops,
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@ -171,7 +171,7 @@ static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
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*/
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*/
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last_seq = atomic64_read(&ring->fence_drv.last_seq);
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last_seq = atomic64_read(&ring->fence_drv.last_seq);
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do {
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do {
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last_emitted = ring->fence_drv.sync_seq[ring->idx];
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last_emitted = ring->fence_drv.sync_seq;
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seq = amdgpu_fence_read(ring);
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seq = amdgpu_fence_read(ring);
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seq |= last_seq & 0xffffffff00000000LL;
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seq |= last_seq & 0xffffffff00000000LL;
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if (seq < last_seq) {
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if (seq < last_seq) {
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@ -274,7 +274,7 @@ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
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bool signaled = false;
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bool signaled = false;
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BUG_ON(!ring);
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BUG_ON(!ring);
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if (seq > ring->fence_drv.sync_seq[ring->idx])
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if (seq > ring->fence_drv.sync_seq)
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return -EINVAL;
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return -EINVAL;
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if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
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if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
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@ -304,7 +304,7 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
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{
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{
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uint64_t seq = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
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uint64_t seq = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
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if (seq >= ring->fence_drv.sync_seq[ring->idx])
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if (seq >= ring->fence_drv.sync_seq)
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return -ENOENT;
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return -ENOENT;
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return amdgpu_fence_ring_wait_seq(ring, seq);
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return amdgpu_fence_ring_wait_seq(ring, seq);
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@ -322,7 +322,7 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
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*/
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*/
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int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
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int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
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{
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{
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uint64_t seq = ring->fence_drv.sync_seq[ring->idx];
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uint64_t seq = ring->fence_drv.sync_seq;
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if (!seq)
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if (!seq)
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return 0;
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return 0;
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@ -347,7 +347,7 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
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* but it's ok to report slightly wrong fence count here.
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* but it's ok to report slightly wrong fence count here.
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*/
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*/
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amdgpu_fence_process(ring);
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amdgpu_fence_process(ring);
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emitted = ring->fence_drv.sync_seq[ring->idx]
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emitted = ring->fence_drv.sync_seq
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- atomic64_read(&ring->fence_drv.last_seq);
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- atomic64_read(&ring->fence_drv.last_seq);
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/* to avoid 32bits warp around */
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/* to avoid 32bits warp around */
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if (emitted > 0x10000000)
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if (emitted > 0x10000000)
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@ -356,68 +356,6 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
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return (unsigned)emitted;
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return (unsigned)emitted;
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}
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}
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/**
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* amdgpu_fence_need_sync - do we need a semaphore
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*
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* @fence: amdgpu fence object
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* @dst_ring: which ring to check against
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*
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* Check if the fence needs to be synced against another ring
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* (all asics). If so, we need to emit a semaphore.
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* Returns true if we need to sync with another ring, false if
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* not.
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*/
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bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
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struct amdgpu_ring *dst_ring)
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{
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struct amdgpu_fence_driver *fdrv;
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if (!fence)
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return false;
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if (fence->ring == dst_ring)
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return false;
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/* we are protected by the ring mutex */
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fdrv = &dst_ring->fence_drv;
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if (fence->seq <= fdrv->sync_seq[fence->ring->idx])
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return false;
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return true;
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}
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/**
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* amdgpu_fence_note_sync - record the sync point
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*
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* @fence: amdgpu fence object
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* @dst_ring: which ring to check against
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*
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* Note the sequence number at which point the fence will
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* be synced with the requested ring (all asics).
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*/
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void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
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struct amdgpu_ring *dst_ring)
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{
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struct amdgpu_fence_driver *dst, *src;
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unsigned i;
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if (!fence)
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return;
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if (fence->ring == dst_ring)
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return;
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/* we are protected by the ring mutex */
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src = &fence->ring->fence_drv;
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dst = &dst_ring->fence_drv;
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
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if (i == dst_ring->idx)
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continue;
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dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
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}
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}
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/**
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/**
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* amdgpu_fence_driver_start_ring - make the fence driver
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* amdgpu_fence_driver_start_ring - make the fence driver
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* ready for use on the requested ring.
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* ready for use on the requested ring.
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@ -471,14 +409,12 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
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*/
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*/
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int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
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int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
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{
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{
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int i, r;
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long timeout;
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long timeout;
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int r;
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ring->fence_drv.cpu_addr = NULL;
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ring->fence_drv.cpu_addr = NULL;
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ring->fence_drv.gpu_addr = 0;
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ring->fence_drv.gpu_addr = 0;
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
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ring->fence_drv.sync_seq = 0;
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ring->fence_drv.sync_seq[i] = 0;
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atomic64_set(&ring->fence_drv.last_seq, 0);
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atomic64_set(&ring->fence_drv.last_seq, 0);
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ring->fence_drv.initialized = false;
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ring->fence_drv.initialized = false;
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@ -650,7 +586,7 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
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if (!ring || !ring->fence_drv.initialized)
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if (!ring || !ring->fence_drv.initialized)
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continue;
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continue;
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amdgpu_fence_write(ring, ring->fence_drv.sync_seq[i]);
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amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
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}
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}
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}
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}
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@ -780,7 +716,7 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
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struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_device *dev = node->minor->dev;
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struct drm_device *dev = node->minor->dev;
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struct amdgpu_device *adev = dev->dev_private;
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struct amdgpu_device *adev = dev->dev_private;
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int i, j;
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int i;
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
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struct amdgpu_ring *ring = adev->rings[i];
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struct amdgpu_ring *ring = adev->rings[i];
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@ -793,15 +729,7 @@ static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
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seq_printf(m, "Last signaled fence 0x%016llx\n",
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seq_printf(m, "Last signaled fence 0x%016llx\n",
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(unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
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(unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
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seq_printf(m, "Last emitted 0x%016llx\n",
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seq_printf(m, "Last emitted 0x%016llx\n",
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ring->fence_drv.sync_seq[i]);
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ring->fence_drv.sync_seq);
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for (j = 0; j < AMDGPU_MAX_RINGS; ++j) {
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struct amdgpu_ring *other = adev->rings[j];
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if (i != j && other && other->fence_drv.initialized &&
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ring->fence_drv.sync_seq[j])
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seq_printf(m, "Last sync to ring %d 0x%016llx\n",
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j, ring->fence_drv.sync_seq[j]);
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}
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}
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}
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return 0;
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return 0;
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}
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}
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@ -4766,7 +4766,7 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned vm_id, uint64_t pd_addr)
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unsigned vm_id, uint64_t pd_addr)
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{
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{
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int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
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int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
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uint32_t seq = ring->fence_drv.sync_seq[ring->idx];
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uint32_t seq = ring->fence_drv.sync_seq;
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uint64_t addr = ring->fence_drv.gpu_addr;
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uint64_t addr = ring->fence_drv.gpu_addr;
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amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
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amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
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