Blackfin arch: add new processor ADSP-BF52x arch/mach support
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Michael Hennerich
Bryan Wu
parent
cfa76f024f
commit
590031450a
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@ -71,7 +71,7 @@ config GENERIC_CALIBRATE_DELAY
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config IRQCHIP_DEMUX_GPIO
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config IRQCHIP_DEMUX_GPIO
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bool
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bool
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depends on (BF53x || BF561 || BF54x)
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depends on (BF52x || BF53x || BF561 || BF54x)
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default y
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default y
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source "init/Kconfig"
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source "init/Kconfig"
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@ -85,6 +85,21 @@ choice
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prompt "CPU"
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prompt "CPU"
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default BF533
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default BF533
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config BF522
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bool "BF522"
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help
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BF522 Processor Support.
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config BF525
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bool "BF525"
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help
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BF525 Processor Support.
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config BF527
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bool "BF527"
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help
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BF527 Processor Support.
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config BF531
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config BF531
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bool "BF531"
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bool "BF531"
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help
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help
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@ -144,13 +159,18 @@ endchoice
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choice
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choice
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prompt "Silicon Rev"
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prompt "Silicon Rev"
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default BF_REV_0_1 if BF527
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default BF_REV_0_2 if BF537
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default BF_REV_0_2 if BF537
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default BF_REV_0_3 if BF533
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default BF_REV_0_3 if BF533
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default BF_REV_0_0 if BF549
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default BF_REV_0_0 if BF549
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config BF_REV_0_0
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config BF_REV_0_0
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bool "0.0"
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bool "0.0"
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depends on (BF549)
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depends on (BF549 || BF527)
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config BF_REV_0_1
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bool "0.2"
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depends on (BF549 || BF527)
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config BF_REV_0_2
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config BF_REV_0_2
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bool "0.2"
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bool "0.2"
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@ -176,6 +196,11 @@ config BF_REV_NONE
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endchoice
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endchoice
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config BF52x
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bool
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depends on (BF522 || BF525 || BF527)
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default y
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config BF53x
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config BF53x
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bool
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bool
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depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
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depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
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@ -204,6 +229,12 @@ choice
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configuration to ensure that all the other settings are
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configuration to ensure that all the other settings are
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correct.
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correct.
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config BFIN527_EZKIT
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bool "BF527-EZKIT"
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depends on (BF522 || BF525 || BF527)
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help
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BF533-EZKIT-LITE board Support.
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config BFIN533_EZKIT
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config BFIN533_EZKIT
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bool "BF533-EZKIT"
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bool "BF533-EZKIT"
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depends on (BF533 || BF532 || BF531)
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depends on (BF533 || BF532 || BF531)
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@ -299,11 +330,17 @@ config MEM_MT48LC8M32B2B5_7
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depends on (BFIN561_BLUETECHNIX_CM)
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depends on (BFIN561_BLUETECHNIX_CM)
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default y
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default y
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config MEM_MT48LC32M16A2TG_75
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bool
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depends on (BFIN527_EZKIT)
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default y
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config BFIN_SHARED_FLASH_ENET
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config BFIN_SHARED_FLASH_ENET
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bool
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bool
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depends on (BFIN533_STAMP)
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depends on (BFIN533_STAMP)
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default y
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default y
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source "arch/blackfin/mach-bf527/Kconfig"
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source "arch/blackfin/mach-bf533/Kconfig"
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source "arch/blackfin/mach-bf533/Kconfig"
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source "arch/blackfin/mach-bf561/Kconfig"
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source "arch/blackfin/mach-bf561/Kconfig"
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source "arch/blackfin/mach-bf537/Kconfig"
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source "arch/blackfin/mach-bf537/Kconfig"
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@ -329,7 +366,7 @@ config CLKIN_HZ
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int "Crystal Frequency in Hz"
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int "Crystal Frequency in Hz"
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default "11059200" if BFIN533_STAMP
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default "11059200" if BFIN533_STAMP
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default "27000000" if BFIN533_EZKIT
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default "27000000" if BFIN533_EZKIT
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default "25000000" if BFIN537_STAMP
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default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT)
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default "30000000" if BFIN561_EZKIT
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default "30000000" if BFIN561_EZKIT
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default "24576000" if PNAV10
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default "24576000" if PNAV10
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help
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help
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@ -362,7 +399,7 @@ config VCO_MULT
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range 1 64
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range 1 64
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default "22" if BFIN533_EZKIT
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default "22" if BFIN533_EZKIT
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default "45" if BFIN533_STAMP
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default "45" if BFIN533_STAMP
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default "20" if BFIN537_STAMP
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default "20" if (BFIN537_STAMP || BFIN527_EZKIT)
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default "22" if BFIN533_BLUETECHNIX_CM
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default "22" if BFIN533_BLUETECHNIX_CM
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default "20" if BFIN537_BLUETECHNIX_CM
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default "20" if BFIN537_BLUETECHNIX_CM
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default "20" if BFIN561_BLUETECHNIX_CM
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default "20" if BFIN561_BLUETECHNIX_CM
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@ -398,7 +435,7 @@ config SCLK_DIV
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range 1 15
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range 1 15
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default 5 if BFIN533_EZKIT
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default 5 if BFIN533_EZKIT
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default 5 if BFIN533_STAMP
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default 5 if BFIN533_STAMP
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default 4 if BFIN537_STAMP
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default 4 if (BFIN537_STAMP || BFIN527_EZKIT)
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default 5 if BFIN533_BLUETECHNIX_CM
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default 5 if BFIN533_BLUETECHNIX_CM
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default 4 if BFIN537_BLUETECHNIX_CM
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default 4 if BFIN537_BLUETECHNIX_CM
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default 4 if BFIN561_BLUETECHNIX_CM
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default 4 if BFIN561_BLUETECHNIX_CM
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@ -450,6 +487,7 @@ comment "Memory Setup"
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config MEM_SIZE
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config MEM_SIZE
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int "SDRAM Memory Size in MBytes"
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int "SDRAM Memory Size in MBytes"
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default 32 if BFIN533_EZKIT
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default 32 if BFIN533_EZKIT
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default 64 if BFIN527_EZKIT
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default 64 if BFIN537_STAMP
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default 64 if BFIN537_STAMP
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default 64 if BFIN561_EZKIT
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default 64 if BFIN561_EZKIT
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default 128 if BFIN533_STAMP
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default 128 if BFIN533_STAMP
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@ -459,6 +497,7 @@ config MEM_ADD_WIDTH
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int "SDRAM Memory Address Width"
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int "SDRAM Memory Address Width"
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default 9 if BFIN533_EZKIT
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default 9 if BFIN533_EZKIT
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default 9 if BFIN561_EZKIT
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default 9 if BFIN561_EZKIT
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default 10 if BFIN527_EZKIT
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default 10 if BFIN537_STAMP
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default 10 if BFIN537_STAMP
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default 11 if BFIN533_STAMP
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default 11 if BFIN533_STAMP
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default 10 if PNAV10
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default 10 if PNAV10
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@ -751,7 +790,7 @@ config LARGE_ALLOCS
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config BFIN_DMA_5XX
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config BFIN_DMA_5XX
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bool "Enable DMA Support"
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bool "Enable DMA Support"
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depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561 || BF54x)
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depends on (BF52x || BF53x || BF561 || BF54x)
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default y
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default y
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help
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help
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DMA driver for BF5xx.
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DMA driver for BF5xx.
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@ -18,6 +18,9 @@ KALLSYMS += --symbol-prefix=_
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KBUILD_DEFCONFIG := BF537-STAMP_defconfig
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KBUILD_DEFCONFIG := BF537-STAMP_defconfig
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# setup the machine name and the machine dependent settings
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# setup the machine name and the machine dependent settings
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machine-$(CONFIG_BF522) := bf527
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machine-$(CONFIG_BF525) := bf527
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machine-$(CONFIG_BF527) := bf527
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machine-$(CONFIG_BF531) := bf533
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machine-$(CONFIG_BF531) := bf533
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machine-$(CONFIG_BF532) := bf533
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machine-$(CONFIG_BF532) := bf533
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machine-$(CONFIG_BF533) := bf533
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machine-$(CONFIG_BF533) := bf533
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@ -32,6 +35,9 @@ machine-$(CONFIG_BF561) := bf561
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MACHINE := $(machine-y)
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MACHINE := $(machine-y)
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export MACHINE
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export MACHINE
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cpu-$(CONFIG_BF522) := bf522
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cpu-$(CONFIG_BF525) := bf525
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cpu-$(CONFIG_BF527) := bf527
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cpu-$(CONFIG_BF531) := bf531
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cpu-$(CONFIG_BF531) := bf531
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cpu-$(CONFIG_BF532) := bf532
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cpu-$(CONFIG_BF532) := bf532
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cpu-$(CONFIG_BF533) := bf533
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cpu-$(CONFIG_BF533) := bf533
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File diff suppressed because it is too large
Load Diff
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@ -124,7 +124,7 @@ static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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};
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};
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#endif
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#endif
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#ifdef BF537_FAMILY
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
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static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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(struct gpio_port_t *) PORTFIO,
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(struct gpio_port_t *) PORTFIO,
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(struct gpio_port_t *) PORTGIO,
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(struct gpio_port_t *) PORTGIO,
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@ -139,6 +139,21 @@ static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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#endif
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#endif
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#ifdef BF527_FAMILY
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static unsigned short *port_mux[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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(unsigned short *) PORTF_MUX,
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(unsigned short *) PORTG_MUX,
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(unsigned short *) PORTH_MUX,
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};
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static const
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u8 pmux_offset[][16] =
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{{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
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{ 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
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};
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#endif
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#ifdef BF561_FAMILY
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#ifdef BF561_FAMILY
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static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
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(struct gpio_port_t *) FIO0_FLAG_D,
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(struct gpio_port_t *) FIO0_FLAG_D,
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@ -186,6 +201,10 @@ static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB
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static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
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static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
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#endif
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#endif
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#ifdef BF527_FAMILY
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static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
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#endif
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#ifdef BF561_FAMILY
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#ifdef BF561_FAMILY
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static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
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static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
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#endif
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#endif
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@ -238,7 +257,7 @@ static int cmp_label(unsigned short ident, const char *label)
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return -EINVAL;
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return -EINVAL;
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}
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}
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#ifdef BF537_FAMILY
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#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
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static void port_setup(unsigned short gpio, unsigned short usage)
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static void port_setup(unsigned short gpio, unsigned short usage)
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{
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{
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if (!check_gpio(gpio)) {
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if (!check_gpio(gpio)) {
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@ -354,6 +373,18 @@ inline u16 get_portmux(unsigned short portno)
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return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
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return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
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}
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}
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#elif defined(BF527_FAMILY)
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inline void portmux_setup(unsigned short portno, unsigned short function)
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{
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u16 pmux, ident = P_IDENT(portno);
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u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
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pmux = *port_mux[gpio_bank(ident)];
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pmux &= ~(3 << offset);
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pmux |= (function & 3) << offset;
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*port_mux[gpio_bank(ident)] = pmux;
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SSYNC();
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}
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#else
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#else
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# define portmux_setup(...) do { } while (0)
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# define portmux_setup(...) do { } while (0)
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#endif
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#endif
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@ -11,7 +11,7 @@
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#include <asm/reboot.h>
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#include <asm/reboot.h>
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#include <asm/system.h>
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#include <asm/system.h>
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#if defined(BF537_FAMILY) || defined(BF533_FAMILY)
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#if defined(BF537_FAMILY) || defined(BF533_FAMILY) || defined(BF527_FAMILY)
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#define SYSCR_VAL 0x0
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#define SYSCR_VAL 0x0
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#elif defined(BF561_FAMILY)
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#elif defined(BF561_FAMILY)
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#define SYSCR_VAL 0x20
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#define SYSCR_VAL 0x20
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@ -0,0 +1,251 @@
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if (BF52x)
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menu "BF527 Specific Configuration"
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comment "Alternative Multiplexing Scheme"
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choice
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prompt "SPORT0"
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default BF527_SPORT0_PORTG
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help
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Select PORT used for SPORT0. See Hardware Reference Manual
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config BF527_SPORT0_PORTF
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bool "PORT F"
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help
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PORT F
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config BF527_SPORT0_PORTG
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bool "PORT G"
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help
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PORT G
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endchoice
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choice
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prompt "SPORT0 TSCLK Location"
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depends on BF527_SPORT0_PORTG
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default BF527_SPORT0_TSCLK_PG10
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help
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Select PIN used for SPORT0_TSCLK. See Hardware Reference Manual
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config BF527_SPORT0_TSCLK_PG10
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bool "PORT PG10"
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help
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PORT PG10
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config BF527_SPORT0_TSCLK_PG14
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bool "PORT PG14"
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help
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PORT PG14
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endchoice
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choice
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prompt "UART1"
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default BF527_UART1_PORTG
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help
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Select PORT used for UART1. See Hardware Reference Manual
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config BF527_UART1_PORTF
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bool "PORT F"
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help
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PORT F
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config BF527_UART1_PORTG
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bool "PORT G"
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help
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PORT G
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endchoice
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choice
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prompt "NAND (NFC) Data"
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default BF527_NAND_D_PORTH
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help
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Select PORT used for NAND Data Bus. See Hardware Reference Manual
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||||||
|
config BF527_NAND_D_PORTF
|
||||||
|
bool "PORT F"
|
||||||
|
help
|
||||||
|
PORT F
|
||||||
|
|
||||||
|
config BF527_NAND_D_PORTH
|
||||||
|
bool "PORT H"
|
||||||
|
help
|
||||||
|
PORT H
|
||||||
|
endchoice
|
||||||
|
|
||||||
|
comment "Interrupt Priority Assignment"
|
||||||
|
menu "Priority"
|
||||||
|
|
||||||
|
config IRQ_PLL_WAKEUP
|
||||||
|
int "IRQ_PLL_WAKEUP"
|
||||||
|
default 7
|
||||||
|
config IRQ_DMA0_ERROR
|
||||||
|
int "IRQ_DMA0_ERROR"
|
||||||
|
default 7
|
||||||
|
config IRQ_DMAR0_BLK
|
||||||
|
int "IRQ_DMAR0_BLK"
|
||||||
|
default 7
|
||||||
|
config IRQ_DMAR1_BLK
|
||||||
|
int "IRQ_DMAR1_BLK"
|
||||||
|
default 7
|
||||||
|
config IRQ_DMAR0_OVR
|
||||||
|
int "IRQ_DMAR0_OVR"
|
||||||
|
default 7
|
||||||
|
config IRQ_DMAR1_OVR
|
||||||
|
int "IRQ_DMAR1_OVR"
|
||||||
|
default 7
|
||||||
|
config IRQ_PPI_ERROR
|
||||||
|
int "IRQ_PPI_ERROR"
|
||||||
|
default 7
|
||||||
|
config IRQ_MAC_ERROR
|
||||||
|
int "IRQ_MAC_ERROR"
|
||||||
|
default 7
|
||||||
|
config IRQ_SPORT0_ERROR
|
||||||
|
int "IRQ_SPORT0_ERROR"
|
||||||
|
default 7
|
||||||
|
config IRQ_SPORT1_ERROR
|
||||||
|
int "IRQ_SPORT1_ERROR"
|
||||||
|
default 7
|
||||||
|
config IRQ_UART0_ERROR
|
||||||
|
int "IRQ_UART0_ERROR"
|
||||||
|
default 7
|
||||||
|
config IRQ_UART1_ERROR
|
||||||
|
int "IRQ_UART1_ERROR"
|
||||||
|
default 7
|
||||||
|
config IRQ_RTC
|
||||||
|
int "IRQ_RTC"
|
||||||
|
default 8
|
||||||
|
config IRQ_PPI
|
||||||
|
int "IRQ_PPI"
|
||||||
|
default 8
|
||||||
|
config IRQ_SPORT0_RX
|
||||||
|
int "IRQ_SPORT0_RX"
|
||||||
|
default 9
|
||||||
|
config IRQ_SPORT0_TX
|
||||||
|
int "IRQ_SPORT0_TX"
|
||||||
|
default 9
|
||||||
|
config IRQ_SPORT1_RX
|
||||||
|
int "IRQ_SPORT1_RX"
|
||||||
|
default 9
|
||||||
|
config IRQ_SPORT1_TX
|
||||||
|
int "IRQ_SPORT1_TX"
|
||||||
|
default 9
|
||||||
|
config IRQ_TWI
|
||||||
|
int "IRQ_TWI"
|
||||||
|
default 10
|
||||||
|
config IRQ_SPI
|
||||||
|
int "IRQ_SPI"
|
||||||
|
default 10
|
||||||
|
config IRQ_UART0_RX
|
||||||
|
int "IRQ_UART0_RX"
|
||||||
|
default 10
|
||||||
|
config IRQ_UART0_TX
|
||||||
|
int "IRQ_UART0_TX"
|
||||||
|
default 10
|
||||||
|
config IRQ_UART1_RX
|
||||||
|
int "IRQ_UART1_RX"
|
||||||
|
default 10
|
||||||
|
config IRQ_UART1_TX
|
||||||
|
int "IRQ_UART1_TX"
|
||||||
|
default 10
|
||||||
|
config IRQ_OPTSEC
|
||||||
|
int "IRQ_OPTSEC"
|
||||||
|
default 11
|
||||||
|
config IRQ_CNT
|
||||||
|
int "IRQ_CNT"
|
||||||
|
default 11
|
||||||
|
config IRQ_MAC_RX
|
||||||
|
int "IRQ_MAC_RX"
|
||||||
|
default 11
|
||||||
|
config IRQ_PORTH_INTA
|
||||||
|
int "IRQ_PORTH_INTA"
|
||||||
|
default 11
|
||||||
|
config IRQ_MAC_TX
|
||||||
|
int "IRQ_MAC_TX/NFC"
|
||||||
|
default 11
|
||||||
|
config IRQ_PORTH_INTB
|
||||||
|
int "IRQ_PORTH_INTB"
|
||||||
|
default 11
|
||||||
|
config IRQ_TMR0
|
||||||
|
int "IRQ_TMR0"
|
||||||
|
default 12
|
||||||
|
config IRQ_TMR1
|
||||||
|
int "IRQ_TMR1"
|
||||||
|
default 12
|
||||||
|
config IRQ_TMR2
|
||||||
|
int "IRQ_TMR2"
|
||||||
|
default 12
|
||||||
|
config IRQ_TMR3
|
||||||
|
int "IRQ_TMR3"
|
||||||
|
default 12
|
||||||
|
config IRQ_TMR4
|
||||||
|
int "IRQ_TMR4"
|
||||||
|
default 12
|
||||||
|
config IRQ_TMR5
|
||||||
|
int "IRQ_TMR5"
|
||||||
|
default 12
|
||||||
|
config IRQ_TMR6
|
||||||
|
int "IRQ_TMR6"
|
||||||
|
default 12
|
||||||
|
config IRQ_TMR7
|
||||||
|
int "IRQ_TMR7"
|
||||||
|
default 12
|
||||||
|
config IRQ_PORTG_INTA
|
||||||
|
int "IRQ_PORTG_INTA"
|
||||||
|
default 12
|
||||||
|
config IRQ_PORTG_INTB
|
||||||
|
int "IRQ_PORTG_INTB"
|
||||||
|
default 12
|
||||||
|
config IRQ_MEM_DMA0
|
||||||
|
int "IRQ_MEM_DMA0"
|
||||||
|
default 13
|
||||||
|
config IRQ_MEM_DMA1
|
||||||
|
int "IRQ_MEM_DMA1"
|
||||||
|
default 13
|
||||||
|
config IRQ_WATCH
|
||||||
|
int "IRQ_WATCH"
|
||||||
|
default 13
|
||||||
|
config IRQ_PORTF_INTA
|
||||||
|
int "IRQ_PORTF_INTA"
|
||||||
|
default 13
|
||||||
|
config IRQ_PORTF_INTB
|
||||||
|
int "IRQ_PORTF_INTB"
|
||||||
|
default 13
|
||||||
|
config IRQ_SPI_ERROR
|
||||||
|
int "IRQ_SPI_ERROR"
|
||||||
|
default 7
|
||||||
|
config IRQ_NFC_ERROR
|
||||||
|
int "IRQ_NFC_ERROR"
|
||||||
|
default 7
|
||||||
|
config IRQ_HDMA_ERROR
|
||||||
|
int "IRQ_HDMA_ERROR"
|
||||||
|
default 7
|
||||||
|
config IRQ_HDMA
|
||||||
|
int "IRQ_HDMA"
|
||||||
|
default 7
|
||||||
|
config IRQ_USB_EINT
|
||||||
|
int "IRQ_USB_EINT"
|
||||||
|
default 10
|
||||||
|
config IRQ_USB_INT0
|
||||||
|
int "IRQ_USB_INT0"
|
||||||
|
default 10
|
||||||
|
config IRQ_USB_INT1
|
||||||
|
int "IRQ_USB_INT1"
|
||||||
|
default 10
|
||||||
|
config IRQ_USB_INT2
|
||||||
|
int "IRQ_USB_INT2"
|
||||||
|
default 10
|
||||||
|
config IRQ_USB_DMA
|
||||||
|
int "IRQ_USB_DMA"
|
||||||
|
default 10
|
||||||
|
|
||||||
|
help
|
||||||
|
Enter the priority numbers between 7-13 ONLY. Others are Reserved.
|
||||||
|
This applies to all the above. It is not recommended to assign the
|
||||||
|
highest priority number 7 to UART or any other device.
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
endif
|
||||||
|
|
@ -0,0 +1,9 @@
|
||||||
|
#
|
||||||
|
# arch/blackfin/mach-bf527/Makefile
|
||||||
|
#
|
||||||
|
|
||||||
|
extra-y := head.o
|
||||||
|
|
||||||
|
obj-y := ints-priority.o dma.o
|
||||||
|
|
||||||
|
obj-$(CONFIG_CPU_FREQ) += cpu.o
|
||||||
|
|
@ -0,0 +1,7 @@
|
||||||
|
#
|
||||||
|
# arch/blackfin/mach-bf532/boards/Makefile
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-y += eth_mac.o
|
||||||
|
obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
|
||||||
|
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
* arch/blackfin/mach-bf537/board/eth_mac.c
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007 Analog Devices, Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
|
||||||
|
#if defined(CONFIG_GENERIC_BOARD) || defined(CONFIG_BFIN537_STAMP)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Currently the MAC address is saved in Flash by U-Boot
|
||||||
|
*/
|
||||||
|
#define FLASH_MAC 0x203f0000
|
||||||
|
|
||||||
|
void get_bf537_ether_addr(char *addr)
|
||||||
|
{
|
||||||
|
unsigned int flash_mac = (unsigned int) FLASH_MAC;
|
||||||
|
*(u32 *)(&(addr[0])) = bfin_read32(flash_mac);
|
||||||
|
flash_mac += 4;
|
||||||
|
*(u16 *)(&(addr[4])) = bfin_read16(flash_mac);
|
||||||
|
}
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Provide MAC address function for other specific board setting
|
||||||
|
*/
|
||||||
|
void get_bf537_ether_addr(char *addr)
|
||||||
|
{
|
||||||
|
printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n", __FILE__);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
EXPORT_SYMBOL(get_bf537_ether_addr);
|
||||||
|
|
@ -0,0 +1,737 @@
|
||||||
|
/*
|
||||||
|
* File: arch/blackfin/mach-bf527/boards/ezkit.c
|
||||||
|
* Based on: arch/blackfin/mach-bf537/boards/stamp.c
|
||||||
|
* Author: Aidan Williams <aidan@nicta.com.au>
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description:
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
* Copyright 2005 National ICT Australia (NICTA)
|
||||||
|
* Copyright 2004-2007 Analog Devices Inc.
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, see the file COPYING, or write
|
||||||
|
* to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/device.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
#include <linux/mtd/mtd.h>
|
||||||
|
#include <linux/mtd/partitions.h>
|
||||||
|
#include <linux/spi/spi.h>
|
||||||
|
#include <linux/spi/flash.h>
|
||||||
|
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
|
||||||
|
#include <linux/usb_isp1362.h>
|
||||||
|
#endif
|
||||||
|
#include <linux/pata_platform.h>
|
||||||
|
#include <linux/irq.h>
|
||||||
|
#include <linux/interrupt.h>
|
||||||
|
#include <linux/usb_sl811.h>
|
||||||
|
#include <asm/dma.h>
|
||||||
|
#include <asm/bfin5xx_spi.h>
|
||||||
|
#include <asm/reboot.h>
|
||||||
|
#include <linux/spi/ad7877.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Name the Board for the /proc/cpuinfo
|
||||||
|
*/
|
||||||
|
char *bfin_board_name = "ADDS-BF527-EZKIT";
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Driver needs to know address, irq and flag pin.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ISP1761_BASE 0x203C0000
|
||||||
|
#define ISP1761_IRQ IRQ_PF7
|
||||||
|
|
||||||
|
#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
|
||||||
|
static struct resource bfin_isp1761_resources[] = {
|
||||||
|
[0] = {
|
||||||
|
.name = "isp1761-regs",
|
||||||
|
.start = ISP1761_BASE + 0x00000000,
|
||||||
|
.end = ISP1761_BASE + 0x000fffff,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
},
|
||||||
|
[1] = {
|
||||||
|
.start = ISP1761_IRQ,
|
||||||
|
.end = ISP1761_IRQ,
|
||||||
|
.flags = IORESOURCE_IRQ,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device bfin_isp1761_device = {
|
||||||
|
.name = "isp1761",
|
||||||
|
.id = 0,
|
||||||
|
.num_resources = ARRAY_SIZE(bfin_isp1761_resources),
|
||||||
|
.resource = bfin_isp1761_resources,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device *bfin_isp1761_devices[] = {
|
||||||
|
&bfin_isp1761_device,
|
||||||
|
};
|
||||||
|
|
||||||
|
int __init bfin_isp1761_init(void)
|
||||||
|
{
|
||||||
|
unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
|
||||||
|
|
||||||
|
printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
|
||||||
|
set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
|
||||||
|
|
||||||
|
return platform_add_devices(bfin_isp1761_devices, num_devices);
|
||||||
|
}
|
||||||
|
|
||||||
|
void __exit bfin_isp1761_exit(void)
|
||||||
|
{
|
||||||
|
platform_device_unregister(&bfin_isp1761_device);
|
||||||
|
}
|
||||||
|
|
||||||
|
arch_initcall(bfin_isp1761_init);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
|
||||||
|
static struct resource bfin_pcmcia_cf_resources[] = {
|
||||||
|
{
|
||||||
|
.start = 0x20310000, /* IO PORT */
|
||||||
|
.end = 0x20312000,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.start = 0x20311000, /* Attribute Memory */
|
||||||
|
.end = 0x20311FFF,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.start = IRQ_PF4,
|
||||||
|
.end = IRQ_PF4,
|
||||||
|
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
|
||||||
|
}, {
|
||||||
|
.start = 6, /* Card Detect PF6 */
|
||||||
|
.end = 6,
|
||||||
|
.flags = IORESOURCE_IRQ,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device bfin_pcmcia_cf_device = {
|
||||||
|
.name = "bfin_cf_pcmcia",
|
||||||
|
.id = -1,
|
||||||
|
.num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
|
||||||
|
.resource = bfin_pcmcia_cf_resources,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
|
||||||
|
static struct platform_device rtc_device = {
|
||||||
|
.name = "rtc-bfin",
|
||||||
|
.id = -1,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
|
||||||
|
static struct resource smc91x_resources[] = {
|
||||||
|
{
|
||||||
|
.name = "smc91x-regs",
|
||||||
|
.start = 0x20300300,
|
||||||
|
.end = 0x20300300 + 16,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
|
||||||
|
.start = IRQ_PF7,
|
||||||
|
.end = IRQ_PF7,
|
||||||
|
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
static struct platform_device smc91x_device = {
|
||||||
|
.name = "smc91x",
|
||||||
|
.id = 0,
|
||||||
|
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||||
|
.resource = smc91x_resources,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
|
||||||
|
static struct resource dm9000_resources[] = {
|
||||||
|
[0] = {
|
||||||
|
.start = 0x203FB800,
|
||||||
|
.end = 0x203FB800 + 8,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
},
|
||||||
|
[1] = {
|
||||||
|
.start = IRQ_PF9,
|
||||||
|
.end = IRQ_PF9,
|
||||||
|
.flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device dm9000_device = {
|
||||||
|
.name = "dm9000",
|
||||||
|
.id = -1,
|
||||||
|
.num_resources = ARRAY_SIZE(dm9000_resources),
|
||||||
|
.resource = dm9000_resources,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
|
||||||
|
static struct resource sl811_hcd_resources[] = {
|
||||||
|
{
|
||||||
|
.start = 0x20340000,
|
||||||
|
.end = 0x20340000,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.start = 0x20340004,
|
||||||
|
.end = 0x20340004,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.start = CONFIG_USB_SL811_BFIN_IRQ,
|
||||||
|
.end = CONFIG_USB_SL811_BFIN_IRQ,
|
||||||
|
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
|
||||||
|
void sl811_port_power(struct device *dev, int is_on)
|
||||||
|
{
|
||||||
|
gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
|
||||||
|
gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS);
|
||||||
|
|
||||||
|
if (is_on)
|
||||||
|
gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
|
||||||
|
else
|
||||||
|
gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static struct sl811_platform_data sl811_priv = {
|
||||||
|
.potpg = 10,
|
||||||
|
.power = 250, /* == 500mA */
|
||||||
|
#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
|
||||||
|
.port_power = &sl811_port_power,
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device sl811_hcd_device = {
|
||||||
|
.name = "sl811-hcd",
|
||||||
|
.id = 0,
|
||||||
|
.dev = {
|
||||||
|
.platform_data = &sl811_priv,
|
||||||
|
},
|
||||||
|
.num_resources = ARRAY_SIZE(sl811_hcd_resources),
|
||||||
|
.resource = sl811_hcd_resources,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
|
||||||
|
static struct resource isp1362_hcd_resources[] = {
|
||||||
|
{
|
||||||
|
.start = 0x20360000,
|
||||||
|
.end = 0x20360000,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.start = 0x20360004,
|
||||||
|
.end = 0x20360004,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
|
||||||
|
.end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
|
||||||
|
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct isp1362_platform_data isp1362_priv = {
|
||||||
|
.sel15Kres = 1,
|
||||||
|
.clknotstop = 0,
|
||||||
|
.oc_enable = 0,
|
||||||
|
.int_act_high = 0,
|
||||||
|
.int_edge_triggered = 0,
|
||||||
|
.remote_wakeup_connected = 0,
|
||||||
|
.no_power_switching = 1,
|
||||||
|
.power_switching_mode = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device isp1362_hcd_device = {
|
||||||
|
.name = "isp1362-hcd",
|
||||||
|
.id = 0,
|
||||||
|
.dev = {
|
||||||
|
.platform_data = &isp1362_priv,
|
||||||
|
},
|
||||||
|
.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
|
||||||
|
.resource = isp1362_hcd_resources,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
|
||||||
|
static struct platform_device bfin_mac_device = {
|
||||||
|
.name = "bfin_mac",
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
|
||||||
|
static struct resource net2272_bfin_resources[] = {
|
||||||
|
{
|
||||||
|
.start = 0x20300000,
|
||||||
|
.end = 0x20300000 + 0x100,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
}, {
|
||||||
|
.start = IRQ_PF7,
|
||||||
|
.end = IRQ_PF7,
|
||||||
|
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device net2272_bfin_device = {
|
||||||
|
.name = "net2272",
|
||||||
|
.id = -1,
|
||||||
|
.num_resources = ARRAY_SIZE(net2272_bfin_resources),
|
||||||
|
.resource = net2272_bfin_resources,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
||||||
|
/* all SPI peripherals info goes here */
|
||||||
|
|
||||||
|
#if defined(CONFIG_MTD_M25P80) \
|
||||||
|
|| defined(CONFIG_MTD_M25P80_MODULE)
|
||||||
|
static struct mtd_partition bfin_spi_flash_partitions[] = {
|
||||||
|
{
|
||||||
|
.name = "bootloader",
|
||||||
|
.size = 0x00020000,
|
||||||
|
.offset = 0,
|
||||||
|
.mask_flags = MTD_CAP_ROM
|
||||||
|
}, {
|
||||||
|
.name = "kernel",
|
||||||
|
.size = 0xe0000,
|
||||||
|
.offset = 0x20000
|
||||||
|
}, {
|
||||||
|
.name = "file system",
|
||||||
|
.size = 0x700000,
|
||||||
|
.offset = 0x00100000,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct flash_platform_data bfin_spi_flash_data = {
|
||||||
|
.name = "m25p80",
|
||||||
|
.parts = bfin_spi_flash_partitions,
|
||||||
|
.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
|
||||||
|
.type = "m25p64",
|
||||||
|
};
|
||||||
|
|
||||||
|
/* SPI flash chip (m25p64) */
|
||||||
|
static struct bfin5xx_spi_chip spi_flash_chip_info = {
|
||||||
|
.enable_dma = 0, /* use dma transfer with this chip*/
|
||||||
|
.bits_per_word = 8,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SPI_ADC_BF533) \
|
||||||
|
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
|
||||||
|
/* SPI ADC chip */
|
||||||
|
static struct bfin5xx_spi_chip spi_adc_chip_info = {
|
||||||
|
.enable_dma = 1, /* use dma transfer with this chip*/
|
||||||
|
.bits_per_word = 16,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SND_BLACKFIN_AD1836) \
|
||||||
|
|| defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
|
||||||
|
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
|
||||||
|
.enable_dma = 0,
|
||||||
|
.bits_per_word = 16,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
|
||||||
|
static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
|
||||||
|
.enable_dma = 0,
|
||||||
|
.bits_per_word = 16,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||||
|
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
|
||||||
|
.enable_dma = 1,
|
||||||
|
.bits_per_word = 8,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_PBX)
|
||||||
|
static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
|
||||||
|
.ctl_reg = 0x4, /* send zero */
|
||||||
|
.enable_dma = 0,
|
||||||
|
.bits_per_word = 8,
|
||||||
|
.cs_change_per_word = 1,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
|
||||||
|
static struct bfin5xx_spi_chip ad5304_chip_info = {
|
||||||
|
.enable_dma = 0,
|
||||||
|
.bits_per_word = 16,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
|
||||||
|
static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
|
||||||
|
.enable_dma = 0,
|
||||||
|
.bits_per_word = 16,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct ad7877_platform_data bfin_ad7877_ts_info = {
|
||||||
|
.model = 7877,
|
||||||
|
.vref_delay_usecs = 50, /* internal, no capacitor */
|
||||||
|
.x_plate_ohms = 419,
|
||||||
|
.y_plate_ohms = 486,
|
||||||
|
.pressure_max = 1000,
|
||||||
|
.pressure_min = 0,
|
||||||
|
.stopacq_polarity = 1,
|
||||||
|
.first_conversion_delay = 3,
|
||||||
|
.acquisition_time = 1,
|
||||||
|
.averaging = 1,
|
||||||
|
.pen_down_acc_interval = 1,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static struct spi_board_info bfin_spi_board_info[] __initdata = {
|
||||||
|
#if defined(CONFIG_MTD_M25P80) \
|
||||||
|
|| defined(CONFIG_MTD_M25P80_MODULE)
|
||||||
|
{
|
||||||
|
/* the modalias must be the same as spi device driver name */
|
||||||
|
.modalias = "m25p80", /* Name of spi_driver for this device */
|
||||||
|
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||||
|
.bus_num = 0, /* Framework bus number */
|
||||||
|
.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
|
||||||
|
.platform_data = &bfin_spi_flash_data,
|
||||||
|
.controller_data = &spi_flash_chip_info,
|
||||||
|
.mode = SPI_MODE_3,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SPI_ADC_BF533) \
|
||||||
|
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
|
||||||
|
{
|
||||||
|
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
|
||||||
|
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
|
||||||
|
.bus_num = 0, /* Framework bus number */
|
||||||
|
.chip_select = 1, /* Framework chip select. */
|
||||||
|
.platform_data = NULL, /* No spi_driver specific config */
|
||||||
|
.controller_data = &spi_adc_chip_info,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SND_BLACKFIN_AD1836) \
|
||||||
|
|| defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
|
||||||
|
{
|
||||||
|
.modalias = "ad1836-spi",
|
||||||
|
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
|
||||||
|
.controller_data = &ad1836_spi_chip_info,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
|
||||||
|
{
|
||||||
|
.modalias = "ad9960-spi",
|
||||||
|
.max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = 1,
|
||||||
|
.controller_data = &ad9960_spi_chip_info,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
|
||||||
|
{
|
||||||
|
.modalias = "spi_mmc_dummy",
|
||||||
|
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = 0,
|
||||||
|
.platform_data = NULL,
|
||||||
|
.controller_data = &spi_mmc_chip_info,
|
||||||
|
.mode = SPI_MODE_3,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.modalias = "spi_mmc",
|
||||||
|
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
|
||||||
|
.platform_data = NULL,
|
||||||
|
.controller_data = &spi_mmc_chip_info,
|
||||||
|
.mode = SPI_MODE_3,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_PBX)
|
||||||
|
{
|
||||||
|
.modalias = "fxs-spi",
|
||||||
|
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = 8 - CONFIG_J11_JUMPER,
|
||||||
|
.controller_data = &spi_si3xxx_chip_info,
|
||||||
|
.mode = SPI_MODE_3,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.modalias = "fxo-spi",
|
||||||
|
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = 8 - CONFIG_J19_JUMPER,
|
||||||
|
.controller_data = &spi_si3xxx_chip_info,
|
||||||
|
.mode = SPI_MODE_3,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
|
||||||
|
{
|
||||||
|
.modalias = "ad5304_spi",
|
||||||
|
.max_speed_hz = 1250000, /* max spi clock (SCK) speed in HZ */
|
||||||
|
.bus_num = 0,
|
||||||
|
.chip_select = 2,
|
||||||
|
.platform_data = NULL,
|
||||||
|
.controller_data = &ad5304_chip_info,
|
||||||
|
.mode = SPI_MODE_2,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
|
||||||
|
{
|
||||||
|
.modalias = "ad7877",
|
||||||
|
.platform_data = &bfin_ad7877_ts_info,
|
||||||
|
.irq = IRQ_PF6,
|
||||||
|
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
|
||||||
|
.bus_num = 1,
|
||||||
|
.chip_select = 1,
|
||||||
|
.controller_data = &spi_ad7877_chip_info,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
/* SPI controller data */
|
||||||
|
static struct bfin5xx_spi_master bfin_spi0_info = {
|
||||||
|
.num_chipselect = 8,
|
||||||
|
.enable_dma = 1, /* master has the ability to do dma transfer */
|
||||||
|
};
|
||||||
|
|
||||||
|
/* SPI (0) */
|
||||||
|
static struct resource bfin_spi0_resource[] = {
|
||||||
|
[0] = {
|
||||||
|
.start = SPI0_REGBASE,
|
||||||
|
.end = SPI0_REGBASE + 0xFF,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
},
|
||||||
|
[1] = {
|
||||||
|
.start = CH_SPI,
|
||||||
|
.end = CH_SPI,
|
||||||
|
.flags = IORESOURCE_IRQ,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device bfin_spi0_device = {
|
||||||
|
.name = "bfin-spi",
|
||||||
|
.id = 0, /* Bus number */
|
||||||
|
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
|
||||||
|
.resource = bfin_spi0_resource,
|
||||||
|
.dev = {
|
||||||
|
.platform_data = &bfin_spi0_info, /* Passed to driver */
|
||||||
|
},
|
||||||
|
};
|
||||||
|
#endif /* spi master and devices */
|
||||||
|
|
||||||
|
#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
|
||||||
|
static struct platform_device bfin_fb_device = {
|
||||||
|
.name = "bf537-lq035",
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
|
||||||
|
static struct platform_device bfin_fb_adv7393_device = {
|
||||||
|
.name = "bfin-adv7393",
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
|
||||||
|
static struct resource bfin_uart_resources[] = {
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||||
|
{
|
||||||
|
.start = 0xFFC00400,
|
||||||
|
.end = 0xFFC004FF,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||||||
|
{
|
||||||
|
.start = 0xFFC02000,
|
||||||
|
.end = 0xFFC020FF,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device bfin_uart_device = {
|
||||||
|
.name = "bfin-uart",
|
||||||
|
.id = 1,
|
||||||
|
.num_resources = ARRAY_SIZE(bfin_uart_resources),
|
||||||
|
.resource = bfin_uart_resources,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
|
||||||
|
static struct resource bfin_twi0_resource[] = {
|
||||||
|
[0] = {
|
||||||
|
.start = TWI0_REGBASE,
|
||||||
|
.end = TWI0_REGBASE,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
},
|
||||||
|
[1] = {
|
||||||
|
.start = IRQ_TWI,
|
||||||
|
.end = IRQ_TWI,
|
||||||
|
.flags = IORESOURCE_IRQ,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device i2c_bfin_twi_device = {
|
||||||
|
.name = "i2c-bfin-twi",
|
||||||
|
.id = 0,
|
||||||
|
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
|
||||||
|
.resource = bfin_twi0_resource,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
||||||
|
static struct platform_device bfin_sport0_uart_device = {
|
||||||
|
.name = "bfin-sport-uart",
|
||||||
|
.id = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device bfin_sport1_uart_device = {
|
||||||
|
.name = "bfin-sport-uart",
|
||||||
|
.id = 1,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
|
||||||
|
#define PATA_INT 55
|
||||||
|
|
||||||
|
static struct pata_platform_info bfin_pata_platform_data = {
|
||||||
|
.ioport_shift = 1,
|
||||||
|
.irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct resource bfin_pata_resources[] = {
|
||||||
|
{
|
||||||
|
.start = 0x20314020,
|
||||||
|
.end = 0x2031403F,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.start = 0x2031401C,
|
||||||
|
.end = 0x2031401F,
|
||||||
|
.flags = IORESOURCE_MEM,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.start = PATA_INT,
|
||||||
|
.end = PATA_INT,
|
||||||
|
.flags = IORESOURCE_IRQ,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_device bfin_pata_device = {
|
||||||
|
.name = "pata_platform",
|
||||||
|
.id = -1,
|
||||||
|
.num_resources = ARRAY_SIZE(bfin_pata_resources),
|
||||||
|
.resource = bfin_pata_resources,
|
||||||
|
.dev = {
|
||||||
|
.platform_data = &bfin_pata_platform_data,
|
||||||
|
}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static struct platform_device *stamp_devices[] __initdata = {
|
||||||
|
#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
|
||||||
|
&bfin_pcmcia_cf_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
|
||||||
|
&rtc_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
|
||||||
|
&sl811_hcd_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
|
||||||
|
&isp1362_hcd_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
|
||||||
|
&smc91x_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
|
||||||
|
&dm9000_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
|
||||||
|
&bfin_mac_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
|
||||||
|
&net2272_bfin_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
||||||
|
&bfin_spi0_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
|
||||||
|
&bfin_fb_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
|
||||||
|
&bfin_fb_adv7393_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
|
||||||
|
&bfin_uart_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
|
||||||
|
&i2c_bfin_twi_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
||||||
|
&bfin_sport0_uart_device,
|
||||||
|
&bfin_sport1_uart_device,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
|
||||||
|
&bfin_pata_device,
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init stamp_init(void)
|
||||||
|
{
|
||||||
|
printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
|
||||||
|
platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
|
||||||
|
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
|
||||||
|
spi_register_board_info(bfin_spi_board_info,
|
||||||
|
ARRAY_SIZE(bfin_spi_board_info));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
|
||||||
|
irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
|
||||||
|
#endif
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
arch_initcall(stamp_init);
|
||||||
|
|
||||||
|
void native_machine_restart(char *cmd)
|
||||||
|
{
|
||||||
|
/* workaround reboot hang when booting from SPI */
|
||||||
|
if ((bfin_read_SYSCR() & 0x7) == 0x3)
|
||||||
|
bfin_gpio_reset_spi0_ssel1();
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,161 @@
|
||||||
|
/*
|
||||||
|
* File: arch/blackfin/mach-bf527/cpu.c
|
||||||
|
* Based on: arch/blackfin/mach-bf537/cpu.c
|
||||||
|
* Author: michael.kang@analog.com
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description: clock scaling for the bf527
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
* Copyright 2004-2007 Analog Devices Inc.
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, see the file COPYING, or write
|
||||||
|
* to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/kernel.h>
|
||||||
|
#include <linux/types.h>
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <linux/cpufreq.h>
|
||||||
|
#include <asm/dpmc.h>
|
||||||
|
#include <linux/fs.h>
|
||||||
|
#include <asm/bfin-global.h>
|
||||||
|
|
||||||
|
/* CONFIG_CLKIN_HZ=11059200 */
|
||||||
|
#define VCO5 (CONFIG_CLKIN_HZ*45) /*497664000 */
|
||||||
|
#define VCO4 (CONFIG_CLKIN_HZ*36) /*398131200 */
|
||||||
|
#define VCO3 (CONFIG_CLKIN_HZ*27) /*298598400 */
|
||||||
|
#define VCO2 (CONFIG_CLKIN_HZ*18) /*199065600 */
|
||||||
|
#define VCO1 (CONFIG_CLKIN_HZ*9) /*99532800 */
|
||||||
|
#define VCO(x) VCO##x
|
||||||
|
|
||||||
|
#define MFREQ(x) {VCO(x), VCO(x)/4}, {VCO(x), VCO(x)/2}, {VCO(x), VCO(x)}
|
||||||
|
/* frequency */
|
||||||
|
static struct cpufreq_frequency_table bf527_freq_table[] = {
|
||||||
|
MFREQ(1),
|
||||||
|
MFREQ(3),
|
||||||
|
{VCO4, VCO4 / 2}, {VCO4, VCO4},
|
||||||
|
MFREQ(5),
|
||||||
|
{0, CPUFREQ_TABLE_END},
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* dpmc_fops->ioctl()
|
||||||
|
* static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
|
||||||
|
*/
|
||||||
|
static int bf527_getfreq(unsigned int cpu)
|
||||||
|
{
|
||||||
|
unsigned long cclk_mhz;
|
||||||
|
|
||||||
|
/* The driver only support single cpu */
|
||||||
|
if (cpu == 0)
|
||||||
|
dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz);
|
||||||
|
else
|
||||||
|
cclk_mhz = -1;
|
||||||
|
|
||||||
|
return cclk_mhz;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int bf527_target(struct cpufreq_policy *policy,
|
||||||
|
unsigned int target_freq, unsigned int relation)
|
||||||
|
{
|
||||||
|
unsigned long cclk_mhz;
|
||||||
|
unsigned long vco_mhz;
|
||||||
|
unsigned long flags;
|
||||||
|
unsigned int index;
|
||||||
|
struct cpufreq_freqs freqs;
|
||||||
|
|
||||||
|
if (cpufreq_frequency_table_target
|
||||||
|
(policy, bf527_freq_table, target_freq, relation, &index))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
cclk_mhz = bf527_freq_table[index].frequency;
|
||||||
|
vco_mhz = bf527_freq_table[index].index;
|
||||||
|
|
||||||
|
dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz);
|
||||||
|
freqs.old = bf527_getfreq(0);
|
||||||
|
freqs.new = cclk_mhz;
|
||||||
|
freqs.cpu = 0;
|
||||||
|
|
||||||
|
pr_debug
|
||||||
|
("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n",
|
||||||
|
cclk_mhz, vco_mhz, index, target_freq, freqs.old);
|
||||||
|
|
||||||
|
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
||||||
|
local_irq_save(flags);
|
||||||
|
dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz);
|
||||||
|
local_irq_restore(flags);
|
||||||
|
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
||||||
|
|
||||||
|
vco_mhz = get_vco();
|
||||||
|
cclk_mhz = get_cclk();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
|
||||||
|
* this platform, anyway.
|
||||||
|
*/
|
||||||
|
static int bf527_verify_speed(struct cpufreq_policy *policy)
|
||||||
|
{
|
||||||
|
return cpufreq_frequency_table_verify(policy, &bf527_freq_table);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __init __bf527_cpu_init(struct cpufreq_policy *policy)
|
||||||
|
{
|
||||||
|
if (policy->cpu != 0)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
|
||||||
|
|
||||||
|
policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
|
||||||
|
/*Now ,only support one cpu */
|
||||||
|
policy->cur = bf527_getfreq(0);
|
||||||
|
cpufreq_frequency_table_get_attr(bf527_freq_table, policy->cpu);
|
||||||
|
return cpufreq_frequency_table_cpuinfo(policy, bf527_freq_table);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct freq_attr *bf527_freq_attr[] = {
|
||||||
|
&cpufreq_freq_attr_scaling_available_freqs,
|
||||||
|
NULL,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct cpufreq_driver bf527_driver = {
|
||||||
|
.verify = bf527_verify_speed,
|
||||||
|
.target = bf527_target,
|
||||||
|
.get = bf527_getfreq,
|
||||||
|
.init = __bf527_cpu_init,
|
||||||
|
.name = "bf527",
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
.attr = bf527_freq_attr,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int __init bf527_cpu_init(void)
|
||||||
|
{
|
||||||
|
return cpufreq_register_driver(&bf527_driver);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __exit bf527_cpu_exit(void)
|
||||||
|
{
|
||||||
|
cpufreq_unregister_driver(&bf527_driver);
|
||||||
|
}
|
||||||
|
|
||||||
|
MODULE_AUTHOR("Mickael Kang");
|
||||||
|
MODULE_DESCRIPTION("cpufreq driver for bf527 CPU");
|
||||||
|
MODULE_LICENSE("GPL");
|
||||||
|
|
||||||
|
module_init(bf527_cpu_init);
|
||||||
|
module_exit(bf527_cpu_exit);
|
||||||
|
|
@ -0,0 +1,115 @@
|
||||||
|
/*
|
||||||
|
* File: arch/blackfin/mach-bf527/dma.c
|
||||||
|
* Based on:
|
||||||
|
* Author:
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description: This file contains the simple DMA Implementation for Blackfin
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
* Copyright 2004-2007 Analog Devices Inc.
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, see the file COPYING, or write
|
||||||
|
* to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
#include <asm/dma.h>
|
||||||
|
|
||||||
|
struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
|
||||||
|
(struct dma_register *) DMA0_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) DMA1_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) DMA2_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) DMA3_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) DMA4_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) DMA5_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) DMA6_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) DMA7_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) DMA8_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) DMA9_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) DMA10_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) DMA11_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
|
||||||
|
(struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
|
||||||
|
};
|
||||||
|
|
||||||
|
int channel2irq(unsigned int channel)
|
||||||
|
{
|
||||||
|
int ret_irq = -1;
|
||||||
|
|
||||||
|
switch (channel) {
|
||||||
|
case CH_PPI:
|
||||||
|
ret_irq = IRQ_PPI;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_EMAC_RX:
|
||||||
|
ret_irq = IRQ_MAC_RX;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_EMAC_TX:
|
||||||
|
ret_irq = IRQ_MAC_TX;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_UART1_RX:
|
||||||
|
ret_irq = IRQ_UART1_RX;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_UART1_TX:
|
||||||
|
ret_irq = IRQ_UART1_TX;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_SPORT0_RX:
|
||||||
|
ret_irq = IRQ_SPORT0_RX;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_SPORT0_TX:
|
||||||
|
ret_irq = IRQ_SPORT0_TX;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_SPORT1_RX:
|
||||||
|
ret_irq = IRQ_SPORT1_RX;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_SPORT1_TX:
|
||||||
|
ret_irq = IRQ_SPORT1_TX;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_SPI:
|
||||||
|
ret_irq = IRQ_SPI;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_UART0_RX:
|
||||||
|
ret_irq = IRQ_UART0_RX;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_UART0_TX:
|
||||||
|
ret_irq = IRQ_UART0_TX;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_MEM_STREAM0_SRC:
|
||||||
|
case CH_MEM_STREAM0_DEST:
|
||||||
|
ret_irq = IRQ_MEM_DMA0;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CH_MEM_STREAM1_SRC:
|
||||||
|
case CH_MEM_STREAM1_DEST:
|
||||||
|
ret_irq = IRQ_MEM_DMA1;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return ret_irq;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,456 @@
|
||||||
|
/*
|
||||||
|
* File: arch/blackfin/mach-bf527/head.S
|
||||||
|
* Based on: arch/blackfin/mach-bf533/head.S
|
||||||
|
* Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
|
||||||
|
*
|
||||||
|
* Created: 1998
|
||||||
|
* Description: Startup code for Blackfin BF537
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
* Copyright 2004-2007 Analog Devices Inc.
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, see the file COPYING, or write
|
||||||
|
* to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/linkage.h>
|
||||||
|
#include <linux/init.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
#include <asm/trace.h>
|
||||||
|
|
||||||
|
#if CONFIG_BFIN_KERNEL_CLOCK
|
||||||
|
#include <asm/mach-common/clocks.h>
|
||||||
|
#include <asm/mach/mem_init.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
.global __rambase
|
||||||
|
.global __ramstart
|
||||||
|
.global __ramend
|
||||||
|
.extern ___bss_stop
|
||||||
|
.extern ___bss_start
|
||||||
|
.extern _bf53x_relocate_l1_mem
|
||||||
|
|
||||||
|
#define INITIAL_STACK 0xFFB01000
|
||||||
|
|
||||||
|
__INIT
|
||||||
|
|
||||||
|
ENTRY(__start)
|
||||||
|
/* R0: argument of command line string, passed from uboot, save it */
|
||||||
|
R7 = R0;
|
||||||
|
/* Enable Cycle Counter and Nesting Of Interrupts */
|
||||||
|
#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
|
||||||
|
R0 = SYSCFG_SNEN;
|
||||||
|
#else
|
||||||
|
R0 = SYSCFG_SNEN | SYSCFG_CCEN;
|
||||||
|
#endif
|
||||||
|
SYSCFG = R0;
|
||||||
|
R0 = 0;
|
||||||
|
|
||||||
|
/* Clear Out All the data and pointer Registers */
|
||||||
|
R1 = R0;
|
||||||
|
R2 = R0;
|
||||||
|
R3 = R0;
|
||||||
|
R4 = R0;
|
||||||
|
R5 = R0;
|
||||||
|
R6 = R0;
|
||||||
|
|
||||||
|
P0 = R0;
|
||||||
|
P1 = R0;
|
||||||
|
P2 = R0;
|
||||||
|
P3 = R0;
|
||||||
|
P4 = R0;
|
||||||
|
P5 = R0;
|
||||||
|
|
||||||
|
LC0 = r0;
|
||||||
|
LC1 = r0;
|
||||||
|
L0 = r0;
|
||||||
|
L1 = r0;
|
||||||
|
L2 = r0;
|
||||||
|
L3 = r0;
|
||||||
|
|
||||||
|
/* Clear Out All the DAG Registers */
|
||||||
|
B0 = r0;
|
||||||
|
B1 = r0;
|
||||||
|
B2 = r0;
|
||||||
|
B3 = r0;
|
||||||
|
|
||||||
|
I0 = r0;
|
||||||
|
I1 = r0;
|
||||||
|
I2 = r0;
|
||||||
|
I3 = r0;
|
||||||
|
|
||||||
|
M0 = r0;
|
||||||
|
M1 = r0;
|
||||||
|
M2 = r0;
|
||||||
|
M3 = r0;
|
||||||
|
|
||||||
|
trace_buffer_init(p0,r0);
|
||||||
|
P0 = R1;
|
||||||
|
R0 = R1;
|
||||||
|
|
||||||
|
/* Turn off the icache */
|
||||||
|
p0.l = LO(IMEM_CONTROL);
|
||||||
|
p0.h = HI(IMEM_CONTROL);
|
||||||
|
R1 = [p0];
|
||||||
|
R0 = ~ENICPLB;
|
||||||
|
R0 = R0 & R1;
|
||||||
|
|
||||||
|
/* Anomaly 05000125 */
|
||||||
|
#if ANOMALY_05000125
|
||||||
|
CLI R2;
|
||||||
|
SSYNC;
|
||||||
|
#endif
|
||||||
|
[p0] = R0;
|
||||||
|
SSYNC;
|
||||||
|
#if ANOMALY_05000125
|
||||||
|
STI R2;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Turn off the dcache */
|
||||||
|
p0.l = LO(DMEM_CONTROL);
|
||||||
|
p0.h = HI(DMEM_CONTROL);
|
||||||
|
R1 = [p0];
|
||||||
|
R0 = ~ENDCPLB;
|
||||||
|
R0 = R0 & R1;
|
||||||
|
|
||||||
|
/* Anomaly 05000125 */
|
||||||
|
#if ANOMALY_05000125
|
||||||
|
CLI R2;
|
||||||
|
SSYNC;
|
||||||
|
#endif
|
||||||
|
[p0] = R0;
|
||||||
|
SSYNC;
|
||||||
|
#if ANOMALY_05000125
|
||||||
|
STI R2;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF527)
|
||||||
|
p0.h = hi(EMAC_SYSTAT);
|
||||||
|
p0.l = lo(EMAC_SYSTAT);
|
||||||
|
R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
|
||||||
|
R0.l = 0xFFFF;
|
||||||
|
[P0] = R0;
|
||||||
|
SSYNC;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Initialise UART - when booting from u-boot, the UART is not disabled
|
||||||
|
* so if we dont initalize here, our serial console gets hosed */
|
||||||
|
p0.h = hi(UART1_LCR);
|
||||||
|
p0.l = lo(UART1_LCR);
|
||||||
|
r0 = 0x0(Z);
|
||||||
|
w[p0] = r0.L; /* To enable DLL writes */
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p0.h = hi(UART1_DLL);
|
||||||
|
p0.l = lo(UART1_DLL);
|
||||||
|
r0 = 0x0(Z);
|
||||||
|
w[p0] = r0.L;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p0.h = hi(UART1_DLH);
|
||||||
|
p0.l = lo(UART1_DLH);
|
||||||
|
r0 = 0x00(Z);
|
||||||
|
w[p0] = r0.L;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p0.h = hi(UART1_GCTL);
|
||||||
|
p0.l = lo(UART1_GCTL);
|
||||||
|
r0 = 0x0(Z);
|
||||||
|
w[p0] = r0.L; /* To enable UART clock */
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/* Initialize stack pointer */
|
||||||
|
sp.l = lo(INITIAL_STACK);
|
||||||
|
sp.h = hi(INITIAL_STACK);
|
||||||
|
fp = sp;
|
||||||
|
usp = sp;
|
||||||
|
|
||||||
|
#ifdef CONFIG_EARLY_PRINTK
|
||||||
|
SP += -12;
|
||||||
|
call _init_early_exception_vectors;
|
||||||
|
SP += 12;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
|
||||||
|
call _bf53x_relocate_l1_mem;
|
||||||
|
#if CONFIG_BFIN_KERNEL_CLOCK
|
||||||
|
call _start_dma_code;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Code for initializing Async memory banks */
|
||||||
|
|
||||||
|
p2.h = hi(EBIU_AMBCTL1);
|
||||||
|
p2.l = lo(EBIU_AMBCTL1);
|
||||||
|
r0.h = hi(AMBCTL1VAL);
|
||||||
|
r0.l = lo(AMBCTL1VAL);
|
||||||
|
[p2] = r0;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p2.h = hi(EBIU_AMBCTL0);
|
||||||
|
p2.l = lo(EBIU_AMBCTL0);
|
||||||
|
r0.h = hi(AMBCTL0VAL);
|
||||||
|
r0.l = lo(AMBCTL0VAL);
|
||||||
|
[p2] = r0;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p2.h = hi(EBIU_AMGCTL);
|
||||||
|
p2.l = lo(EBIU_AMGCTL);
|
||||||
|
r0 = AMGCTLVAL;
|
||||||
|
w[p2] = r0;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/* This section keeps the processor in supervisor mode
|
||||||
|
* during kernel boot. Switches to user mode at end of boot.
|
||||||
|
* See page 3-9 of Hardware Reference manual for documentation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* EVT15 = _real_start */
|
||||||
|
|
||||||
|
p0.l = lo(EVT15);
|
||||||
|
p0.h = hi(EVT15);
|
||||||
|
p1.l = _real_start;
|
||||||
|
p1.h = _real_start;
|
||||||
|
[p0] = p1;
|
||||||
|
csync;
|
||||||
|
|
||||||
|
p0.l = lo(IMASK);
|
||||||
|
p0.h = hi(IMASK);
|
||||||
|
p1.l = IMASK_IVG15;
|
||||||
|
p1.h = 0x0;
|
||||||
|
[p0] = p1;
|
||||||
|
csync;
|
||||||
|
|
||||||
|
raise 15;
|
||||||
|
p0.l = .LWAIT_HERE;
|
||||||
|
p0.h = .LWAIT_HERE;
|
||||||
|
reti = p0;
|
||||||
|
#if ANOMALY_05000281
|
||||||
|
nop; nop; nop;
|
||||||
|
#endif
|
||||||
|
rti;
|
||||||
|
|
||||||
|
.LWAIT_HERE:
|
||||||
|
jump .LWAIT_HERE;
|
||||||
|
ENDPROC(__start)
|
||||||
|
|
||||||
|
ENTRY(_real_start)
|
||||||
|
[ -- sp ] = reti;
|
||||||
|
p0.l = lo(WDOG_CTL);
|
||||||
|
p0.h = hi(WDOG_CTL);
|
||||||
|
r0 = 0xAD6(z);
|
||||||
|
w[p0] = r0; /* watchdog off for now */
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/* Code update for BSS size == 0
|
||||||
|
* Zero out the bss region.
|
||||||
|
*/
|
||||||
|
|
||||||
|
p1.l = ___bss_start;
|
||||||
|
p1.h = ___bss_start;
|
||||||
|
p2.l = ___bss_stop;
|
||||||
|
p2.h = ___bss_stop;
|
||||||
|
r0 = 0;
|
||||||
|
p2 -= p1;
|
||||||
|
lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
|
||||||
|
.L_clear_bss:
|
||||||
|
B[p1++] = r0;
|
||||||
|
|
||||||
|
/* In case there is a NULL pointer reference
|
||||||
|
* Zero out region before stext
|
||||||
|
*/
|
||||||
|
|
||||||
|
p1.l = 0x0;
|
||||||
|
p1.h = 0x0;
|
||||||
|
r0.l = __stext;
|
||||||
|
r0.h = __stext;
|
||||||
|
r0 = r0 >> 1;
|
||||||
|
p2 = r0;
|
||||||
|
r0 = 0;
|
||||||
|
lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
|
||||||
|
.L_clear_zero:
|
||||||
|
W[p1++] = r0;
|
||||||
|
|
||||||
|
/* pass the uboot arguments to the global value command line */
|
||||||
|
R0 = R7;
|
||||||
|
call _cmdline_init;
|
||||||
|
|
||||||
|
p1.l = __rambase;
|
||||||
|
p1.h = __rambase;
|
||||||
|
r0.l = __sdata;
|
||||||
|
r0.h = __sdata;
|
||||||
|
[p1] = r0;
|
||||||
|
|
||||||
|
p1.l = __ramstart;
|
||||||
|
p1.h = __ramstart;
|
||||||
|
p3.l = ___bss_stop;
|
||||||
|
p3.h = ___bss_stop;
|
||||||
|
|
||||||
|
r1 = p3;
|
||||||
|
[p1] = r1;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* load the current thread pointer and stack
|
||||||
|
*/
|
||||||
|
r1.l = _init_thread_union;
|
||||||
|
r1.h = _init_thread_union;
|
||||||
|
|
||||||
|
r2.l = 0x2000;
|
||||||
|
r2.h = 0x0000;
|
||||||
|
r1 = r1 + r2;
|
||||||
|
sp = r1;
|
||||||
|
usp = sp;
|
||||||
|
fp = sp;
|
||||||
|
jump.l _start_kernel;
|
||||||
|
ENDPROC(_real_start)
|
||||||
|
|
||||||
|
__FINIT
|
||||||
|
|
||||||
|
.section .l1.text
|
||||||
|
#if CONFIG_BFIN_KERNEL_CLOCK
|
||||||
|
ENTRY(_start_dma_code)
|
||||||
|
|
||||||
|
/* Enable PHY CLK buffer output */
|
||||||
|
p0.h = hi(VR_CTL);
|
||||||
|
p0.l = lo(VR_CTL);
|
||||||
|
r0.l = w[p0];
|
||||||
|
bitset(r0, 14);
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p0.h = hi(SIC_IWR0);
|
||||||
|
p0.l = lo(SIC_IWR0);
|
||||||
|
r0.l = 0x1;
|
||||||
|
r0.h = 0x0;
|
||||||
|
[p0] = r0;
|
||||||
|
SSYNC;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set PLL_CTL
|
||||||
|
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
|
||||||
|
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
|
||||||
|
* - [7] = output delay (add 200ps of delay to mem signals)
|
||||||
|
* - [6] = input delay (add 200ps of input delay to mem signals)
|
||||||
|
* - [5] = PDWN : 1=All Clocks off
|
||||||
|
* - [3] = STOPCK : 1=Core Clock off
|
||||||
|
* - [1] = PLL_OFF : 1=Disable Power to PLL
|
||||||
|
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
|
||||||
|
* all other bits set to zero
|
||||||
|
*/
|
||||||
|
|
||||||
|
p0.h = hi(PLL_LOCKCNT);
|
||||||
|
p0.l = lo(PLL_LOCKCNT);
|
||||||
|
r0 = 0x300(Z);
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
P2.H = hi(EBIU_SDGCTL);
|
||||||
|
P2.L = lo(EBIU_SDGCTL);
|
||||||
|
R0 = [P2];
|
||||||
|
BITSET (R0, 24);
|
||||||
|
[P2] = R0;
|
||||||
|
SSYNC;
|
||||||
|
|
||||||
|
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
|
||||||
|
r0 = r0 << 9; /* Shift it over, */
|
||||||
|
r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
|
||||||
|
r0 = r1 | r0;
|
||||||
|
r1 = PLL_BYPASS; /* Bypass the PLL? */
|
||||||
|
r1 = r1 << 8; /* Shift it over */
|
||||||
|
r0 = r1 | r0; /* add them all together */
|
||||||
|
|
||||||
|
p0.h = hi(PLL_CTL);
|
||||||
|
p0.l = lo(PLL_CTL); /* Load the address */
|
||||||
|
cli r2; /* Disable interrupts */
|
||||||
|
ssync;
|
||||||
|
w[p0] = r0.l; /* Set the value */
|
||||||
|
idle; /* Wait for the PLL to stablize */
|
||||||
|
sti r2; /* Enable interrupts */
|
||||||
|
|
||||||
|
.Lcheck_again:
|
||||||
|
p0.h = hi(PLL_STAT);
|
||||||
|
p0.l = lo(PLL_STAT);
|
||||||
|
R0 = W[P0](Z);
|
||||||
|
CC = BITTST(R0,5);
|
||||||
|
if ! CC jump .Lcheck_again;
|
||||||
|
|
||||||
|
/* Configure SCLK & CCLK Dividers */
|
||||||
|
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
|
||||||
|
p0.h = hi(PLL_DIV);
|
||||||
|
p0.l = lo(PLL_DIV);
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p0.l = lo(EBIU_SDRRC);
|
||||||
|
p0.h = hi(EBIU_SDRRC);
|
||||||
|
r0 = mem_SDRRC;
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p0.l = LO(EBIU_SDBCTL);
|
||||||
|
p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
|
||||||
|
r0 = mem_SDBCTL;
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
P2.H = hi(EBIU_SDGCTL);
|
||||||
|
P2.L = lo(EBIU_SDGCTL);
|
||||||
|
R0 = [P2];
|
||||||
|
BITCLR (R0, 24);
|
||||||
|
p0.h = hi(EBIU_SDSTAT);
|
||||||
|
p0.l = lo(EBIU_SDSTAT);
|
||||||
|
r2.l = w[p0];
|
||||||
|
cc = bittst(r2,3);
|
||||||
|
if !cc jump .Lskip;
|
||||||
|
NOP;
|
||||||
|
BITSET (R0, 23);
|
||||||
|
.Lskip:
|
||||||
|
[P2] = R0;
|
||||||
|
SSYNC;
|
||||||
|
|
||||||
|
R0.L = lo(mem_SDGCTL);
|
||||||
|
R0.H = hi(mem_SDGCTL);
|
||||||
|
R1 = [p2];
|
||||||
|
R1 = R1 | R0;
|
||||||
|
[P2] = R1;
|
||||||
|
SSYNC;
|
||||||
|
|
||||||
|
p0.h = hi(SIC_IWR0);
|
||||||
|
p0.l = lo(SIC_IWR0);
|
||||||
|
r0.l = lo(IWR_ENABLE_ALL);
|
||||||
|
r0.h = hi(IWR_ENABLE_ALL);
|
||||||
|
[p0] = r0;
|
||||||
|
SSYNC;
|
||||||
|
|
||||||
|
RTS;
|
||||||
|
ENDPROC(_start_dma_code)
|
||||||
|
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
|
||||||
|
|
||||||
|
.data
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set up the usable of RAM stuff. Size of RAM is determined then
|
||||||
|
* an initial stack set up at the end.
|
||||||
|
*/
|
||||||
|
|
||||||
|
.align 4
|
||||||
|
__rambase:
|
||||||
|
.long 0
|
||||||
|
__ramstart:
|
||||||
|
.long 0
|
||||||
|
__ramend:
|
||||||
|
.long 0
|
||||||
|
|
@ -0,0 +1,100 @@
|
||||||
|
/*
|
||||||
|
* File: arch/blackfin/mach-bf537/ints-priority.c
|
||||||
|
* Based on: arch/blackfin/mach-bf533/ints-priority.c
|
||||||
|
* Author: Michael Hennerich (michael.hennerich@analog.com)
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description: Set up the interrupt priorities
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
* Copyright 2004-2007 Analog Devices Inc.
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, see the file COPYING, or write
|
||||||
|
* to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/irq.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
|
||||||
|
void program_IAR(void)
|
||||||
|
{
|
||||||
|
/* Program the IAR0 Register with the configured priority */
|
||||||
|
bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
|
||||||
|
((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
|
||||||
|
((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
|
||||||
|
((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
|
||||||
|
((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
|
||||||
|
((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
|
||||||
|
((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
|
||||||
|
((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
|
||||||
|
|
||||||
|
|
||||||
|
bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
|
||||||
|
((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
|
||||||
|
((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
|
||||||
|
((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
|
||||||
|
((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
|
||||||
|
((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
|
||||||
|
|
||||||
|
bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
|
||||||
|
((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
|
||||||
|
((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
|
||||||
|
((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
|
||||||
|
((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
|
||||||
|
((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
|
||||||
|
((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
|
||||||
|
((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
|
||||||
|
|
||||||
|
bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
|
||||||
|
((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
|
||||||
|
((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
|
||||||
|
((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
|
||||||
|
((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
|
||||||
|
((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
|
||||||
|
((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
|
||||||
|
((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
|
||||||
|
|
||||||
|
bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
|
||||||
|
((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
|
||||||
|
((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
|
||||||
|
((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
|
||||||
|
((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) |
|
||||||
|
((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
|
||||||
|
((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
|
||||||
|
((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS));
|
||||||
|
|
||||||
|
bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
|
||||||
|
((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
|
||||||
|
((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
|
||||||
|
((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
|
||||||
|
((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
|
||||||
|
((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
|
||||||
|
((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
|
||||||
|
((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS));
|
||||||
|
|
||||||
|
bfin_write_SIC_IAR6(((CONFIG_IRQ_NFC_ERROR - 7) << IRQ_NFC_ERROR_POS) |
|
||||||
|
((CONFIG_IRQ_HDMA_ERROR - 7) << IRQ_HDMA_ERROR_POS) |
|
||||||
|
((CONFIG_IRQ_HDMA - 7) << IRQ_HDMA_POS) |
|
||||||
|
((CONFIG_IRQ_USB_EINT - 7) << IRQ_USB_EINT_POS) |
|
||||||
|
((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
|
||||||
|
((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
|
||||||
|
((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
|
||||||
|
((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS));
|
||||||
|
|
||||||
|
SSYNC();
|
||||||
|
}
|
||||||
|
|
@ -92,10 +92,15 @@ static void __init search_IAR(void)
|
||||||
|
|
||||||
for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
|
for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
|
||||||
int iar_shift = (irqn & 7) * 4;
|
int iar_shift = (irqn & 7) * 4;
|
||||||
if (ivg ==
|
if (ivg ==
|
||||||
(0xf &
|
(0xf &
|
||||||
|
#ifndef CONFIG_BF52x
|
||||||
bfin_read32((unsigned long *)SIC_IAR0 +
|
bfin_read32((unsigned long *)SIC_IAR0 +
|
||||||
(irqn >> 3)) >> iar_shift)) {
|
(irqn >> 3)) >> iar_shift)) {
|
||||||
|
#else
|
||||||
|
bfin_read32((unsigned long *)SIC_IAR0 +
|
||||||
|
((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
|
||||||
|
#endif
|
||||||
ivg_table[irq_pos].irqno = IVG7 + irqn;
|
ivg_table[irq_pos].irqno = IVG7 + irqn;
|
||||||
ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
|
ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
|
||||||
ivg7_13[ivg].istop++;
|
ivg7_13[ivg].istop++;
|
||||||
|
|
@ -140,7 +145,7 @@ static void bfin_core_unmask_irq(unsigned int irq)
|
||||||
|
|
||||||
static void bfin_internal_mask_irq(unsigned int irq)
|
static void bfin_internal_mask_irq(unsigned int irq)
|
||||||
{
|
{
|
||||||
#ifndef CONFIG_BF54x
|
#ifdef CONFIG_BF53x
|
||||||
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
|
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
|
||||||
~(1 << (irq - (IRQ_CORETMR + 1))));
|
~(1 << (irq - (IRQ_CORETMR + 1))));
|
||||||
#else
|
#else
|
||||||
|
|
@ -155,7 +160,7 @@ static void bfin_internal_mask_irq(unsigned int irq)
|
||||||
|
|
||||||
static void bfin_internal_unmask_irq(unsigned int irq)
|
static void bfin_internal_unmask_irq(unsigned int irq)
|
||||||
{
|
{
|
||||||
#ifndef CONFIG_BF54x
|
#ifdef CONFIG_BF53x
|
||||||
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
|
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
|
||||||
(1 << (irq - (IRQ_CORETMR + 1))));
|
(1 << (irq - (IRQ_CORETMR + 1))));
|
||||||
#else
|
#else
|
||||||
|
|
@ -750,13 +755,15 @@ int __init init_arch_irq(void)
|
||||||
int irq;
|
int irq;
|
||||||
unsigned long ilat = 0;
|
unsigned long ilat = 0;
|
||||||
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */
|
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */
|
||||||
#ifdef CONFIG_BF54x
|
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
|
||||||
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
|
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
|
||||||
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
|
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
|
||||||
bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
|
|
||||||
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
|
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
|
||||||
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
|
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
|
||||||
|
#ifdef CONFIG_BF54x
|
||||||
|
bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
|
||||||
bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
|
bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
|
||||||
|
#endif
|
||||||
#else
|
#else
|
||||||
bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
|
bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
|
||||||
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
|
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
|
||||||
|
|
@ -787,7 +794,7 @@ int __init init_arch_irq(void)
|
||||||
|
|
||||||
switch (irq) {
|
switch (irq) {
|
||||||
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
|
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
|
||||||
#ifndef CONFIG_BF54x
|
#if defined(CONFIG_BF53x)
|
||||||
case IRQ_PROG_INTA:
|
case IRQ_PROG_INTA:
|
||||||
set_irq_chained_handler(irq,
|
set_irq_chained_handler(irq,
|
||||||
bfin_demux_gpio_irq);
|
bfin_demux_gpio_irq);
|
||||||
|
|
@ -798,7 +805,7 @@ int __init init_arch_irq(void)
|
||||||
bfin_demux_gpio_irq);
|
bfin_demux_gpio_irq);
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#else
|
#elif defined(CONFIG_BF54x)
|
||||||
case IRQ_PINT0:
|
case IRQ_PINT0:
|
||||||
set_irq_chained_handler(irq,
|
set_irq_chained_handler(irq,
|
||||||
bfin_demux_gpio_irq);
|
bfin_demux_gpio_irq);
|
||||||
|
|
@ -815,7 +822,20 @@ int __init init_arch_irq(void)
|
||||||
set_irq_chained_handler(irq,
|
set_irq_chained_handler(irq,
|
||||||
bfin_demux_gpio_irq);
|
bfin_demux_gpio_irq);
|
||||||
break;
|
break;
|
||||||
#endif /*CONFIG_BF54x */
|
#elif defined(CONFIG_BF52x)
|
||||||
|
case IRQ_PORTF_INTA:
|
||||||
|
set_irq_chained_handler(irq,
|
||||||
|
bfin_demux_gpio_irq);
|
||||||
|
break;
|
||||||
|
case IRQ_PORTG_INTA:
|
||||||
|
set_irq_chained_handler(irq,
|
||||||
|
bfin_demux_gpio_irq);
|
||||||
|
break;
|
||||||
|
case IRQ_PORTH_INTA:
|
||||||
|
set_irq_chained_handler(irq,
|
||||||
|
bfin_demux_gpio_irq);
|
||||||
|
break;
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
default:
|
default:
|
||||||
set_irq_handler(irq, handle_simple_irq);
|
set_irq_handler(irq, handle_simple_irq);
|
||||||
|
|
@ -880,14 +900,15 @@ void do_irq(int vec, struct pt_regs *fp)
|
||||||
} else {
|
} else {
|
||||||
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
|
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
|
||||||
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
|
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
|
||||||
#ifdef CONFIG_BF54x
|
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
|
||||||
unsigned long sic_status[3];
|
unsigned long sic_status[3];
|
||||||
|
|
||||||
SSYNC();
|
SSYNC();
|
||||||
sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
|
sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
|
||||||
sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
|
sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
|
||||||
|
#ifdef CONFIG_BF54x
|
||||||
sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
|
sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
|
||||||
|
#endif
|
||||||
for (;; ivg++) {
|
for (;; ivg++) {
|
||||||
if (ivg >= ivg_stop) {
|
if (ivg >= ivg_stop) {
|
||||||
atomic_inc(&num_spurious);
|
atomic_inc(&num_spurious);
|
||||||
|
|
|
||||||
|
|
@ -16,7 +16,7 @@
|
||||||
/*
|
/*
|
||||||
* BF537: 8 timers:
|
* BF537: 8 timers:
|
||||||
*/
|
*/
|
||||||
#if defined(CONFIG_BF537)
|
#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
|
||||||
# define MAX_BLACKFIN_GPTIMERS 8
|
# define MAX_BLACKFIN_GPTIMERS 8
|
||||||
# define TIMER0_GROUP_REG TIMER_ENABLE
|
# define TIMER0_GROUP_REG TIMER_ENABLE
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -29,6 +29,7 @@
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Number BF537/6/4 BF561 BF533/2/1
|
* Number BF537/6/4 BF561 BF533/2/1
|
||||||
|
* BF527/5/2
|
||||||
*
|
*
|
||||||
* GPIO_0 PF0 PF0 PF0
|
* GPIO_0 PF0 PF0 PF0
|
||||||
* GPIO_1 PF1 PF1 PF1
|
* GPIO_1 PF1 PF1 PF1
|
||||||
|
|
@ -164,7 +165,7 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef BF537_FAMILY
|
#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
|
||||||
#define MAX_BLACKFIN_GPIOS 48
|
#define MAX_BLACKFIN_GPIOS 48
|
||||||
|
|
||||||
#define GPIO_PF0 0
|
#define GPIO_PF0 0
|
||||||
|
|
|
||||||
|
|
@ -38,4 +38,12 @@
|
||||||
|
|
||||||
/* Anomalies that don't exist on this proc */
|
/* Anomalies that don't exist on this proc */
|
||||||
#define ANOMALY_05000323 (0)
|
#define ANOMALY_05000323 (0)
|
||||||
|
#define ANOMALY_05000244 (0)
|
||||||
|
#define ANOMALY_05000198 (0)
|
||||||
|
#define ANOMALY_05000125 (0)
|
||||||
|
#define ANOMALY_05000158 (0)
|
||||||
|
#define ANOMALY_05000273 (0)
|
||||||
|
#define ANOMALY_05000263 (0)
|
||||||
|
#define ANOMALY_05000311 (0)
|
||||||
|
#define ANOMALY_05000230 (0)
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,127 @@
|
||||||
|
/*
|
||||||
|
* File: include/asm-blackfin/mach-bf527/bf527.h
|
||||||
|
* Based on: include/asm-blackfin/mach-bf537/bf537.h
|
||||||
|
* Author: Michael Hennerich (michael.hennerich@analog.com)
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description: SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF527
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
* Copyright 2004-2007 Analog Devices Inc.
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, see the file COPYING, or write
|
||||||
|
* to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __MACH_BF527_H__
|
||||||
|
#define __MACH_BF527_H__
|
||||||
|
|
||||||
|
#define SUPPORTED_REVID 2
|
||||||
|
|
||||||
|
#define OFFSET_(x) ((x) & 0x0000FFFF)
|
||||||
|
|
||||||
|
/*some misc defines*/
|
||||||
|
#define IMASK_IVG15 0x8000
|
||||||
|
#define IMASK_IVG14 0x4000
|
||||||
|
#define IMASK_IVG13 0x2000
|
||||||
|
#define IMASK_IVG12 0x1000
|
||||||
|
|
||||||
|
#define IMASK_IVG11 0x0800
|
||||||
|
#define IMASK_IVG10 0x0400
|
||||||
|
#define IMASK_IVG9 0x0200
|
||||||
|
#define IMASK_IVG8 0x0100
|
||||||
|
|
||||||
|
#define IMASK_IVG7 0x0080
|
||||||
|
#define IMASK_IVGTMR 0x0040
|
||||||
|
#define IMASK_IVGHW 0x0020
|
||||||
|
|
||||||
|
/***************************/
|
||||||
|
|
||||||
|
#define BFIN_DSUBBANKS 4
|
||||||
|
#define BFIN_DWAYS 2
|
||||||
|
#define BFIN_DLINES 64
|
||||||
|
#define BFIN_ISUBBANKS 4
|
||||||
|
#define BFIN_IWAYS 4
|
||||||
|
#define BFIN_ILINES 32
|
||||||
|
|
||||||
|
#define WAY0_L 0x1
|
||||||
|
#define WAY1_L 0x2
|
||||||
|
#define WAY01_L 0x3
|
||||||
|
#define WAY2_L 0x4
|
||||||
|
#define WAY02_L 0x5
|
||||||
|
#define WAY12_L 0x6
|
||||||
|
#define WAY012_L 0x7
|
||||||
|
|
||||||
|
#define WAY3_L 0x8
|
||||||
|
#define WAY03_L 0x9
|
||||||
|
#define WAY13_L 0xA
|
||||||
|
#define WAY013_L 0xB
|
||||||
|
|
||||||
|
#define WAY32_L 0xC
|
||||||
|
#define WAY320_L 0xD
|
||||||
|
#define WAY321_L 0xE
|
||||||
|
#define WAYALL_L 0xF
|
||||||
|
|
||||||
|
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
|
||||||
|
|
||||||
|
/********************************* EBIU Settings ************************************/
|
||||||
|
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
|
||||||
|
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
|
||||||
|
|
||||||
|
#ifdef CONFIG_C_AMBEN_ALL
|
||||||
|
#define V_AMBEN AMBEN_ALL
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_C_AMBEN
|
||||||
|
#define V_AMBEN 0x0
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_C_AMBEN_B0
|
||||||
|
#define V_AMBEN AMBEN_B0
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_C_AMBEN_B0_B1
|
||||||
|
#define V_AMBEN AMBEN_B0_B1
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_C_AMBEN_B0_B1_B2
|
||||||
|
#define V_AMBEN AMBEN_B0_B1_B2
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_C_AMCKEN
|
||||||
|
#define V_AMCKEN AMCKEN
|
||||||
|
#else
|
||||||
|
#define V_AMCKEN 0x0
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_C_CDPRIO
|
||||||
|
#define V_CDPRIO 0x100
|
||||||
|
#else
|
||||||
|
#define V_CDPRIO 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
|
||||||
|
|
||||||
|
#ifdef CONFIG_BF527
|
||||||
|
#define CPU "BF527"
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_BF525
|
||||||
|
#define CPU "BF525"
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_BF522
|
||||||
|
#define CPU "BF522"
|
||||||
|
#endif
|
||||||
|
#ifndef CPU
|
||||||
|
#define CPU "UNKNOWN"
|
||||||
|
#define CPUID 0x0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __MACH_BF527_H__ */
|
||||||
|
|
@ -0,0 +1,152 @@
|
||||||
|
#include <linux/serial.h>
|
||||||
|
#include <asm/dma.h>
|
||||||
|
#include <asm/portmux.h>
|
||||||
|
|
||||||
|
#define NR_PORTS 2
|
||||||
|
|
||||||
|
#define OFFSET_THR 0x00 /* Transmit Holding register */
|
||||||
|
#define OFFSET_RBR 0x00 /* Receive Buffer register */
|
||||||
|
#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
|
||||||
|
#define OFFSET_IER 0x04 /* Interrupt Enable Register */
|
||||||
|
#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
|
||||||
|
#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
|
||||||
|
#define OFFSET_LCR 0x0C /* Line Control Register */
|
||||||
|
#define OFFSET_MCR 0x10 /* Modem Control Register */
|
||||||
|
#define OFFSET_LSR 0x14 /* Line Status Register */
|
||||||
|
#define OFFSET_MSR 0x18 /* Modem Status Register */
|
||||||
|
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
|
||||||
|
#define OFFSET_GCTL 0x24 /* Global Control Register */
|
||||||
|
|
||||||
|
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
|
||||||
|
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
|
||||||
|
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
|
||||||
|
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
|
||||||
|
#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
|
||||||
|
#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
|
||||||
|
#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
|
||||||
|
#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
|
||||||
|
|
||||||
|
#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
|
||||||
|
#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
|
||||||
|
#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
|
||||||
|
#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
|
||||||
|
#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
|
||||||
|
#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
|
||||||
|
|
||||||
|
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
|
||||||
|
# define CONFIG_SERIAL_BFIN_CTSRTS
|
||||||
|
|
||||||
|
# ifndef CONFIG_UART0_CTS_PIN
|
||||||
|
# define CONFIG_UART0_CTS_PIN -1
|
||||||
|
# endif
|
||||||
|
|
||||||
|
# ifndef CONFIG_UART0_RTS_PIN
|
||||||
|
# define CONFIG_UART0_RTS_PIN -1
|
||||||
|
# endif
|
||||||
|
|
||||||
|
# ifndef CONFIG_UART1_CTS_PIN
|
||||||
|
# define CONFIG_UART1_CTS_PIN -1
|
||||||
|
# endif
|
||||||
|
|
||||||
|
# ifndef CONFIG_UART1_RTS_PIN
|
||||||
|
# define CONFIG_UART1_RTS_PIN -1
|
||||||
|
# endif
|
||||||
|
#endif
|
||||||
|
/*
|
||||||
|
* The pin configuration is different from schematic
|
||||||
|
*/
|
||||||
|
struct bfin_serial_port {
|
||||||
|
struct uart_port port;
|
||||||
|
unsigned int old_status;
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||||
|
int tx_done;
|
||||||
|
int tx_count;
|
||||||
|
struct circ_buf rx_dma_buf;
|
||||||
|
struct timer_list rx_dma_timer;
|
||||||
|
int rx_dma_nrows;
|
||||||
|
unsigned int tx_dma_channel;
|
||||||
|
unsigned int rx_dma_channel;
|
||||||
|
struct work_struct tx_dma_workqueue;
|
||||||
|
#else
|
||||||
|
struct work_struct cts_workqueue;
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||||
|
int cts_pin;
|
||||||
|
int rts_pin;
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
struct bfin_serial_port bfin_serial_ports[NR_PORTS];
|
||||||
|
struct bfin_serial_res {
|
||||||
|
unsigned long uart_base_addr;
|
||||||
|
int uart_irq;
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||||
|
unsigned int uart_tx_dma_channel;
|
||||||
|
unsigned int uart_rx_dma_channel;
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||||
|
int uart_cts_pin;
|
||||||
|
int uart_rts_pin;
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
struct bfin_serial_res bfin_serial_resource[] = {
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||||
|
{
|
||||||
|
0xFFC00400,
|
||||||
|
IRQ_UART0_RX,
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||||
|
CH_UART0_TX,
|
||||||
|
CH_UART0_RX,
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_BFIN_UART0_CTSRTS
|
||||||
|
CONFIG_UART0_CTS_PIN,
|
||||||
|
CONFIG_UART0_RTS_PIN,
|
||||||
|
#endif
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||||||
|
{
|
||||||
|
0xFFC02000,
|
||||||
|
IRQ_UART1_RX,
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_DMA
|
||||||
|
CH_UART1_TX,
|
||||||
|
CH_UART1_RX,
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_BFIN_UART1_CTSRTS
|
||||||
|
CONFIG_UART1_CTS_PIN,
|
||||||
|
CONFIG_UART1_RTS_PIN,
|
||||||
|
#endif
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
int nr_ports = ARRAY_SIZE(bfin_serial_resource);
|
||||||
|
|
||||||
|
#define DRIVER_NAME "bfin-uart"
|
||||||
|
|
||||||
|
static void bfin_serial_hw_init(struct bfin_serial_port *uart)
|
||||||
|
{
|
||||||
|
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||||
|
peripheral_request(P_UART0_TX, DRIVER_NAME);
|
||||||
|
peripheral_request(P_UART0_RX, DRIVER_NAME);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||||||
|
peripheral_request(P_UART1_TX, DRIVER_NAME);
|
||||||
|
peripheral_request(P_UART1_RX, DRIVER_NAME);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
|
||||||
|
if (uart->cts_pin >= 0) {
|
||||||
|
gpio_request(uart->cts_pin, DRIVER_NAME);
|
||||||
|
gpio_direction_input(uart->cts_pin);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (uart->rts_pin >= 0) {
|
||||||
|
gpio_request(uart->rts_pin, DRIVER_NAME);
|
||||||
|
gpio_direction_output(uart->rts_pin);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,78 @@
|
||||||
|
/*
|
||||||
|
* File: include/asm-blackfin/mach-bf527/blackfin.h
|
||||||
|
* Based on:
|
||||||
|
* Author:
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description:
|
||||||
|
*
|
||||||
|
* Rev:
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2, or (at your option)
|
||||||
|
* any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; see the file COPYING.
|
||||||
|
* If not, write to the Free Software Foundation,
|
||||||
|
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _MACH_BLACKFIN_H_
|
||||||
|
#define _MACH_BLACKFIN_H_
|
||||||
|
|
||||||
|
#define BF527_FAMILY
|
||||||
|
|
||||||
|
#include "bf527.h"
|
||||||
|
#include "mem_map.h"
|
||||||
|
#include "defBF522.h"
|
||||||
|
#include "anomaly.h"
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF527)
|
||||||
|
#include "defBF527.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF525)
|
||||||
|
#include "defBF525.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(__ASSEMBLY__)
|
||||||
|
#include "cdefBF522.h"
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF527)
|
||||||
|
#include "cdefBF527.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF525)
|
||||||
|
#include "cdefBF525.h"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* UART_IIR Register */
|
||||||
|
#define STATUS(x) ((x << 1) & 0x06)
|
||||||
|
#define STATUS_P1 0x02
|
||||||
|
#define STATUS_P0 0x01
|
||||||
|
|
||||||
|
/* DPMC*/
|
||||||
|
#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
|
||||||
|
#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
|
||||||
|
#define STOPCK_OFF STOPCK
|
||||||
|
|
||||||
|
/* PLL_DIV Masks */
|
||||||
|
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
|
||||||
|
#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
|
||||||
|
#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
|
||||||
|
#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -45,8 +45,8 @@
|
||||||
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
|
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
|
||||||
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
|
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
|
||||||
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
|
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
|
||||||
#define bfin_read_CHIPID() bfin_read16(CHIPID)
|
#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
||||||
#define bfin_write_CHIPID(val) bfin_write16(CHIPID, val)
|
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
|
||||||
|
|
||||||
|
|
||||||
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
|
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
|
||||||
|
|
@ -59,9 +59,8 @@
|
||||||
#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
|
#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
|
||||||
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
|
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
|
||||||
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
|
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
|
||||||
/* legacy register name (below) provided for backwards code compatibility */
|
#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
|
||||||
#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
|
#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
|
||||||
#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
|
|
||||||
|
|
||||||
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
|
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
|
||||||
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
|
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
|
||||||
|
|
@ -74,15 +73,13 @@
|
||||||
|
|
||||||
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
|
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
|
||||||
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
|
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
|
||||||
/* legacy register name (below) provided for backwards code compatibility */
|
#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
|
||||||
#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
|
#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
|
||||||
#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
|
|
||||||
|
|
||||||
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
|
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
|
||||||
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
|
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
|
||||||
/* legacy register name (below) provided for backwards code compatibility */
|
#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
|
||||||
#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
|
#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
|
||||||
#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
|
|
||||||
|
|
||||||
/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
|
/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -32,12 +32,12 @@
|
||||||
#define _DEF_BF527_H
|
#define _DEF_BF527_H
|
||||||
|
|
||||||
/* Include all Core registers and bit definitions */
|
/* Include all Core registers and bit definitions */
|
||||||
#include <def_LPBlackfin.h>
|
#include <asm/mach-common/def_LPBlackfin.h>
|
||||||
|
|
||||||
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
|
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
|
||||||
|
|
||||||
/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
|
/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
|
||||||
#include <defBF52x_base.h>
|
#include "defBF52x_base.h"
|
||||||
|
|
||||||
/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
|
/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
|
||||||
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
|
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
|
||||||
|
|
|
||||||
|
|
@ -52,13 +52,13 @@
|
||||||
#define SYSCR 0xFFC00104 /* System Configuration Register */
|
#define SYSCR 0xFFC00104 /* System Configuration Register */
|
||||||
#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
|
#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
|
||||||
|
|
||||||
#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
|
#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
|
||||||
#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
|
#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
|
||||||
#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
|
#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
|
||||||
#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
|
#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
|
||||||
#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
|
#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
|
||||||
#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
|
#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
|
||||||
#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
|
#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
|
||||||
|
|
||||||
/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
|
/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
|
||||||
#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
|
#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
|
||||||
|
|
@ -691,6 +691,8 @@
|
||||||
|
|
||||||
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
|
/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
|
||||||
/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
|
/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
|
||||||
|
|
||||||
|
#if 0
|
||||||
#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
|
#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
|
||||||
|
|
||||||
#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
|
#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
|
||||||
|
|
@ -732,6 +734,7 @@
|
||||||
#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
|
#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
|
||||||
#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
|
#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
|
||||||
#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
|
#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
|
||||||
|
#endif
|
||||||
|
|
||||||
/* SIC_IAR0 Macros */
|
/* SIC_IAR0 Macros */
|
||||||
#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
|
#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,60 @@
|
||||||
|
/*
|
||||||
|
* file: include/asm-blackfin/mach-bf527/dma.h
|
||||||
|
* based on: include/asm-blackfin/mach-bf537/dma.h
|
||||||
|
* author: Michael Hennerich (michael.hennerich@analog.com)
|
||||||
|
*
|
||||||
|
* created:
|
||||||
|
* description:
|
||||||
|
* system DMA map
|
||||||
|
* rev:
|
||||||
|
*
|
||||||
|
* modified:
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* bugs: enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* this program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the gnu general public license as published by
|
||||||
|
* the free software foundation; either version 2, or (at your option)
|
||||||
|
* any later version.
|
||||||
|
*
|
||||||
|
* this program is distributed in the hope that it will be useful,
|
||||||
|
* but without any warranty; without even the implied warranty of
|
||||||
|
* merchantability or fitness for a particular purpose. see the
|
||||||
|
* gnu general public license for more details.
|
||||||
|
*
|
||||||
|
* you should have received a copy of the gnu general public license
|
||||||
|
* along with this program; see the file copying.
|
||||||
|
* if not, write to the free software foundation,
|
||||||
|
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _MACH_DMA_H_
|
||||||
|
#define _MACH_DMA_H_
|
||||||
|
|
||||||
|
#define MAX_BLACKFIN_DMA_CHANNEL 16
|
||||||
|
|
||||||
|
#define CH_PPI 0 /* PPI receive/transmit or NFC */
|
||||||
|
#define CH_NFC 0 /* PPI receive/transmit or NFC */
|
||||||
|
#define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */
|
||||||
|
#define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */
|
||||||
|
#define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */
|
||||||
|
#define CH_SPORT0_RX 3 /* SPORT0 receive */
|
||||||
|
#define CH_SPORT0_TX 4 /* SPORT0 transmit */
|
||||||
|
#define CH_SPORT1_RX 5 /* SPORT1 receive */
|
||||||
|
#define CH_SPORT1_TX 6 /* SPORT1 transmit */
|
||||||
|
#define CH_SPI 7 /* SPI transmit/receive */
|
||||||
|
#define CH_UART0_RX 8 /* UART0 receive */
|
||||||
|
#define CH_UART0_TX 9 /* UART0 transmit */
|
||||||
|
#define CH_UART1_RX 10 /* UART1 receive */
|
||||||
|
#define CH_UART1_TX 11 /* UART1 transmit */
|
||||||
|
|
||||||
|
#define CH_MEM_STREAM0_DEST 12 /* TX */
|
||||||
|
#define CH_MEM_STREAM0_SRC 13 /* RX */
|
||||||
|
#define CH_MEM_STREAM1_DEST 14 /* TX */
|
||||||
|
#define CH_MEM_STREAM1_SRC 15 /* RX */
|
||||||
|
|
||||||
|
extern int channel2irq(unsigned int channel);
|
||||||
|
extern struct dma_register *base_addr[];
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,263 @@
|
||||||
|
/*
|
||||||
|
* file: include/asm-blackfin/mach-bf527/irq.h
|
||||||
|
* based on: include/asm-blackfin/mach-bf537/irq.h
|
||||||
|
* author: Michael Hennerich (michael.hennerich@analog.com)
|
||||||
|
*
|
||||||
|
* created:
|
||||||
|
* description:
|
||||||
|
* system mmr register map
|
||||||
|
* rev:
|
||||||
|
*
|
||||||
|
* modified:
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* bugs: enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* this program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the gnu general public license as published by
|
||||||
|
* the free software foundation; either version 2, or (at your option)
|
||||||
|
* any later version.
|
||||||
|
*
|
||||||
|
* this program is distributed in the hope that it will be useful,
|
||||||
|
* but without any warranty; without even the implied warranty of
|
||||||
|
* merchantability or fitness for a particular purpose. see the
|
||||||
|
* gnu general public license for more details.
|
||||||
|
*
|
||||||
|
* you should have received a copy of the gnu general public license
|
||||||
|
* along with this program; see the file copying.
|
||||||
|
* if not, write to the free software foundation,
|
||||||
|
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _BF527_IRQ_H_
|
||||||
|
#define _BF527_IRQ_H_
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Interrupt source definitions
|
||||||
|
Event Source Core Event Name
|
||||||
|
Core Emulation **
|
||||||
|
Events (highest priority) EMU 0
|
||||||
|
Reset RST 1
|
||||||
|
NMI NMI 2
|
||||||
|
Exception EVX 3
|
||||||
|
Reserved -- 4
|
||||||
|
Hardware Error IVHW 5
|
||||||
|
Core Timer IVTMR 6 *
|
||||||
|
|
||||||
|
.....
|
||||||
|
|
||||||
|
Software Interrupt 1 IVG14 31
|
||||||
|
Software Interrupt 2 --
|
||||||
|
(lowest priority) IVG15 32 *
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define NR_PERI_INTS (2 * 32)
|
||||||
|
|
||||||
|
/* The ABSTRACT IRQ definitions */
|
||||||
|
/** the first seven of the following are fixed, the rest you change if you need to **/
|
||||||
|
#define IRQ_EMU 0 /* Emulation */
|
||||||
|
#define IRQ_RST 1 /* reset */
|
||||||
|
#define IRQ_NMI 2 /* Non Maskable */
|
||||||
|
#define IRQ_EVX 3 /* Exception */
|
||||||
|
#define IRQ_UNUSED 4 /* - unused interrupt */
|
||||||
|
#define IRQ_HWERR 5 /* Hardware Error */
|
||||||
|
#define IRQ_CORETMR 6 /* Core timer */
|
||||||
|
|
||||||
|
#define BFIN_IRQ(x) ((x) + 7)
|
||||||
|
|
||||||
|
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
|
||||||
|
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
|
||||||
|
#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
|
||||||
|
#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
|
||||||
|
#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
|
||||||
|
#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
|
||||||
|
#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
|
||||||
|
#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
|
||||||
|
#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
|
||||||
|
#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
|
||||||
|
#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
|
||||||
|
#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
|
||||||
|
#define IRQ_RTC BFIN_IRQ(14) /* RTC */
|
||||||
|
#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
|
||||||
|
#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
|
||||||
|
#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
|
||||||
|
#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
|
||||||
|
#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
|
||||||
|
#define IRQ_TWI BFIN_IRQ(20) /* TWI */
|
||||||
|
#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
|
||||||
|
#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
|
||||||
|
#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
|
||||||
|
#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
|
||||||
|
#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
|
||||||
|
#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
|
||||||
|
#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
|
||||||
|
#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
|
||||||
|
#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
|
||||||
|
#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
|
||||||
|
#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
|
||||||
|
#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
|
||||||
|
#define IRQ_TMR0 BFIN_IRQ(32) /* Timer 0 */
|
||||||
|
#define IRQ_TMR1 BFIN_IRQ(33) /* Timer 1 */
|
||||||
|
#define IRQ_TMR2 BFIN_IRQ(34) /* Timer 2 */
|
||||||
|
#define IRQ_TMR3 BFIN_IRQ(35) /* Timer 3 */
|
||||||
|
#define IRQ_TMR4 BFIN_IRQ(36) /* Timer 4 */
|
||||||
|
#define IRQ_TMR5 BFIN_IRQ(37) /* Timer 5 */
|
||||||
|
#define IRQ_TMR6 BFIN_IRQ(38) /* Timer 6 */
|
||||||
|
#define IRQ_TMR7 BFIN_IRQ(39) /* Timer 7 */
|
||||||
|
#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
|
||||||
|
#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
|
||||||
|
#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
|
||||||
|
#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
|
||||||
|
#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
|
||||||
|
#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
|
||||||
|
#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
|
||||||
|
#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */
|
||||||
|
#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */
|
||||||
|
#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */
|
||||||
|
#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */
|
||||||
|
#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */
|
||||||
|
#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */
|
||||||
|
#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */
|
||||||
|
#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
|
||||||
|
#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
|
||||||
|
|
||||||
|
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
|
||||||
|
|
||||||
|
#define IRQ_PF0 71
|
||||||
|
#define IRQ_PF1 72
|
||||||
|
#define IRQ_PF2 73
|
||||||
|
#define IRQ_PF3 74
|
||||||
|
#define IRQ_PF4 75
|
||||||
|
#define IRQ_PF5 76
|
||||||
|
#define IRQ_PF6 77
|
||||||
|
#define IRQ_PF7 78
|
||||||
|
#define IRQ_PF8 79
|
||||||
|
#define IRQ_PF9 80
|
||||||
|
#define IRQ_PF10 81
|
||||||
|
#define IRQ_PF11 82
|
||||||
|
#define IRQ_PF12 83
|
||||||
|
#define IRQ_PF13 84
|
||||||
|
#define IRQ_PF14 85
|
||||||
|
#define IRQ_PF15 86
|
||||||
|
|
||||||
|
#define IRQ_PG0 87
|
||||||
|
#define IRQ_PG1 88
|
||||||
|
#define IRQ_PG2 89
|
||||||
|
#define IRQ_PG3 90
|
||||||
|
#define IRQ_PG4 91
|
||||||
|
#define IRQ_PG5 92
|
||||||
|
#define IRQ_PG6 93
|
||||||
|
#define IRQ_PG7 94
|
||||||
|
#define IRQ_PG8 95
|
||||||
|
#define IRQ_PG9 96
|
||||||
|
#define IRQ_PG10 97
|
||||||
|
#define IRQ_PG11 98
|
||||||
|
#define IRQ_PG12 99
|
||||||
|
#define IRQ_PG13 100
|
||||||
|
#define IRQ_PG14 101
|
||||||
|
#define IRQ_PG15 102
|
||||||
|
|
||||||
|
#define IRQ_PH0 103
|
||||||
|
#define IRQ_PH1 104
|
||||||
|
#define IRQ_PH2 105
|
||||||
|
#define IRQ_PH3 106
|
||||||
|
#define IRQ_PH4 107
|
||||||
|
#define IRQ_PH5 108
|
||||||
|
#define IRQ_PH6 109
|
||||||
|
#define IRQ_PH7 110
|
||||||
|
#define IRQ_PH8 111
|
||||||
|
#define IRQ_PH9 112
|
||||||
|
#define IRQ_PH10 113
|
||||||
|
#define IRQ_PH11 114
|
||||||
|
#define IRQ_PH12 115
|
||||||
|
#define IRQ_PH13 116
|
||||||
|
#define IRQ_PH14 117
|
||||||
|
#define IRQ_PH15 118
|
||||||
|
|
||||||
|
#define GPIO_IRQ_BASE IRQ_PF0
|
||||||
|
|
||||||
|
#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
|
||||||
|
#define NR_IRQS (IRQ_PH15+1)
|
||||||
|
#else
|
||||||
|
#define NR_IRQS (SYS_IRQS+1)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define IVG7 7
|
||||||
|
#define IVG8 8
|
||||||
|
#define IVG9 9
|
||||||
|
#define IVG10 10
|
||||||
|
#define IVG11 11
|
||||||
|
#define IVG12 12
|
||||||
|
#define IVG13 13
|
||||||
|
#define IVG14 14
|
||||||
|
#define IVG15 15
|
||||||
|
|
||||||
|
/* IAR0 BIT FIELDS */
|
||||||
|
#define IRQ_PLL_WAKEUP_POS 0
|
||||||
|
#define IRQ_DMA0_ERROR_POS 4
|
||||||
|
#define IRQ_DMAR0_BLK_POS 8
|
||||||
|
#define IRQ_DMAR1_BLK_POS 12
|
||||||
|
#define IRQ_DMAR0_OVR_POS 16
|
||||||
|
#define IRQ_DMAR1_OVR_POS 20
|
||||||
|
#define IRQ_PPI_ERROR_POS 24
|
||||||
|
#define IRQ_MAC_ERROR_POS 28
|
||||||
|
|
||||||
|
/* IAR1 BIT FIELDS */
|
||||||
|
#define IRQ_SPORT0_ERROR_POS 0
|
||||||
|
#define IRQ_SPORT1_ERROR_POS 4
|
||||||
|
#define IRQ_UART0_ERROR_POS 16
|
||||||
|
#define IRQ_UART1_ERROR_POS 20
|
||||||
|
#define IRQ_RTC_POS 24
|
||||||
|
#define IRQ_PPI_POS 28
|
||||||
|
|
||||||
|
/* IAR2 BIT FIELDS */
|
||||||
|
#define IRQ_SPORT0_RX_POS 0
|
||||||
|
#define IRQ_SPORT0_TX_POS 4
|
||||||
|
#define IRQ_SPORT1_RX_POS 8
|
||||||
|
#define IRQ_SPORT1_TX_POS 12
|
||||||
|
#define IRQ_TWI_POS 16
|
||||||
|
#define IRQ_SPI_POS 20
|
||||||
|
#define IRQ_UART0_RX_POS 24
|
||||||
|
#define IRQ_UART0_TX_POS 28
|
||||||
|
|
||||||
|
/* IAR3 BIT FIELDS */
|
||||||
|
#define IRQ_UART1_RX_POS 0
|
||||||
|
#define IRQ_UART1_TX_POS 4
|
||||||
|
#define IRQ_OPTSEC_POS 8
|
||||||
|
#define IRQ_CNT_POS 12
|
||||||
|
#define IRQ_MAC_RX_POS 16
|
||||||
|
#define IRQ_PORTH_INTA_POS 20
|
||||||
|
#define IRQ_MAC_TX_POS 24
|
||||||
|
#define IRQ_PORTH_INTB_POS 28
|
||||||
|
|
||||||
|
/* IAR4 BIT FIELDS */
|
||||||
|
#define IRQ_TMR0_POS 0
|
||||||
|
#define IRQ_TMR1_POS 4
|
||||||
|
#define IRQ_TMR2_POS 8
|
||||||
|
#define IRQ_TMR3_POS 12
|
||||||
|
#define IRQ_TMR4_POS 16
|
||||||
|
#define IRQ_TMR5_POS 20
|
||||||
|
#define IRQ_TMR6_POS 24
|
||||||
|
#define IRQ_TMR7_POS 28
|
||||||
|
|
||||||
|
/* IAR5 BIT FIELDS */
|
||||||
|
#define IRQ_PORTG_INTA_POS 0
|
||||||
|
#define IRQ_PORTG_INTB_POS 4
|
||||||
|
#define IRQ_MEM_DMA0_POS 8
|
||||||
|
#define IRQ_MEM_DMA1_POS 12
|
||||||
|
#define IRQ_WATCH_POS 16
|
||||||
|
#define IRQ_PORTF_INTA_POS 20
|
||||||
|
#define IRQ_PORTF_INTB_POS 24
|
||||||
|
#define IRQ_SPI_ERROR_POS 28
|
||||||
|
|
||||||
|
/* IAR6 BIT FIELDS */
|
||||||
|
#define IRQ_NFC_ERROR_POS 0
|
||||||
|
#define IRQ_HDMA_ERROR_POS 4
|
||||||
|
#define IRQ_HDMA_POS 8
|
||||||
|
#define IRQ_USB_EINT_POS 12
|
||||||
|
#define IRQ_USB_INT0_POS 16
|
||||||
|
#define IRQ_USB_INT1_POS 20
|
||||||
|
#define IRQ_USB_INT2_POS 24
|
||||||
|
#define IRQ_USB_DMA_POS 28
|
||||||
|
|
||||||
|
#endif /* _BF527_IRQ_H_ */
|
||||||
|
|
@ -0,0 +1,337 @@
|
||||||
|
/*
|
||||||
|
* File: include/asm-blackfin/mach-bf527/mem_init.h
|
||||||
|
* Based on:
|
||||||
|
* Author:
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description:
|
||||||
|
*
|
||||||
|
* Rev:
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
* Copyright 2004-2007 Analog Devices Inc.
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2, or (at your option)
|
||||||
|
* any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; see the file COPYING.
|
||||||
|
* If not, write to the Free Software Foundation,
|
||||||
|
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
|
||||||
|
#if (CONFIG_SCLK_HZ > 119402985)
|
||||||
|
#define SDRAM_tRP TRP_2
|
||||||
|
#define SDRAM_tRP_num 2
|
||||||
|
#define SDRAM_tRAS TRAS_7
|
||||||
|
#define SDRAM_tRAS_num 7
|
||||||
|
#define SDRAM_tRCD TRCD_2
|
||||||
|
#define SDRAM_tWR TWR_2
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
|
||||||
|
#define SDRAM_tRP TRP_2
|
||||||
|
#define SDRAM_tRP_num 2
|
||||||
|
#define SDRAM_tRAS TRAS_6
|
||||||
|
#define SDRAM_tRAS_num 6
|
||||||
|
#define SDRAM_tRCD TRCD_2
|
||||||
|
#define SDRAM_tWR TWR_2
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
|
||||||
|
#define SDRAM_tRP TRP_2
|
||||||
|
#define SDRAM_tRP_num 2
|
||||||
|
#define SDRAM_tRAS TRAS_5
|
||||||
|
#define SDRAM_tRAS_num 5
|
||||||
|
#define SDRAM_tRCD TRCD_2
|
||||||
|
#define SDRAM_tWR TWR_2
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
|
||||||
|
#define SDRAM_tRP TRP_2
|
||||||
|
#define SDRAM_tRP_num 2
|
||||||
|
#define SDRAM_tRAS TRAS_4
|
||||||
|
#define SDRAM_tRAS_num 4
|
||||||
|
#define SDRAM_tRCD TRCD_2
|
||||||
|
#define SDRAM_tWR TWR_2
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
|
||||||
|
#define SDRAM_tRP TRP_2
|
||||||
|
#define SDRAM_tRP_num 2
|
||||||
|
#define SDRAM_tRAS TRAS_3
|
||||||
|
#define SDRAM_tRAS_num 3
|
||||||
|
#define SDRAM_tRCD TRCD_2
|
||||||
|
#define SDRAM_tWR TWR_2
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
|
||||||
|
#define SDRAM_tRP TRP_1
|
||||||
|
#define SDRAM_tRP_num 1
|
||||||
|
#define SDRAM_tRAS TRAS_4
|
||||||
|
#define SDRAM_tRAS_num 3
|
||||||
|
#define SDRAM_tRCD TRCD_1
|
||||||
|
#define SDRAM_tWR TWR_2
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
|
||||||
|
#define SDRAM_tRP TRP_1
|
||||||
|
#define SDRAM_tRP_num 1
|
||||||
|
#define SDRAM_tRAS TRAS_3
|
||||||
|
#define SDRAM_tRAS_num 3
|
||||||
|
#define SDRAM_tRCD TRCD_1
|
||||||
|
#define SDRAM_tWR TWR_2
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
|
||||||
|
#define SDRAM_tRP TRP_1
|
||||||
|
#define SDRAM_tRP_num 1
|
||||||
|
#define SDRAM_tRAS TRAS_2
|
||||||
|
#define SDRAM_tRAS_num 2
|
||||||
|
#define SDRAM_tRCD TRCD_1
|
||||||
|
#define SDRAM_tWR TWR_2
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_SCLK_HZ <= 29850746)
|
||||||
|
#define SDRAM_tRP TRP_1
|
||||||
|
#define SDRAM_tRP_num 1
|
||||||
|
#define SDRAM_tRAS TRAS_1
|
||||||
|
#define SDRAM_tRAS_num 1
|
||||||
|
#define SDRAM_tRCD TRCD_1
|
||||||
|
#define SDRAM_tWR TWR_2
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_MT48LC16M16A2TG_75)
|
||||||
|
/*SDRAM INFORMATION: */
|
||||||
|
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||||
|
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||||
|
#define SDRAM_CL CL_3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_MT48LC16M8A2TG_75)
|
||||||
|
/*SDRAM INFORMATION: */
|
||||||
|
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||||
|
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
|
||||||
|
#define SDRAM_CL CL_3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_MT48LC32M8A2_75)
|
||||||
|
/*SDRAM INFORMATION: */
|
||||||
|
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||||
|
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||||
|
#define SDRAM_CL CL_3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
|
||||||
|
/*SDRAM INFORMATION: */
|
||||||
|
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||||
|
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||||
|
#define SDRAM_CL CL_3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_GENERIC_BOARD)
|
||||||
|
/*SDRAM INFORMATION: Modify this for your board */
|
||||||
|
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||||
|
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||||
|
#define SDRAM_CL CL_3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_MT48LC32M16A2TG_75)
|
||||||
|
/*SDRAM INFORMATION: */
|
||||||
|
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||||
|
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||||
|
#define SDRAM_CL CL_3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_SIZE == 128)
|
||||||
|
#define SDRAM_SIZE EBSZ_128
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_MEM_SIZE == 64)
|
||||||
|
#define SDRAM_SIZE EBSZ_64
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_MEM_SIZE == 32)
|
||||||
|
#define SDRAM_SIZE EBSZ_32
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_MEM_SIZE == 16)
|
||||||
|
#define SDRAM_SIZE EBSZ_16
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_MEM_ADD_WIDTH == 11)
|
||||||
|
#define SDRAM_WIDTH EBCAW_11
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_MEM_ADD_WIDTH == 10)
|
||||||
|
#define SDRAM_WIDTH EBCAW_10
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_MEM_ADD_WIDTH == 9)
|
||||||
|
#define SDRAM_WIDTH EBCAW_9
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_MEM_ADD_WIDTH == 8)
|
||||||
|
#define SDRAM_WIDTH EBCAW_8
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
|
||||||
|
|
||||||
|
/* Equation from section 17 (p17-46) of BF533 HRM */
|
||||||
|
#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
|
||||||
|
|
||||||
|
/* Enable SCLK Out */
|
||||||
|
#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
|
||||||
|
|
||||||
|
#if defined CONFIG_CLKIN_HALF
|
||||||
|
#define CLKIN_HALF 1
|
||||||
|
#else
|
||||||
|
#define CLKIN_HALF 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined CONFIG_PLL_BYPASS
|
||||||
|
#define PLL_BYPASS 1
|
||||||
|
#else
|
||||||
|
#define PLL_BYPASS 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/***************************************Currently Not Being Used *********************************/
|
||||||
|
#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
|
||||||
|
#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
|
||||||
|
#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
|
||||||
|
#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
|
||||||
|
#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
|
||||||
|
|
||||||
|
#if (flash_EBIU_AMBCTL_TT > 3)
|
||||||
|
#define flash_EBIU_AMBCTL0_TT B0TT_4
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_TT == 3)
|
||||||
|
#define flash_EBIU_AMBCTL0_TT B0TT_3
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_TT == 2)
|
||||||
|
#define flash_EBIU_AMBCTL0_TT B0TT_2
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_TT < 2)
|
||||||
|
#define flash_EBIU_AMBCTL0_TT B0TT_1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (flash_EBIU_AMBCTL_ST > 3)
|
||||||
|
#define flash_EBIU_AMBCTL0_ST B0ST_4
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_ST == 3)
|
||||||
|
#define flash_EBIU_AMBCTL0_ST B0ST_3
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_ST == 2)
|
||||||
|
#define flash_EBIU_AMBCTL0_ST B0ST_2
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_ST < 2)
|
||||||
|
#define flash_EBIU_AMBCTL0_ST B0ST_1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (flash_EBIU_AMBCTL_HT > 2)
|
||||||
|
#define flash_EBIU_AMBCTL0_HT B0HT_3
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_HT == 2)
|
||||||
|
#define flash_EBIU_AMBCTL0_HT B0HT_2
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_HT == 1)
|
||||||
|
#define flash_EBIU_AMBCTL0_HT B0HT_1
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
|
||||||
|
#define flash_EBIU_AMBCTL0_HT B0HT_0
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
|
||||||
|
#define flash_EBIU_AMBCTL0_HT B0HT_1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT > 14)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_15
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 14)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_14
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 13)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_13
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 12)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_12
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 11)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_11
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 10)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_10
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 9)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_9
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 8)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_8
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 7)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_7
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 6)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_6
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 5)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_5
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 4)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_4
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 3)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_3
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 2)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_2
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_WAT == 1)
|
||||||
|
#define flash_EBIU_AMBCTL0_WAT B0WAT_1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT > 14)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_15
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 14)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_14
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 13)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_13
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 12)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_12
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 11)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_11
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 10)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_10
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 9)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_9
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 8)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_8
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 7)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_7
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 6)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_6
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 5)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_5
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 4)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_4
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 3)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_3
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 2)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_2
|
||||||
|
#endif
|
||||||
|
#if (flash_EBIU_AMBCTL_RAT == 1)
|
||||||
|
#define flash_EBIU_AMBCTL0_RAT B0RAT_1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define flash_EBIU_AMBCTL0 \
|
||||||
|
(flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
|
||||||
|
flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
|
||||||
|
|
@ -0,0 +1,98 @@
|
||||||
|
/*
|
||||||
|
* file: include/asm-blackfin/mach-bf527/mem_map.h
|
||||||
|
* based on: include/asm-blackfin/mach-bf537/mem_map.h
|
||||||
|
* author: Michael Hennerich (michael.hennerich@analog.com)
|
||||||
|
*
|
||||||
|
* created:
|
||||||
|
* description:
|
||||||
|
* Memory MAP Common header file for blackfin BF527/5/2 of processors.
|
||||||
|
* rev:
|
||||||
|
*
|
||||||
|
* modified:
|
||||||
|
*
|
||||||
|
* bugs: enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* this program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the gnu general public license as published by
|
||||||
|
* the free software foundation; either version 2, or (at your option)
|
||||||
|
* any later version.
|
||||||
|
*
|
||||||
|
* this program is distributed in the hope that it will be useful,
|
||||||
|
* but without any warranty; without even the implied warranty of
|
||||||
|
* merchantability or fitness for a particular purpose. see the
|
||||||
|
* gnu general public license for more details.
|
||||||
|
*
|
||||||
|
* you should have received a copy of the gnu general public license
|
||||||
|
* along with this program; see the file copying.
|
||||||
|
* if not, write to the free software foundation,
|
||||||
|
* 59 temple place - suite 330, boston, ma 02111-1307, usa.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _MEM_MAP_527_H_
|
||||||
|
#define _MEM_MAP_527_H_
|
||||||
|
|
||||||
|
#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
|
||||||
|
#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
|
||||||
|
|
||||||
|
/* Async Memory Banks */
|
||||||
|
#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
|
||||||
|
#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
|
||||||
|
#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
|
||||||
|
#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
|
||||||
|
#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
|
||||||
|
#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
|
||||||
|
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
|
||||||
|
#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
|
||||||
|
|
||||||
|
/* Boot ROM Memory */
|
||||||
|
|
||||||
|
#define BOOT_ROM_START 0xEF000000
|
||||||
|
|
||||||
|
/* Level 1 Memory */
|
||||||
|
|
||||||
|
/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
|
||||||
|
|
||||||
|
#ifdef CONFIG_BFIN_ICACHE
|
||||||
|
#define BFIN_ICACHESIZE (16*1024)
|
||||||
|
#else
|
||||||
|
#define BFIN_ICACHESIZE (0*1024)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define L1_CODE_START 0xFFA00000
|
||||||
|
#define L1_DATA_A_START 0xFF800000
|
||||||
|
#define L1_DATA_B_START 0xFF900000
|
||||||
|
|
||||||
|
#define L1_CODE_LENGTH 0xC000
|
||||||
|
|
||||||
|
#ifdef CONFIG_BFIN_DCACHE
|
||||||
|
|
||||||
|
#ifdef CONFIG_BFIN_DCACHE_BANKA
|
||||||
|
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
|
||||||
|
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||||
|
#define L1_DATA_B_LENGTH 0x8000
|
||||||
|
#define BFIN_DCACHESIZE (16*1024)
|
||||||
|
#define BFIN_DSUPBANKS 1
|
||||||
|
#else
|
||||||
|
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
|
||||||
|
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
|
||||||
|
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
|
||||||
|
#define BFIN_DCACHESIZE (32*1024)
|
||||||
|
#define BFIN_DSUPBANKS 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else
|
||||||
|
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
|
||||||
|
#define L1_DATA_A_LENGTH 0x8000
|
||||||
|
#define L1_DATA_B_LENGTH 0x8000
|
||||||
|
#define BFIN_DCACHESIZE (0*1024)
|
||||||
|
#define BFIN_DSUPBANKS 0
|
||||||
|
#endif /*CONFIG_BFIN_DCACHE */
|
||||||
|
|
||||||
|
/* Scratch Pad Memory */
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
|
||||||
|
#define L1_SCRATCH_START 0xFFB00000
|
||||||
|
#define L1_SCRATCH_LENGTH 0x1000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _MEM_MAP_527_H_ */
|
||||||
|
|
@ -0,0 +1,205 @@
|
||||||
|
#ifndef _MACH_PORTMUX_H_
|
||||||
|
#define _MACH_PORTMUX_H_
|
||||||
|
|
||||||
|
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF527_SPORT0_PORTF)
|
||||||
|
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
|
||||||
|
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
|
||||||
|
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
|
||||||
|
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
|
||||||
|
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
|
||||||
|
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
|
||||||
|
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
|
||||||
|
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
|
||||||
|
#elif defined(CONFIG_BF527_SPORT0_PORTG)
|
||||||
|
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
|
||||||
|
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
|
||||||
|
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
|
||||||
|
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
|
||||||
|
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
|
||||||
|
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
|
||||||
|
#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
|
||||||
|
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
|
||||||
|
#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
|
||||||
|
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
|
||||||
|
#endif
|
||||||
|
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
|
||||||
|
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
|
||||||
|
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
|
||||||
|
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
|
||||||
|
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
|
||||||
|
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
|
||||||
|
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
|
||||||
|
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
|
||||||
|
|
||||||
|
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
|
||||||
|
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
|
||||||
|
|
||||||
|
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
|
||||||
|
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF527_UART1_PORTF)
|
||||||
|
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
|
||||||
|
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
|
||||||
|
#elif defined(CONFIG_BF527_UART1_PORTG)
|
||||||
|
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
|
||||||
|
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define P_HWAIT (P_DONTCARE)
|
||||||
|
|
||||||
|
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
|
||||||
|
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
|
||||||
|
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
|
||||||
|
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
|
||||||
|
#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
|
||||||
|
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
|
||||||
|
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
|
||||||
|
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
|
||||||
|
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
|
||||||
|
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
|
||||||
|
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
|
||||||
|
/* #define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
|
||||||
|
#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
|
||||||
|
#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
|
||||||
|
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
|
||||||
|
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
|
||||||
|
#define P_MDC (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
|
||||||
|
#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
|
||||||
|
#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
|
||||||
|
|
||||||
|
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
|
||||||
|
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
|
||||||
|
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
|
||||||
|
|
||||||
|
#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
|
||||||
|
#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
|
||||||
|
#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
|
||||||
|
#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
|
||||||
|
#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF527_NAND_D_PORTF)
|
||||||
|
#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
|
||||||
|
#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
|
||||||
|
#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
|
||||||
|
#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
|
||||||
|
#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
|
||||||
|
#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
|
||||||
|
#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
|
||||||
|
#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
|
||||||
|
#elif defined(CONFIG_BF527_NAND_D_PORTH)
|
||||||
|
#define P_NAND_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
|
||||||
|
#define P_NAND_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
|
||||||
|
#define P_NAND_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
|
||||||
|
#define P_NAND_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
|
||||||
|
#define P_NAND_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
|
||||||
|
#define P_NAND_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
|
||||||
|
#define P_NAND_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
|
||||||
|
#define P_NAND_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
|
||||||
|
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
|
||||||
|
#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
|
||||||
|
#define P_NAND_WE (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
|
||||||
|
#define P_NAND_RE (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
|
||||||
|
#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
|
||||||
|
#define P_NAND_CLE (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
|
||||||
|
#define P_NAND_ALE (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
|
||||||
|
|
||||||
|
#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
|
||||||
|
#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
|
||||||
|
|
||||||
|
#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
|
||||||
|
#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
|
||||||
|
#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
|
||||||
|
#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
|
||||||
|
#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
|
||||||
|
#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
|
||||||
|
#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
|
||||||
|
#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
|
||||||
|
#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
|
||||||
|
#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
|
||||||
|
#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
|
||||||
|
#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
|
||||||
|
#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
|
||||||
|
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
|
||||||
|
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
|
||||||
|
#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
|
||||||
|
#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
|
||||||
|
#define P_MDIO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
|
||||||
|
|
||||||
|
#define P_TWI0_SCL (P_DONTCARE)
|
||||||
|
#define P_TWI0_SDA (P_DONTCARE)
|
||||||
|
#define P_PPI0_FS1 (P_DONTCARE)
|
||||||
|
#define P_TMR0 (P_DONTCARE)
|
||||||
|
#define P_TMRCLK (P_DONTCARE)
|
||||||
|
#define P_PPI0_CLK (P_DONTCARE)
|
||||||
|
|
||||||
|
#define P_MII0 {\
|
||||||
|
P_MII0_ETxD0, \
|
||||||
|
P_MII0_ETxD1, \
|
||||||
|
P_MII0_ETxD2, \
|
||||||
|
P_MII0_ETxD3, \
|
||||||
|
P_MII0_ETxEN, \
|
||||||
|
P_MII0_TxCLK, \
|
||||||
|
P_MII0_PHYINT, \
|
||||||
|
P_MII0_COL, \
|
||||||
|
P_MII0_ERxD0, \
|
||||||
|
P_MII0_ERxD1, \
|
||||||
|
P_MII0_ERxD2, \
|
||||||
|
P_MII0_ERxD3, \
|
||||||
|
P_MII0_ERxDV, \
|
||||||
|
P_MII0_ERxCLK, \
|
||||||
|
P_MII0_ERxER, \
|
||||||
|
P_MII0_CRS, \
|
||||||
|
P_MDC, \
|
||||||
|
P_MDIO, 0}
|
||||||
|
|
||||||
|
#define P_RMII0 {\
|
||||||
|
P_MII0_ETxD0, \
|
||||||
|
P_MII0_ETxD1, \
|
||||||
|
P_MII0_ETxEN, \
|
||||||
|
P_MII0_ERxD0, \
|
||||||
|
P_MII0_ERxD1, \
|
||||||
|
P_MII0_ERxER, \
|
||||||
|
P_RMII0_REF_CLK, \
|
||||||
|
P_RMII0_MDINT, \
|
||||||
|
P_RMII0_CRS_DV, \
|
||||||
|
P_MDC, \
|
||||||
|
P_MDIO, 0}
|
||||||
|
|
||||||
|
#endif /* _MACH_PORTMUX_H_ */
|
||||||
Loading…
Reference in New Issue