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drm/amdgpu: disallow direct upload save restore list from gfx driver 

Direct uploading save/restore list via mmio register writes breaks the security
policy. Instead, the driver should pass s&r list to psp.

For all the ASICs that use rlc v2_1 headers, the driver actually upload s&r list
twice, in non-psp ucode front door loading phase and gfx pg initialization phase.
The latter is not allowed.

VG12 is the only exception where the driver still keeps legacy approach for S&R
list uploading. In theory, this can be elimnated if we have valid srcntl ucode
for VG12.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Candice Li <Candice.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2019-11-04 16:20:06 +08:00 committed by Alex Deucher
parent d7c5782acd
commit 58f46d4b65
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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@ -2725,7 +2725,8 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
* And it's needed by gfxoff feature. * And it's needed by gfxoff feature.
*/ */
if (adev->gfx.rlc.is_rlc_v2_1) { if (adev->gfx.rlc.is_rlc_v2_1) {
gfx_v9_1_init_rlc_save_restore_list(adev); if (adev->asic_type == CHIP_VEGA12)
gfx_v9_1_init_rlc_save_restore_list(adev);
gfx_v9_0_enable_save_restore_machine(adev); gfx_v9_0_enable_save_restore_machine(adev);
} }