Merge series "" from :
Changes from ChiYuan Huang <cy_huang@richtek.com> to fix a couple of bugs and add a new device ID/quirk for the rt9120s to the driver.
This commit is contained in:
commit
58da0d84fd
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/bits.h>
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/i2c.h>
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@ -23,9 +24,11 @@
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#define RT9120_REG_ERRRPT 0x10
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#define RT9120_REG_ERRRPT 0x10
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#define RT9120_REG_MSVOL 0x20
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#define RT9120_REG_MSVOL 0x20
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#define RT9120_REG_SWRESET 0x40
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#define RT9120_REG_SWRESET 0x40
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#define RT9120_REG_INTERCFG 0x63
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#define RT9120_REG_INTERNAL0 0x65
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#define RT9120_REG_INTERNAL0 0x65
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#define RT9120_REG_INTERNAL1 0x69
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#define RT9120_REG_INTERNAL1 0x69
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#define RT9120_REG_UVPOPT 0x6C
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#define RT9120_REG_UVPOPT 0x6C
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#define RT9120_REG_DIGCFG 0xF8
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#define RT9120_VID_MASK GENMASK(15, 8)
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#define RT9120_VID_MASK GENMASK(15, 8)
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#define RT9120_SWRST_MASK BIT(7)
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#define RT9120_SWRST_MASK BIT(7)
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@ -46,8 +49,10 @@
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#define RT9120_CFG_WORDLEN_24 24
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#define RT9120_CFG_WORDLEN_24 24
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#define RT9120_CFG_WORDLEN_32 32
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#define RT9120_CFG_WORDLEN_32 32
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#define RT9120_DVDD_UVSEL_MASK GENMASK(5, 4)
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#define RT9120_DVDD_UVSEL_MASK GENMASK(5, 4)
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#define RT9120_AUTOSYNC_MASK BIT(6)
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#define RT9120_VENDOR_ID 0x4200
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#define RT9120_VENDOR_ID 0x42
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#define RT9120S_VENDOR_ID 0x43
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#define RT9120_RESET_WAITMS 20
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#define RT9120_RESET_WAITMS 20
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#define RT9120_CHIPON_WAITMS 20
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#define RT9120_CHIPON_WAITMS 20
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#define RT9120_AMPON_WAITMS 50
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#define RT9120_AMPON_WAITMS 50
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@ -61,9 +66,16 @@
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SNDRV_PCM_FMTBIT_S24_LE |\
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SNDRV_PCM_FMTBIT_S24_LE |\
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SNDRV_PCM_FMTBIT_S32_LE)
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SNDRV_PCM_FMTBIT_S32_LE)
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enum {
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CHIP_IDX_RT9120 = 0,
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CHIP_IDX_RT9120S,
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CHIP_IDX_MAX
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};
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struct rt9120_data {
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struct rt9120_data {
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struct device *dev;
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struct device *dev;
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struct regmap *regmap;
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struct regmap *regmap;
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int chip_idx;
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};
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};
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/* 11bit [min,max,step] = [-103.9375dB, 24dB, 0.0625dB] */
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/* 11bit [min,max,step] = [-103.9375dB, 24dB, 0.0625dB] */
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@ -149,8 +161,12 @@ static int rt9120_codec_probe(struct snd_soc_component *comp)
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snd_soc_component_init_regmap(comp, data->regmap);
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snd_soc_component_init_regmap(comp, data->regmap);
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/* Internal setting */
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/* Internal setting */
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snd_soc_component_write(comp, RT9120_REG_INTERNAL1, 0x03);
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if (data->chip_idx == CHIP_IDX_RT9120S) {
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snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x69);
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snd_soc_component_write(comp, RT9120_REG_INTERCFG, 0xde);
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snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x66);
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} else
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snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04);
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return 0;
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return 0;
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}
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}
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@ -201,8 +217,8 @@ static int rt9120_hw_params(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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struct snd_soc_dai *dai)
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{
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{
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struct snd_soc_component *comp = dai->component;
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struct snd_soc_component *comp = dai->component;
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unsigned int param_width, param_slot_width;
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unsigned int param_width, param_slot_width, auto_sync;
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int width;
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int width, fs;
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switch (width = params_width(param)) {
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switch (width = params_width(param)) {
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case 16:
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case 16:
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@ -240,6 +256,16 @@ static int rt9120_hw_params(struct snd_pcm_substream *substream,
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snd_soc_component_update_bits(comp, RT9120_REG_I2SWL,
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snd_soc_component_update_bits(comp, RT9120_REG_I2SWL,
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RT9120_AUDWL_MASK, param_slot_width);
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RT9120_AUDWL_MASK, param_slot_width);
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fs = width * params_channels(param);
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/* If fs is divided by 48, disable auto sync */
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if (fs % 48 == 0)
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auto_sync = 0;
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else
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auto_sync = RT9120_AUTOSYNC_MASK;
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snd_soc_component_update_bits(comp, RT9120_REG_DIGCFG,
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RT9120_AUTOSYNC_MASK, auto_sync);
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return 0;
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return 0;
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}
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}
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@ -279,9 +305,11 @@ static const struct regmap_range rt9120_rd_yes_ranges[] = {
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regmap_reg_range(0x20, 0x27),
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regmap_reg_range(0x20, 0x27),
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regmap_reg_range(0x30, 0x38),
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regmap_reg_range(0x30, 0x38),
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regmap_reg_range(0x3A, 0x40),
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regmap_reg_range(0x3A, 0x40),
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regmap_reg_range(0x63, 0x63),
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regmap_reg_range(0x65, 0x65),
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regmap_reg_range(0x65, 0x65),
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regmap_reg_range(0x69, 0x69),
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regmap_reg_range(0x69, 0x69),
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regmap_reg_range(0x6C, 0x6C)
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regmap_reg_range(0x6C, 0x6C),
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regmap_reg_range(0xF8, 0xF8)
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};
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};
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static const struct regmap_access_table rt9120_rd_table = {
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static const struct regmap_access_table rt9120_rd_table = {
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@ -297,9 +325,11 @@ static const struct regmap_range rt9120_wr_yes_ranges[] = {
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regmap_reg_range(0x30, 0x38),
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regmap_reg_range(0x30, 0x38),
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regmap_reg_range(0x3A, 0x3D),
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regmap_reg_range(0x3A, 0x3D),
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regmap_reg_range(0x40, 0x40),
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regmap_reg_range(0x40, 0x40),
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regmap_reg_range(0x63, 0x63),
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regmap_reg_range(0x65, 0x65),
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regmap_reg_range(0x65, 0x65),
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regmap_reg_range(0x69, 0x69),
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regmap_reg_range(0x69, 0x69),
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regmap_reg_range(0x6C, 0x6C)
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regmap_reg_range(0x6C, 0x6C),
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regmap_reg_range(0xF8, 0xF8)
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};
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};
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static const struct regmap_access_table rt9120_wr_table = {
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static const struct regmap_access_table rt9120_wr_table = {
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@ -370,7 +400,7 @@ static int rt9120_reg_write(void *context, unsigned int reg, unsigned int val)
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static const struct regmap_config rt9120_regmap_config = {
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static const struct regmap_config rt9120_regmap_config = {
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.reg_bits = 8,
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.reg_bits = 8,
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.val_bits = 32,
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.val_bits = 32,
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.max_register = RT9120_REG_UVPOPT,
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.max_register = RT9120_REG_DIGCFG,
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.reg_read = rt9120_reg_read,
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.reg_read = rt9120_reg_read,
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.reg_write = rt9120_reg_write,
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.reg_write = rt9120_reg_write,
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@ -388,8 +418,16 @@ static int rt9120_check_vendor_info(struct rt9120_data *data)
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if (ret)
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if (ret)
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return ret;
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return ret;
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if ((devid & RT9120_VID_MASK) != RT9120_VENDOR_ID) {
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devid = FIELD_GET(RT9120_VID_MASK, devid);
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dev_err(data->dev, "DEVID not correct [0x%04x]\n", devid);
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switch (devid) {
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case RT9120_VENDOR_ID:
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data->chip_idx = CHIP_IDX_RT9120;
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break;
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case RT9120S_VENDOR_ID:
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data->chip_idx = CHIP_IDX_RT9120S;
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break;
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default:
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dev_err(data->dev, "DEVID not correct [0x%0x]\n", devid);
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return -ENODEV;
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return -ENODEV;
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}
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}
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