V4L/DVB (8485): v4l-dvb: remove broken PlanB driver
The PlanB driver has been broken since around May 2004. No one stepped in to maintain it, so it is now being removed. Signed-off-by: Adrian Bunk <bunk@kernel.org> Acked-by: Michel Lanners <mlan@cpu.lu> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Adrian Bunk
Mauro Carvalho Chehab
parent
322e4095c9
commit
58cfdf9acf
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@ -487,17 +487,6 @@ config VIDEO_PMS
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To compile this driver as a module, choose M here: the
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module will be called pms.
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config VIDEO_PLANB
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tristate "PlanB Video-In on PowerMac"
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depends on PPC_PMAC && VIDEO_V4L1 && BROKEN
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help
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PlanB is the V4L driver for the PowerMac 7x00/8x00 series video
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input hardware. If you want to experiment with this, say Y.
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Otherwise, or if you don't understand a word, say N. See
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<http://www.cpu.lu/~mlan/linux/dev/planb.html> for more info.
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Saying M will compile this driver as a module (planb).
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config VIDEO_BWQCAM
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tristate "Quickcam BW Video For Linux"
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depends on PARPORT && VIDEO_V4L1
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@ -57,7 +57,6 @@ obj-$(CONFIG_VIDEO_ZORAN_DC30) += zr36050.o zr36016.o
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obj-$(CONFIG_VIDEO_ZORAN_ZR36060) += zr36060.o
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obj-$(CONFIG_VIDEO_PMS) += pms.o
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obj-$(CONFIG_VIDEO_PLANB) += planb.o
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obj-$(CONFIG_VIDEO_VINO) += vino.o indycam.o
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obj-$(CONFIG_VIDEO_STRADIS) += stradis.o
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obj-$(CONFIG_VIDEO_CPIA) += cpia.o
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File diff suppressed because it is too large
Load Diff
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@ -1,232 +0,0 @@
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/*
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planb - PlanB frame grabber driver
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PlanB is used in the 7x00/8x00 series of PowerMacintosh
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Computers as video input DMA controller.
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Copyright (C) 1998 Michel Lanners (mlan@cpu.lu)
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Based largely on the bttv driver by Ralph Metzler (rjkm@thp.uni-koeln.de)
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Additional debugging and coding by Takashi Oe (toe@unlserve.unl.edu)
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* $Id: planb.h,v 1.13 1999/05/03 19:28:56 mlan Exp $ */
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#ifndef _PLANB_H_
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#define _PLANB_H_
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#ifdef __KERNEL__
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#include <asm/dbdma.h>
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#include "saa7196.h"
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#endif /* __KERNEL__ */
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#define PLANB_DEVICE_NAME "Apple PlanB Video-In"
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#define PLANB_REV "1.0"
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#ifdef __KERNEL__
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//#define PLANB_GSCANLINE /* use this if apps have the notion of */
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/* grab buffer scanline */
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/* This should be safe for both PAL and NTSC */
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#define PLANB_MAXPIXELS 768
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#define PLANB_MAXLINES 576
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#define PLANB_NTSC_MAXLINES 480
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/* Uncomment your preferred norm ;-) */
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#define PLANB_DEF_NORM VIDEO_MODE_PAL
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//#define PLANB_DEF_NORM VIDEO_MODE_NTSC
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//#define PLANB_DEF_NORM VIDEO_MODE_SECAM
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/* fields settings */
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#define PLANB_GRAY 0x1 /* 8-bit mono? */
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#define PLANB_COLOUR15 0x2 /* 16-bit mode */
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#define PLANB_COLOUR32 0x4 /* 32-bit mode */
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#define PLANB_CLIPMASK 0x8 /* hardware clipmasking */
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/* misc. flags for PlanB DMA operation */
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#define CH_SYNC 0x1 /* synchronize channels (set by ch1;
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cleared by ch2) */
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#define FIELD_SYNC 0x2 /* used for the start of each field
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(0 -> 1 -> 0 for ch1; 0 -> 1 for ch2) */
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#define EVEN_FIELD 0x0 /* even field is detected if unset */
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#define DMA_ABORT 0x2 /* error or just out of sync if set */
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#define ODD_FIELD 0x4 /* odd field is detected if set */
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/* for capture operations */
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#define MAX_GBUFFERS 2
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/* note PLANB_MAX_FBUF must be divisible by PAGE_SIZE */
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#ifdef PLANB_GSCANLINE
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#define PLANB_MAX_FBUF 0x240000 /* 576 * 1024 * 4 */
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#define TAB_FACTOR (1)
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#else
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#define PLANB_MAX_FBUF 0x1b0000 /* 576 * 768 * 4 */
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#define TAB_FACTOR (2)
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#endif
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#endif /* __KERNEL__ */
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struct planb_saa_regs {
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unsigned char addr;
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unsigned char val;
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};
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struct planb_stat_regs {
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unsigned int ch1_stat;
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unsigned int ch2_stat;
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unsigned char saa_stat0;
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unsigned char saa_stat1;
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};
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struct planb_any_regs {
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unsigned int offset;
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unsigned int bytes;
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unsigned char data[128];
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};
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/* planb private ioctls */
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#define PLANBIOCGSAAREGS _IOWR('v', BASE_VIDIOCPRIVATE, struct planb_saa_regs) /* Read a saa7196 reg value */
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#define PLANBIOCSSAAREGS _IOW('v', BASE_VIDIOCPRIVATE + 1, struct planb_saa_regs) /* Set a saa7196 reg value */
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#define PLANBIOCGSTAT _IOR('v', BASE_VIDIOCPRIVATE + 2, struct planb_stat_regs) /* Read planb status */
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#define PLANB_TV_MODE 1
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#define PLANB_VTR_MODE 2
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#define PLANBIOCGMODE _IOR('v', BASE_VIDIOCPRIVATE + 3, int) /* Get TV/VTR mode */
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#define PLANBIOCSMODE _IOW('v', BASE_VIDIOCPRIVATE + 4, int) /* Set TV/VTR mode */
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#ifdef PLANB_GSCANLINE
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#define PLANBG_GRAB_BPL _IOR('v', BASE_VIDIOCPRIVATE + 5, int) /* # of bytes per scanline in grab buffer */
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#endif
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/* call wake_up_interruptible() with appropriate actions */
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#define PLANB_INTR_DEBUG _IOW('v', BASE_VIDIOCPRIVATE + 20, int)
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/* investigate which reg does what */
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#define PLANB_INV_REGS _IOWR('v', BASE_VIDIOCPRIVATE + 21, struct planb_any_regs)
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#ifdef __KERNEL__
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/* Potentially useful macros */
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#define PLANB_SET(x) ((x) << 16 | (x))
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#define PLANB_CLR(x) ((x) << 16)
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/* This represents the physical register layout */
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struct planb_registers {
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volatile struct dbdma_regs ch1; /* 0x00: video in */
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volatile unsigned int even; /* 0x40: even field setting */
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volatile unsigned int odd; /* 0x44; odd field setting */
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unsigned int pad1[14]; /* empty? */
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volatile struct dbdma_regs ch2; /* 0x80: clipmask out */
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unsigned int pad2[16]; /* 0xc0: empty? */
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volatile unsigned int reg3; /* 0x100: ???? */
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volatile unsigned int intr_stat; /* 0x104: irq status */
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#define PLANB_CLR_IRQ 0x00 /* clear Plan B interrupt */
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#define PLANB_GEN_IRQ 0x01 /* assert Plan B interrupt */
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#define PLANB_FRM_IRQ 0x0100 /* end of frame */
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unsigned int pad3[1]; /* empty? */
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volatile unsigned int reg5; /* 0x10c: ??? */
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unsigned int pad4[60]; /* empty? */
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volatile unsigned char saa_addr; /* 0x200: SAA subadr */
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char pad5[3];
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volatile unsigned char saa_regval; /* SAA7196 write reg. val */
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char pad6[3];
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volatile unsigned char saa_status; /* SAA7196 status byte */
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/* There is more unused stuff here */
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};
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struct planb_window {
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int x, y;
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ushort width, height;
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ushort bpp, bpl, depth, pad;
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ushort swidth, sheight;
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int norm;
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int interlace;
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u32 color_fmt;
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int chromakey;
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int mode; /* used to switch between TV/VTR modes */
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};
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struct planb_suspend {
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int overlay;
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int frame;
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struct dbdma_cmd cmd;
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};
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struct planb {
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struct video_device video_dev;
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struct video_picture picture; /* Current picture params */
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struct video_audio audio_dev; /* Current audio params */
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volatile struct planb_registers *planb_base; /* virt base of planb */
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struct planb_registers *planb_base_phys; /* phys base of planb */
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void *priv_space; /* Org. alloc. mem for kfree */
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int user;
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unsigned int tab_size;
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int maxlines;
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struct mutex lock;
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unsigned int irq; /* interrupt number */
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volatile unsigned int intr_mask;
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struct pci_dev *dev; /* Our PCI device */
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int overlay; /* overlay running? */
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struct planb_window win;
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unsigned long frame_buffer_phys; /* We need phys for DMA */
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int offset; /* offset of pixel 1 */
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volatile struct dbdma_cmd *ch1_cmd; /* Video In DMA cmd buffer */
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volatile struct dbdma_cmd *ch2_cmd; /* Clip Out DMA cmd buffer */
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volatile struct dbdma_cmd *overlay_last1;
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volatile struct dbdma_cmd *overlay_last2;
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unsigned long ch1_cmd_phys;
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volatile unsigned char *mask; /* Clipmask buffer */
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int suspend;
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wait_queue_head_t suspendq;
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struct planb_suspend suspended;
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int cmd_buff_inited; /* cmd buffer inited? */
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int grabbing;
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unsigned int gcount;
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wait_queue_head_t capq;
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int last_fr;
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int prev_last_fr;
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unsigned char **rawbuf;
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int rawbuf_size;
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int gbuf_idx[MAX_GBUFFERS];
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volatile struct dbdma_cmd *cap_cmd[MAX_GBUFFERS];
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volatile struct dbdma_cmd *last_cmd[MAX_GBUFFERS];
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volatile struct dbdma_cmd *pre_cmd[MAX_GBUFFERS];
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int need_pre_capture[MAX_GBUFFERS];
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#define PLANB_DUMMY 40 /* # of command buf's allocated for pre-capture seq. */
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int gwidth[MAX_GBUFFERS], gheight[MAX_GBUFFERS];
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unsigned int gfmt[MAX_GBUFFERS];
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int gnorm_switch[MAX_GBUFFERS];
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volatile unsigned int *frame_stat;
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#define GBUFFER_UNUSED 0x00U
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#define GBUFFER_GRABBING 0x01U
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#define GBUFFER_DONE 0x02U
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#ifdef PLANB_GSCANLINE
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int gbytes_per_line;
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#else
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#define MAX_LNUM 431 /* change this if PLANB_MAXLINES or */
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/* PLANB_MAXPIXELS changes */
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int l_fr_addr_idx[MAX_GBUFFERS];
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unsigned char *l_to_addr[MAX_GBUFFERS][MAX_LNUM];
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int l_to_next_idx[MAX_GBUFFERS][MAX_LNUM];
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int l_to_next_size[MAX_GBUFFERS][MAX_LNUM];
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int lsize[MAX_GBUFFERS], lnum[MAX_GBUFFERS];
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#endif
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};
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#endif /* __KERNEL__ */
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#endif /* _PLANB_H_ */
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@ -1,117 +0,0 @@
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/*
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Definitions for the Philips SAA7196 digital video decoder,
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scaler, and clock generator circuit (DESCpro), as used in
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the PlanB video input of the Powermac 7x00/8x00 series.
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Copyright (C) 1998 Michel Lanners (mlan@cpu.lu)
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The register defines are shamelessly copied from the meteor
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driver out of NetBSD (with permission),
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and are copyrighted (c) 1995 Mark Tinguely and Jim Lowe
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(Thanks !)
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Additional debugging and coding by Takashi Oe (toe@unlinfo.unl.edu)
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The default values used for PlanB are my mistakes.
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*/
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/* $Id: saa7196.h,v 1.5 1999/03/26 23:28:47 mlan Exp $ */
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#ifndef _SAA7196_H_
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#define _SAA7196_H_
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#define SAA7196_NUMREGS 0x31 /* Number of registers (used)*/
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#define NUM_SUPPORTED_NORM 3 /* Number of supported norms by PlanB */
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/* Decoder part: */
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#define SAA7196_IDEL 0x00 /* Increment delay */
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#define SAA7196_HSB5 0x01 /* H-sync begin; 50 hz */
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#define SAA7196_HSS5 0x02 /* H-sync stop; 50 hz */
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#define SAA7196_HCB5 0x03 /* H-clamp begin; 50 hz */
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#define SAA7196_HCS5 0x04 /* H-clamp stop; 50 hz */
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#define SAA7196_HSP5 0x05 /* H-sync after PHI1; 50 hz */
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#define SAA7196_LUMC 0x06 /* Luminance control */
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#define SAA7196_HUEC 0x07 /* Hue control */
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#define SAA7196_CKTQ 0x08 /* Colour Killer Threshold QAM (PAL, NTSC) */
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#define SAA7196_CKTS 0x09 /* Colour Killer Threshold SECAM */
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#define SAA7196_PALS 0x0a /* PAL switch sensitivity */
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#define SAA7196_SECAMS 0x0b /* SECAM switch sensitivity */
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#define SAA7196_CGAINC 0x0c /* Chroma gain control */
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#define SAA7196_STDC 0x0d /* Standard/Mode control */
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#define SAA7196_IOCC 0x0e /* I/O and Clock Control */
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#define SAA7196_CTRL1 0x0f /* Control #1 */
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#define SAA7196_CTRL2 0x10 /* Control #2 */
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#define SAA7196_CGAINR 0x11 /* Chroma Gain Reference */
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#define SAA7196_CSAT 0x12 /* Chroma Saturation */
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#define SAA7196_CONT 0x13 /* Luminance Contrast */
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#define SAA7196_HSB6 0x14 /* H-sync begin; 60 hz */
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#define SAA7196_HSS6 0x15 /* H-sync stop; 60 hz */
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#define SAA7196_HCB6 0x16 /* H-clamp begin; 60 hz */
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#define SAA7196_HCS6 0x17 /* H-clamp stop; 60 hz */
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#define SAA7196_HSP6 0x18 /* H-sync after PHI1; 60 hz */
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#define SAA7196_BRIG 0x19 /* Luminance Brightness */
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/* Scaler part: */
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#define SAA7196_FMTS 0x20 /* Formats and sequence */
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#define SAA7196_OUTPIX 0x21 /* Output data pixel/line */
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#define SAA7196_INPIX 0x22 /* Input data pixel/line */
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#define SAA7196_HWS 0x23 /* Horiz. window start */
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#define SAA7196_HFILT 0x24 /* Horiz. filter */
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#define SAA7196_OUTLINE 0x25 /* Output data lines/field */
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#define SAA7196_INLINE 0x26 /* Input data lines/field */
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#define SAA7196_VWS 0x27 /* Vertical window start */
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#define SAA7196_VYP 0x28 /* AFS/vertical Y processing */
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#define SAA7196_VBS 0x29 /* Vertical Bypass start */
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#define SAA7196_VBCNT 0x2a /* Vertical Bypass count */
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#define SAA7196_VBP 0x2b /* veritcal Bypass Polarity */
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#define SAA7196_VLOW 0x2c /* Colour-keying lower V limit */
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#define SAA7196_VHIGH 0x2d /* Colour-keying upper V limit */
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#define SAA7196_ULOW 0x2e /* Colour-keying lower U limit */
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#define SAA7196_UHIGH 0x2f /* Colour-keying upper U limit */
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#define SAA7196_DPATH 0x30 /* Data path setting */
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/* Initialization default values: */
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unsigned char saa_regs[NUM_SUPPORTED_NORM][SAA7196_NUMREGS] = {
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/* PAL, 768x576 (no scaling), composite video-in */
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/* Decoder: */
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{ 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x63, 0xff,
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0xfe, 0xf0, 0xfe, 0xe0, 0x20, 0x06, 0x3b, 0x98,
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0x00, 0x59, 0x41, 0x45, 0x34, 0x0a, 0xf4, 0xd2,
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0xe9, 0xa2,
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/* Padding */
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0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
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/* Scaler: */
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0x72, 0x80, 0x00, 0x03, 0x8d, 0x20, 0x20, 0x12,
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0xa5, 0x12, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
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0x87 },
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/* NTSC, 640x480? (no scaling), composite video-in */
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/* Decoder: */
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{ 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x50, 0x00,
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0xf8, 0xf0, 0xfe, 0xe0, 0x00, 0x06, 0x3b, 0x98,
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0x00, 0x2c, 0x3d, 0x40, 0x34, 0x0a, 0xf4, 0xd2,
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0xe9, 0x98,
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/* Padding */
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0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
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/* Scaler: */
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0x72, 0x80, 0x80, 0x03, 0x89, 0xf0, 0xf0, 0x0d,
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0xa0, 0x0d, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
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0x87 },
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/* SECAM, 768x576 (no scaling), composite video-in */
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/* Decoder: */
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{ 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x63, 0xff,
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0xfe, 0xf0, 0xfe, 0xe0, 0x20, 0x07, 0x3b, 0x98,
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0x00, 0x59, 0x41, 0x45, 0x34, 0x0a, 0xf4, 0xd2,
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0xe9, 0xa2,
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/* Padding */
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0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
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/* Scaler: */
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0x72, 0x80, 0x00, 0x03, 0x8d, 0x20, 0x20, 0x12,
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0xa5, 0x12, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
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0x87 }
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};
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#endif /* _SAA7196_H_ */
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||||
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