drm/i915: rip out the PM_IIR WARN
After banging my head against this for the past few months, I still don't see how this could possible race under the premise that once an irq bit is masked in PM_IMR and reset in PM_IIR it won't show up again until we unmask it in PM_IMR. Still, we have reports of this being seen in the wild. Now Bspec has this little bit of lovely language in the PMIIR register: Public SNB Docs, Vol3Part2, 2.5.14 "PMIIR": "For each bit, the IIR can store a second pending interrupt if two or more of the same interrupt conditions occur before the first condition is cleared. Upon clearing the interrupt, the IIR bit will momentarily go low, then return high to indicate there is another interrupt pending." Now if we presume that PMIMR only prevent new interrupts from being queued, we could easily end up masking an interrupt and clearing it, but the 2nd pending interrupt setting the bit in PMIIR right away again. Which leads, the next time the irq handler runs, to hitting the WARN. Also, no bad side effects of this have ever been reported. And we've tracked down our issues with the gpu turbo getting stuck to bogus interrupt generation limits in th RPLIMIT register. So let's just rip out this WARN as bogus and call it a day. The only shallow thing here is that this 2-deep irq queue in the hw makes you wonder how racy the windows irq handler is ... Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=42907 Cc: stable@vger.kernel.org Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -412,7 +412,6 @@ static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
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*/
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*/
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spin_lock_irqsave(&dev_priv->rps_lock, flags);
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spin_lock_irqsave(&dev_priv->rps_lock, flags);
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WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
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dev_priv->pm_iir |= pm_iir;
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dev_priv->pm_iir |= pm_iir;
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I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
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I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
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POSTING_READ(GEN6_PMIMR);
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POSTING_READ(GEN6_PMIMR);
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