net: sparx5: Implement SIOCSHWTSTAMP and SIOCGHWTSTAMP
Implement the ioctl callbacks SIOCSHWTSTAMP and SIOCGHWTSTAMP to allow to configure the ports to enable/disable timestamping for TX. The RX timestamping is always enabled. The HW is capable to run both 1-step timestamping and 2-step timestamping. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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0933bd0404
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589a07b8eb
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@ -84,6 +84,10 @@ enum sparx5_vlan_port_type {
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#define SPARX5_PHC_COUNT 3
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#define SPARX5_PHC_PORT 0
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#define IFH_REW_OP_NOOP 0x0
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#define IFH_REW_OP_ONE_STEP_PTP 0x3
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#define IFH_REW_OP_TWO_STEP_PTP 0x4
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struct sparx5;
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struct sparx5_db_hw {
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@ -174,6 +178,8 @@ struct sparx5_port {
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u32 custom_etype;
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bool vlan_aware;
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struct hrtimer inj_timer;
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/* ptp */
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u8 ptp_cmd;
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};
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enum sparx5_core_clockfreq {
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@ -242,6 +248,7 @@ struct sparx5 {
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bool ptp;
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struct sparx5_phc phc[SPARX5_PHC_COUNT];
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spinlock_t ptp_clock_lock; /* lock for phc */
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struct mutex ptp_lock; /* lock for ptp interface state */
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};
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/* sparx5_switchdev.c */
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@ -314,6 +321,8 @@ void sparx5_unregister_netdevs(struct sparx5 *sparx5);
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/* sparx5_ptp.c */
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int sparx5_ptp_init(struct sparx5 *sparx5);
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void sparx5_ptp_deinit(struct sparx5 *sparx5);
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int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct ifreq *ifr);
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int sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct ifreq *ifr);
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/* Clock period in picoseconds */
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static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
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@ -179,6 +179,24 @@ static int sparx5_get_port_parent_id(struct net_device *dev,
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return 0;
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}
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static int sparx5_port_ioctl(struct net_device *dev, struct ifreq *ifr,
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int cmd)
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{
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struct sparx5_port *sparx5_port = netdev_priv(dev);
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struct sparx5 *sparx5 = sparx5_port->sparx5;
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if (!phy_has_hwtstamp(dev->phydev) && sparx5->ptp) {
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switch (cmd) {
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case SIOCSHWTSTAMP:
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return sparx5_ptp_hwtstamp_set(sparx5_port, ifr);
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case SIOCGHWTSTAMP:
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return sparx5_ptp_hwtstamp_get(sparx5_port, ifr);
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}
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}
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return phy_mii_ioctl(dev->phydev, ifr, cmd);
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}
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static const struct net_device_ops sparx5_port_netdev_ops = {
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.ndo_open = sparx5_port_open,
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.ndo_stop = sparx5_port_stop,
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@ -189,6 +207,7 @@ static const struct net_device_ops sparx5_port_netdev_ops = {
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.ndo_validate_addr = eth_validate_addr,
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.ndo_get_stats64 = sparx5_get_stats64,
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.ndo_get_port_parent_id = sparx5_get_port_parent_id,
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.ndo_eth_ioctl = sparx5_port_ioctl,
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};
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bool sparx5_netdevice_check(const struct net_device *dev)
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@ -74,6 +74,79 @@ static u64 sparx5_ptp_get_nominal_value(struct sparx5 *sparx5)
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return res;
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}
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int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, struct ifreq *ifr)
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{
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struct sparx5 *sparx5 = port->sparx5;
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struct hwtstamp_config cfg;
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struct sparx5_phc *phc;
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/* For now don't allow to run ptp on ports that are part of a bridge,
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* because in case of transparent clock the HW will still forward the
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* frames, so there would be duplicate frames
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*/
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if (test_bit(port->portno, sparx5->bridge_mask))
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return -EINVAL;
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if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
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return -EFAULT;
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switch (cfg.tx_type) {
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case HWTSTAMP_TX_ON:
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port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
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break;
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case HWTSTAMP_TX_ONESTEP_SYNC:
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port->ptp_cmd = IFH_REW_OP_ONE_STEP_PTP;
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break;
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case HWTSTAMP_TX_OFF:
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port->ptp_cmd = IFH_REW_OP_NOOP;
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break;
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default:
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return -ERANGE;
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}
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switch (cfg.rx_filter) {
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case HWTSTAMP_FILTER_NONE:
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break;
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case HWTSTAMP_FILTER_ALL:
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case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
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case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
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case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
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case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
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case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
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case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
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case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
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case HWTSTAMP_FILTER_PTP_V2_EVENT:
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case HWTSTAMP_FILTER_PTP_V2_SYNC:
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case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
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case HWTSTAMP_FILTER_NTP_ALL:
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cfg.rx_filter = HWTSTAMP_FILTER_ALL;
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break;
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default:
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return -ERANGE;
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}
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/* Commit back the result & save it */
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mutex_lock(&sparx5->ptp_lock);
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phc = &sparx5->phc[SPARX5_PHC_PORT];
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memcpy(&phc->hwtstamp_config, &cfg, sizeof(cfg));
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mutex_unlock(&sparx5->ptp_lock);
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return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
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}
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int sparx5_ptp_hwtstamp_get(struct sparx5_port *port, struct ifreq *ifr)
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{
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struct sparx5 *sparx5 = port->sparx5;
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struct sparx5_phc *phc;
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phc = &sparx5->phc[SPARX5_PHC_PORT];
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return copy_to_user(ifr->ifr_data, &phc->hwtstamp_config,
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sizeof(phc->hwtstamp_config)) ? -EFAULT : 0;
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}
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static int sparx5_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
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{
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struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info);
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@ -291,6 +364,7 @@ int sparx5_ptp_init(struct sparx5 *sparx5)
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}
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spin_lock_init(&sparx5->ptp_clock_lock);
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mutex_init(&sparx5->ptp_lock);
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/* Disable master counters */
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spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0), sparx5, PTP_PTP_DOM_CFG);
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