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ARM: tlb: don't bother with barriers for branch predictor maintenance 

Branch predictor maintenance is only required when we are either
changing the kernel's view of memory (switching tables completely) or
dealing with ASID rollover.

Both of these use-cases require subsequent TLB invalidation, which has
the relevant barrier instructions to ensure completion and visibility
of the maintenance, so this patch removes the instruction barrier from
[local_]flush_bp_all.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon 2013-05-23 18:29:18 +01:00
parent f0915781bd
commit 587b9b6487
1 changed files with 4 additions and 3 deletions
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7
arch/arm/include/asm/tlbflush.h
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@ -527,6 +527,10 @@ static inline void __flush_tlb_kernel_page(unsigned long kaddr)
}
}
/*
* Branch predictor maintenance is paired with full TLB invalidation, so
* there is no need for any barriers here.
*/
static inline void local_flush_bp_all(void)
{
const int zero = 0;
@ -536,9 +540,6 @@ static inline void local_flush_bp_all(void)
asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
else if (tlb_flag(TLB_V6_BP))
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
if (tlb_flag(TLB_BARRIER))
isb();
}
#include <asm/cputype.h>