[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces, and, depending on the specific model, PCI-E interface, PCI-X interface, SATA controllers, crypto unit, SPI interface, SDIO interface, device bus, NAND controller, DMA engine and/or XOR engine. This contains the basic structure and architecture register definitions. Signed-off-by: Tzachi Perelstein <tzachi@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Reviewed-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Tzachi Perelstein
Russell King
parent
d910a0aa21
commit
585cf17561
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@ -333,6 +333,12 @@ config ARCH_MXC
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help
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Support for Freescale MXC/iMX-based family of processors
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config ARCH_ORION
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bool "Marvell Orion"
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depends on MMU
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help
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Support for Marvell Orion System on Chip family.
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config ARCH_PNX4008
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bool "Philips Nexperia PNX4008 Mobile"
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help
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@ -441,6 +447,8 @@ source "arch/arm/mach-omap1/Kconfig"
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source "arch/arm/mach-omap2/Kconfig"
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source "arch/arm/mach-orion/Kconfig"
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source "arch/arm/plat-s3c24xx/Kconfig"
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source "arch/arm/plat-s3c/Kconfig"
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@ -139,6 +139,7 @@ endif
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machine-$(CONFIG_ARCH_KS8695) := ks8695
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incdir-$(CONFIG_ARCH_MXC) := mxc
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machine-$(CONFIG_ARCH_MX3) := mx3
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machine-$(CONFIG_ARCH_ORION) := orion
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ifeq ($(CONFIG_ARCH_EBSA110),y)
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# This is what happens if you forget the IOCS16 line.
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@ -0,0 +1,7 @@
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if ARCH_ORION
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menu "Orion Implementations"
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endmenu
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endif
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@ -0,0 +1 @@
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obj-y += common.o
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@ -0,0 +1,3 @@
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zreladdr-y := 0x00008000
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params_phys-y := 0x00000100
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initrd_phys-y := 0x00800000
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@ -0,0 +1,53 @@
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/*
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* arch/arm/mach-orion/common.c
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*
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* Core functions for Marvell Orion System On Chip
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/page.h>
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#include <asm/mach/map.h>
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#include <asm/arch/orion.h>
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#include "common.h"
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc orion_io_desc[] __initdata = {
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{
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.virtual = ORION_REGS_BASE,
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.pfn = __phys_to_pfn(ORION_REGS_BASE),
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.length = ORION_REGS_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = ORION_PCIE_IO_BASE,
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.pfn = __phys_to_pfn(ORION_PCIE_IO_BASE),
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.length = ORION_PCIE_IO_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = ORION_PCI_IO_BASE,
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.pfn = __phys_to_pfn(ORION_PCI_IO_BASE),
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.length = ORION_PCI_IO_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = ORION_PCIE_WA_BASE,
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.pfn = __phys_to_pfn(ORION_PCIE_WA_BASE),
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.length = ORION_PCIE_WA_SIZE,
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.type = MT_DEVICE
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},
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};
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void __init orion_map_io(void)
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{
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iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc));
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}
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@ -0,0 +1,9 @@
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#ifndef __ARCH_ORION_COMMON_H__
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#define __ARCH_ORION_COMMON_H__
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/*
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* Basic Orion init functions used early by machine-setup.
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*/
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void __init orion_map_io(void);
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#endif /* __ARCH_ORION_COMMON_H__ */
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@ -0,0 +1,17 @@
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/*
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* linux/include/asm-arm/arch-orion/debug-macro.S
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*
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* Debugging macro include header
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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.macro addruart,rx
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mov \rx, #0xf1000000
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orr \rx, \rx, #0x00012000
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.endm
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#define UART_SHIFT 2
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#include <asm/hardware/debug-8250.S>
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@ -0,0 +1 @@
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/* empty */
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@ -0,0 +1,31 @@
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/*
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* include/asm-arm/arch-orion/entry-macro.S
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*
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* Low-level IRQ helper macros for Orion platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/arch/orion.h>
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.macro disable_fiq
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =MAIN_IRQ_CAUSE
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, [\base, #0] @ main cause
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ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
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mov \irqnr, #0 @ default irqnr
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@ find cause bits that are unmasked
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ands \irqstat, \irqstat, \tmp @ clear Z flag if any
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clzne \irqnr, \irqstat @ calc irqnr
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rsbne \irqnr, \irqnr, #31
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.endm
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@ -0,0 +1,24 @@
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/*
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* include/asm-arm/arch-orion/hardware.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_ARCH_HARDWARE_H__
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#define __ASM_ARCH_HARDWARE_H__
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#include "orion.h"
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#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE
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#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
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#define pcibios_assign_all_busses() 1
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM 0x01000000
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#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
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#endif /* _ASM_ARCH_HARDWARE_H */
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@ -0,0 +1,27 @@
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/*
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* include/asm-arm/arch-orion/io.h
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*
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* Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#include "orion.h"
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#define IO_SPACE_LIMIT 0xffffffff
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#define IO_SPACE_REMAP ORION_PCI_SYS_IO_BASE
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static inline void __iomem *__io(unsigned long addr)
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{
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return (void __iomem *)addr;
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}
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#define __io(a) __io(a)
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#define __mem_pci(a) (a)
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#endif
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@ -0,0 +1,61 @@
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/*
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* include/asm-arm/arch-orion/irqs.h
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*
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* IRQ definitions for Orion SoC
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_IRQS_H__
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#define __ASM_ARCH_IRQS_H__
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#include "orion.h" /* need GPIO_MAX */
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/*
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* Orion Main Interrupt Controller
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*/
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#define IRQ_ORION_BRIDGE 0
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#define IRQ_ORION_DOORBELL_H2C 1
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#define IRQ_ORION_DOORBELL_C2H 2
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#define IRQ_ORION_UART0 3
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#define IRQ_ORION_UART1 4
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#define IRQ_ORION_I2C 5
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#define IRQ_ORION_GPIO_0_7 6
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#define IRQ_ORION_GPIO_8_15 7
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#define IRQ_ORION_GPIO_16_23 8
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#define IRQ_ORION_GPIO_24_31 9
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#define IRQ_ORION_PCIE0_ERR 10
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#define IRQ_ORION_PCIE0_INT 11
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#define IRQ_ORION_USB1_CTRL 12
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#define IRQ_ORION_DEV_BUS_ERR 14
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#define IRQ_ORION_PCI_ERR 15
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#define IRQ_ORION_USB_BR_ERR 16
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#define IRQ_ORION_USB0_CTRL 17
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#define IRQ_ORION_ETH_RX 18
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#define IRQ_ORION_ETH_TX 19
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#define IRQ_ORION_ETH_MISC 20
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#define IRQ_ORION_ETH_SUM 21
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#define IRQ_ORION_ETH_ERR 22
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#define IRQ_ORION_IDMA_ERR 23
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#define IRQ_ORION_IDMA_0 24
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#define IRQ_ORION_IDMA_1 25
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#define IRQ_ORION_IDMA_2 26
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#define IRQ_ORION_IDMA_3 27
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#define IRQ_ORION_CESA 28
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#define IRQ_ORION_SATA 29
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#define IRQ_ORION_XOR0 30
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#define IRQ_ORION_XOR1 31
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/*
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* Orion General Purpose Pins
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*/
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#define IRQ_ORION_GPIO_START 32
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#define NR_GPIO_IRQS GPIO_MAX
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#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
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#endif /* __ASM_ARCH_IRQS_H__ */
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@ -0,0 +1,15 @@
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/*
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* include/asm-arm/arch-orion/memory.h
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*
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* Marvell Orion memory definitions
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*/
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#ifndef __ASM_ARCH_MMU_H
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#define __ASM_ARCH_MMU_H
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#define PHYS_OFFSET UL(0x00000000)
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#define __virt_to_bus(x) __virt_to_phys(x)
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#define __bus_to_virt(x) __phys_to_virt(x)
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#endif
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@ -0,0 +1,140 @@
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/*
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* include/asm-arm/arch-orion/orion.h
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*
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* Generic definitions of Orion SoC flavors:
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* Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_ORION_H__
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#define __ASM_ARCH_ORION_H__
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/*******************************************************************************
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* Orion Address Map
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* Use the same mapping (1:1 virtual:physical) of internal registers and
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* PCI system (PCI+PCIE) for all machines.
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* Each machine defines the rest of its mapping (e.g. device bus flashes)
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******************************************************************************/
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#define ORION_REGS_BASE 0xf1000000
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#define ORION_REGS_SIZE SZ_1M
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#define ORION_PCI_SYS_MEM_BASE 0xe0000000
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#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE
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#define ORION_PCIE_MEM_SIZE SZ_128M
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#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
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#define ORION_PCI_MEM_SIZE SZ_128M
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#define ORION_PCI_SYS_IO_BASE 0xf2000000
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#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
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#define ORION_PCIE_IO_SIZE SZ_1M
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#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
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#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
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#define ORION_PCI_IO_SIZE SZ_1M
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#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
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/* Relevant only for Orion-NAS */
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#define ORION_PCIE_WA_BASE 0xf0000000
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#define ORION_PCIE_WA_SIZE SZ_16M
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/*******************************************************************************
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* Supported Devices & Revisions
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******************************************************************************/
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/* Orion-NAS (88F5182) */
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#define MV88F5182_DEV_ID 0x5182
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#define MV88F5182_REV_A2 2
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/* Orion-2 (88F5281) */
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#define MV88F5281_DEV_ID 0x5281
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#define MV88F5281_REV_D1 5
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#define MV88F5281_REV_D2 6
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/*******************************************************************************
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* Orion Registers Map
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******************************************************************************/
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#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000)
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#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000)
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#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000)
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#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000)
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#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000)
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#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000)
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#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000)
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#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000)
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#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000)
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#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x))
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#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x))
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#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x))
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#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x))
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#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x))
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#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x))
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#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x))
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#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x))
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#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x))
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/*******************************************************************************
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* Device Bus Registers
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******************************************************************************/
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#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000)
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#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004)
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#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050)
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#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008)
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#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010)
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#define GPIO_OUT ORION_DEV_BUS_REG(0x100)
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#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104)
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#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108)
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#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c)
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#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110)
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#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114)
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#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118)
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#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c)
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#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c)
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#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460)
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#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464)
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#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c)
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#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
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#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
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#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
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#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
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#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
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#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
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#define GPIO_MAX 32
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/***************************************************************************
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* Orion CPU Bridge Registers
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**************************************************************************/
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#define CPU_CONF ORION_BRIDGE_REG(0x100)
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#define CPU_CTRL ORION_BRIDGE_REG(0x104)
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#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108)
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#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c)
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#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C)
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#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110)
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#define BRIDGE_MASK ORION_BRIDGE_REG(0x114)
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#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
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||||
#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
|
||||
#define TIMER_CTRL ORION_BRIDGE_REG(0x300)
|
||||
#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8))
|
||||
#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8))
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*******************************************************************************
|
||||
* Helpers to access Orion registers
|
||||
******************************************************************************/
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define orion_read(r) __raw_readl(r)
|
||||
#define orion_write(r, val) __raw_writel(val, r)
|
||||
|
||||
/*
|
||||
* These are not preempt safe. Locks, if needed, must be taken care by caller.
|
||||
*/
|
||||
#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask))
|
||||
#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask))
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ASM_ARCH_ORION_H__ */
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* include/asm-arm/arch-orion/system.h
|
||||
*
|
||||
* Tzachi Perelstein <tzachi@marvell.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/orion.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
/*
|
||||
* Enable and issue soft reset
|
||||
*/
|
||||
orion_setbits(CPU_RESET_MASK, (1 << 2));
|
||||
orion_setbits(CPU_SOFT_RESET, 1);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* include/asm-arm/arch-orion/timex.h
|
||||
*
|
||||
* Tzachi Perelstein <tzachi@marvell.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#define ORION_TCLK 166666667
|
||||
#define CLOCK_TICK_RATE ORION_TCLK
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* include/asm-arm/arch-orion/uncompress.h
|
||||
*
|
||||
* Tzachi Perelstein <tzachi@marvell.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <asm/arch/orion.h>
|
||||
|
||||
#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14))
|
||||
#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0))
|
||||
|
||||
#define LSR_THRE 0x20
|
||||
|
||||
static void putc(const char c)
|
||||
{
|
||||
int j = 0x1000;
|
||||
while (--j && !(*MV_UART_LSR & LSR_THRE))
|
||||
barrier();
|
||||
*MV_UART_THR = c;
|
||||
}
|
||||
|
||||
static void flush(void)
|
||||
{
|
||||
}
|
||||
|
||||
static void orion_early_putstr(const char *ptr)
|
||||
{
|
||||
char c;
|
||||
while ((c = *ptr++) != '\0') {
|
||||
if (c == '\n')
|
||||
putc('\r');
|
||||
putc(c);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup()
|
||||
#define arch_decomp_wdog()
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
/*
|
||||
* include/asm-arm/arch-orion/vmalloc.h
|
||||
*/
|
||||
|
||||
#define VMALLOC_END 0xf0000000
|
||||
Loading…
Reference in New Issue