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serial: 8250_dw: Add StarFive JH7100 quirk 

On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
exactly 16 * 115200Hz and many other common bitrates. Trying this will
only result in a higher input clock, but low enough that the UART's
internal divisor can't come close enough to the baud rate target.
So rather than try to set the input clock it's better to skip the
clk_set_rate call and rely solely on the UART's internal divisor.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Link: https://lore.kernel.org/r/20211116150119.2171-15-kernel@esmil.dk
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Emil Renner Berthing 2021-11-16 16:01:17 +01:00 committed by Greg Kroah-Hartman
parent c668d56764
commit 57dcb6ec85
1 changed files with 3 additions and 0 deletions
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3
drivers/tty/serial/8250/8250_dw.c
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@ -414,6 +414,8 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
if (of_device_is_compatible(np, "marvell,armada-38x-uart")) if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
p->serial_out = dw8250_serial_out38x; p->serial_out = dw8250_serial_out38x;
if (of_device_is_compatible(np, "starfive,jh7100-uart"))
p->set_termios = dw8250_do_set_termios;
} else if (acpi_dev_present("APMC0D08", NULL, -1)) { } else if (acpi_dev_present("APMC0D08", NULL, -1)) {
p->iotype = UPIO_MEM32; p->iotype = UPIO_MEM32;
@ -696,6 +698,7 @@ static const struct of_device_id dw8250_of_match[] = {
{ .compatible = "cavium,octeon-3860-uart" }, { .compatible = "cavium,octeon-3860-uart" },
{ .compatible = "marvell,armada-38x-uart" }, { .compatible = "marvell,armada-38x-uart" },
{ .compatible = "renesas,rzn1-uart" }, { .compatible = "renesas,rzn1-uart" },
{ .compatible = "starfive,jh7100-uart" },
{ /* Sentinel */ } { /* Sentinel */ }
}; };
MODULE_DEVICE_TABLE(of, dw8250_of_match); MODULE_DEVICE_TABLE(of, dw8250_of_match);