[POWERPC] Revise PPC44x MMU code for arch/powerpc
This patch takes the definitions for the PPC44x MMU (a software loaded TLB) from asm-ppc/mmu.h, cleans them up of things no longer necessary in arch/powerpc and puts them in a new asm-powerpc/mmu_44x.h file. It also substantially simplifies arch/powerpc/mm/44x_mmu.c and makes a couple of small fixes necessary for the 44x MMU code to build and work properly in arch/powerpc. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
David Gibson
Paul Mackerras
parent
c3e8011ad1
commit
57d7909e0d
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@ -120,8 +120,8 @@ skpinv: addi r4,r4,1 /* Increment */
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* Configure and load pinned entry into TLB slot 63.
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*/
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lis r3,KERNELBASE@h /* Load the kernel virtual address */
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ori r3,r3,KERNELBASE@l
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lis r3,PAGE_OFFSET@h
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ori r3,r3,PAGE_OFFSET@l
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/* Kernel is at the base of RAM */
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li r4, 0 /* Load the kernel physical address */
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@ -24,73 +24,38 @@
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*
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*/
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/stddef.h>
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#include <linux/vmalloc.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/highmem.h>
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#include <asm/pgalloc.h>
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#include <asm/prom.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/uaccess.h>
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#include <asm/smp.h>
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#include <asm/bootx.h>
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#include <asm/machdep.h>
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#include <asm/setup.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include "mmu_decl.h"
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extern char etext[], _stext[];
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/* Used by the 44x TLB replacement exception handler.
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* Just needed it declared someplace.
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*/
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unsigned int tlb_44x_index = 0;
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unsigned int tlb_44x_hwater = 62;
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unsigned int tlb_44x_index; /* = 0 */
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unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
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/*
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* "Pins" a 256MB TLB entry in AS0 for kernel lowmem
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*/
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static void __init
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ppc44x_pin_tlb(int slot, unsigned int virt, unsigned int phys)
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static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
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{
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unsigned long attrib = 0;
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__asm__ __volatile__("\
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clrrwi %2,%2,10\n\
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ori %2,%2,%4\n\
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clrrwi %1,%1,10\n\
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li %0,0\n\
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ori %0,%0,%5\n\
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tlbwe %2,%3,%6\n\
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tlbwe %1,%3,%7\n\
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tlbwe %0,%3,%8"
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__asm__ __volatile__(
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"tlbwe %2,%3,%4\n"
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"tlbwe %1,%3,%5\n"
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"tlbwe %0,%3,%6\n"
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:
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: "r" (attrib), "r" (phys), "r" (virt), "r" (slot),
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"i" (PPC44x_TLB_VALID | PPC44x_TLB_256M),
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"i" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
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: "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
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"r" (phys),
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"r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
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"r" (tlb_44x_hwater--), /* slot for this TLB entry */
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"i" (PPC44x_TLB_PAGEID),
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"i" (PPC44x_TLB_XLAT),
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"i" (PPC44x_TLB_ATTRIB));
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}
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/*
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* MMU_init_hw does the chip-specific initialization of the MMU hardware.
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*/
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void __init MMU_init_hw(void)
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{
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flush_instruction_cache();
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@ -98,22 +63,13 @@ void __init MMU_init_hw(void)
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unsigned long __init mmu_mapin_ram(void)
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{
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unsigned int pinned_tlbs = 1;
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int i;
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unsigned long addr;
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/* Determine number of entries necessary to cover lowmem */
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pinned_tlbs = (unsigned int)
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(_ALIGN(total_lowmem, PPC_PIN_SIZE) >> PPC44x_PIN_SHIFT);
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/* Write upper watermark to save location */
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tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs;
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/* If necessary, set additional pinned TLBs */
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if (pinned_tlbs > 1)
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for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) {
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unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC_PIN_SIZE;
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ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr);
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}
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/* Pin in enough TLBs to cover any lowmem not covered by the
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* initial 256M mapping established in head_44x.S */
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for (addr = PPC_PIN_SIZE; addr < total_lowmem;
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addr += PPC_PIN_SIZE)
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ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
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return total_lowmem;
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}
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@ -40,7 +40,8 @@ extern int __map_without_bats;
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extern unsigned long ioremap_base;
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extern unsigned int rtas_data, rtas_size;
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extern PTE *Hash, *Hash_end;
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struct _PTE;
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extern struct _PTE *Hash, *Hash_end;
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extern unsigned long Hash_size, Hash_mask;
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extern unsigned int num_tlbcam_entries;
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@ -0,0 +1,72 @@
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#ifndef _ASM_POWERPC_MMU_44X_H_
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#define _ASM_POWERPC_MMU_44X_H_
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/*
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* PPC440 support
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*/
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#define PPC44x_MMUCR_TID 0x000000ff
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#define PPC44x_MMUCR_STS 0x00010000
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#define PPC44x_TLB_PAGEID 0
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#define PPC44x_TLB_XLAT 1
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#define PPC44x_TLB_ATTRIB 2
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/* Page identification fields */
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#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
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#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
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#define PPC44x_TLB_TS 0x00000100 /* Translation address space */
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#define PPC44x_TLB_1K 0x00000000 /* Page sizes */
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#define PPC44x_TLB_4K 0x00000010
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#define PPC44x_TLB_16K 0x00000020
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#define PPC44x_TLB_64K 0x00000030
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#define PPC44x_TLB_256K 0x00000040
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#define PPC44x_TLB_1M 0x00000050
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#define PPC44x_TLB_16M 0x00000070
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#define PPC44x_TLB_256M 0x00000090
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/* Translation fields */
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#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
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#define PPC44x_TLB_ERPN_MASK 0x0000000f
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/* Storage attribute and access control fields */
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#define PPC44x_TLB_ATTR_MASK 0x0000ff80
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#define PPC44x_TLB_U0 0x00008000 /* User 0 */
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#define PPC44x_TLB_U1 0x00004000 /* User 1 */
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#define PPC44x_TLB_U2 0x00002000 /* User 2 */
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#define PPC44x_TLB_U3 0x00001000 /* User 3 */
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#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
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#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
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#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
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#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
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#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */
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#define PPC44x_TLB_PERM_MASK 0x0000003f
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#define PPC44x_TLB_UX 0x00000020 /* User execution */
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#define PPC44x_TLB_UW 0x00000010 /* User write */
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#define PPC44x_TLB_UR 0x00000008 /* User read */
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#define PPC44x_TLB_SX 0x00000004 /* Super execution */
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#define PPC44x_TLB_SW 0x00000002 /* Super write */
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#define PPC44x_TLB_SR 0x00000001 /* Super read */
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/* Number of TLB entries */
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#define PPC44x_TLB_SIZE 64
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#ifndef __ASSEMBLY__
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typedef unsigned long long phys_addr_t;
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extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
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typedef struct {
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unsigned long id;
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unsigned long vdso_base;
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} mm_context_t;
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#endif /* !__ASSEMBLY__ */
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#define PPC44x_EARLY_TLBS 1
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/* Size of the TLBs used for pinning in lowmem */
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#define PPC_PIN_SIZE (1 << 28) /* 256M */
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#endif /* _ASM_POWERPC_MMU_44X_H_ */
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@ -5,9 +5,12 @@
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#ifdef CONFIG_PPC64
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/* 64-bit classic hash table MMU */
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# include <asm/mmu-hash64.h>
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#elif defined(CONFIG_44x)
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/* 44x-style software loaded TLB */
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# include <asm/mmu-44x.h>
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#else
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/* 32-bit. FIXME: split up the 32-bit MMU types, and revise for
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* arch/powerpc */
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/* Other 32-bit. FIXME: split up the other 32-bit MMU types, and
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* revise for arch/powerpc */
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# include <asm-ppc/mmu.h>
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#endif
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