[POWERPC] 4xx: PLB to PCI-X support
This adds base support code for the 4xx PCI-X bridge. It also provides placeholders for the PCI and PCI-E version but they aren't supported with this patch. The bridges are configured based on device-tree properties. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This commit is contained in:
Benjamin Herrenschmidt
Josh Boyer
parent
0e6140a56f
commit
5738ec6d00
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@ -27,6 +27,9 @@ obj-$(CONFIG_PPC_I8259) += i8259.o
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obj-$(CONFIG_PPC_83xx) += ipic.o
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obj-$(CONFIG_4xx) += uic.o
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obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
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ifeq ($(CONFIG_PCI),y)
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obj-$(CONFIG_4xx) += ppc4xx_pci.o
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endif
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endif
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# Temporary hack until we have migrated to asm-powerpc
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@ -0,0 +1,339 @@
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/*
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* PCI / PCI-X / PCI-Express support for 4xx parts
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*
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* Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <asm/io.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include "ppc4xx_pci.h"
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static int dma_offset_set;
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/* Move that to a useable header */
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extern unsigned long total_memory;
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static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
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void __iomem *reg,
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struct resource *res)
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{
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u64 size;
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const u32 *ranges;
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int rlen;
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int pna = of_n_addr_cells(hose->dn);
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int np = pna + 5;
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/* Default */
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res->start = 0;
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res->end = size = 0x80000000;
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res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
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/* Get dma-ranges property */
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ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
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if (ranges == NULL)
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goto out;
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/* Walk it */
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while ((rlen -= np * 4) >= 0) {
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u32 pci_space = ranges[0];
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u64 pci_addr = of_read_number(ranges + 1, 2);
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u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
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size = of_read_number(ranges + pna + 3, 2);
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ranges += np;
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if (cpu_addr == OF_BAD_ADDR || size == 0)
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continue;
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/* We only care about memory */
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if ((pci_space & 0x03000000) != 0x02000000)
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continue;
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/* We currently only support memory at 0, and pci_addr
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* within 32 bits space
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*/
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if (cpu_addr != 0 || pci_addr > 0xffffffff) {
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printk(KERN_WARNING "%s: Ignored unsupported dma range"
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" 0x%016llx...0x%016llx -> 0x%016llx\n",
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hose->dn->full_name,
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pci_addr, pci_addr + size - 1, cpu_addr);
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continue;
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}
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/* Check if not prefetchable */
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if (!(pci_space & 0x40000000))
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res->flags &= ~IORESOURCE_PREFETCH;
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/* Use that */
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res->start = pci_addr;
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#ifndef CONFIG_RESOURCES_64BIT
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/* Beware of 32 bits resources */
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if ((pci_addr + size) > 0x100000000ull)
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res->end = 0xffffffff;
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else
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#endif
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res->end = res->start + size - 1;
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break;
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}
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/* We only support one global DMA offset */
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if (dma_offset_set && pci_dram_offset != res->start) {
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printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
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hose->dn->full_name);
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return -ENXIO;
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}
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/* Check that we can fit all of memory as we don't support
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* DMA bounce buffers
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*/
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if (size < total_memory) {
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printk(KERN_ERR "%s: dma-ranges too small "
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"(size=%llx total_memory=%lx)\n",
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hose->dn->full_name, size, total_memory);
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return -ENXIO;
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}
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/* Check we are a power of 2 size and that base is a multiple of size*/
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if (!is_power_of_2(size) ||
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(res->start & (size - 1)) != 0) {
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printk(KERN_ERR "%s: dma-ranges unaligned\n",
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hose->dn->full_name);
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return -ENXIO;
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}
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/* Check that we are fully contained within 32 bits space */
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if (res->end > 0xffffffff) {
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printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
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hose->dn->full_name);
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return -ENXIO;
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}
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out:
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dma_offset_set = 1;
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pci_dram_offset = res->start;
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printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
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pci_dram_offset);
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return 0;
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}
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/*
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* 4xx PCI 2.x part
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*/
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static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
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{
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/* NYI */
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}
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/*
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* 4xx PCI-X part
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*/
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static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
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void __iomem *reg)
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{
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u32 lah, lal, pciah, pcial, sa;
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int i, j;
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/* Setup outbound memory windows */
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for (i = j = 0; i < 3; i++) {
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struct resource *res = &hose->mem_resources[i];
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/* we only care about memory windows */
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if (!(res->flags & IORESOURCE_MEM))
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continue;
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if (j > 1) {
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printk(KERN_WARNING "%s: Too many ranges\n",
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hose->dn->full_name);
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break;
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}
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/* Calculate register values */
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#ifdef CONFIG_PTE_64BIT
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lah = res->start >> 32;
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lal = res->start & 0xffffffffu;
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pciah = (res->start - hose->pci_mem_offset) >> 32;
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pcial = (res->start - hose->pci_mem_offset) & 0xffffffffu;
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#else
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lah = pciah = 0;
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lal = res->start;
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pcial = res->start - hose->pci_mem_offset;
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#endif
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sa = res->end + 1 - res->start;
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if (!is_power_of_2(sa) || sa < 0x100000 ||
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sa > 0xffffffffu) {
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printk(KERN_WARNING "%s: Resource out of range\n",
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hose->dn->full_name);
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continue;
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}
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sa = (0xffffffffu << ilog2(sa)) | 0x1;
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/* Program register values */
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if (j == 0) {
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writel(lah, reg + PCIX0_POM0LAH);
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writel(lal, reg + PCIX0_POM0LAL);
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writel(pciah, reg + PCIX0_POM0PCIAH);
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writel(pcial, reg + PCIX0_POM0PCIAL);
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writel(sa, reg + PCIX0_POM0SA);
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} else {
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writel(lah, reg + PCIX0_POM1LAH);
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writel(lal, reg + PCIX0_POM1LAL);
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writel(pciah, reg + PCIX0_POM1PCIAH);
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writel(pcial, reg + PCIX0_POM1PCIAL);
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writel(sa, reg + PCIX0_POM1SA);
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}
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j++;
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}
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}
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static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
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void __iomem *reg,
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const struct resource *res,
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int big_pim,
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int enable_msi_hole)
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{
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resource_size_t size = res->end - res->start + 1;
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u32 sa;
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/* RAM is always at 0 */
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writel(0x00000000, reg + PCIX0_PIM0LAH);
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writel(0x00000000, reg + PCIX0_PIM0LAL);
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/* Calculate window size */
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sa = (0xffffffffu << ilog2(size)) | 1;
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sa |= 0x1;
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if (res->flags & IORESOURCE_PREFETCH)
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sa |= 0x2;
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if (enable_msi_hole)
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sa |= 0x4;
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writel(sa, reg + PCIX0_PIM0SA);
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if (big_pim)
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writel(0xffffffff, reg + PCIX0_PIM0SAH);
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/* Map on PCI side */
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writel(0x00000000, reg + PCIX0_BAR0H);
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writel(res->start, reg + PCIX0_BAR0L);
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writew(0x0006, reg + PCIX0_COMMAND);
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}
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static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
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{
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struct resource rsrc_cfg;
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struct resource rsrc_reg;
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struct resource dma_window;
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struct pci_controller *hose = NULL;
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void __iomem *reg = NULL;
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const int *bus_range;
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int big_pim = 0, msi = 0, primary = 0;
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/* Fetch config space registers address */
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if (of_address_to_resource(np, 0, &rsrc_cfg)) {
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printk(KERN_ERR "%s:Can't get PCI-X config register base !",
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np->full_name);
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return;
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}
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/* Fetch host bridge internal registers address */
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if (of_address_to_resource(np, 3, &rsrc_reg)) {
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printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
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np->full_name);
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return;
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}
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/* Check if it supports large PIMs (440GX) */
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if (of_get_property(np, "large-inbound-windows", NULL))
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big_pim = 1;
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/* Check if we should enable MSIs inbound hole */
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if (of_get_property(np, "enable-msi-hole", NULL))
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msi = 1;
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/* Check if primary bridge */
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if (of_get_property(np, "primary", NULL))
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primary = 1;
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/* Get bus range if any */
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bus_range = of_get_property(np, "bus-range", NULL);
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/* Map registers */
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reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
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if (reg == NULL) {
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printk(KERN_ERR "%s: Can't map registers !", np->full_name);
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goto fail;
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}
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/* Allocate the host controller data structure */
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hose = pcibios_alloc_controller(np);
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if (!hose)
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goto fail;
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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/* Setup config space */
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setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
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/* Disable all windows */
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writel(0, reg + PCIX0_POM0SA);
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writel(0, reg + PCIX0_POM1SA);
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writel(0, reg + PCIX0_POM2SA);
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writel(0, reg + PCIX0_PIM0SA);
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writel(0, reg + PCIX0_PIM1SA);
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writel(0, reg + PCIX0_PIM2SA);
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if (big_pim) {
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writel(0, reg + PCIX0_PIM0SAH);
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writel(0, reg + PCIX0_PIM2SAH);
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}
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/* Parse outbound mapping resources */
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pci_process_bridge_OF_ranges(hose, np, primary);
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/* Parse inbound mapping resources */
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if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
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goto fail;
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/* Configure outbound ranges POMs */
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ppc4xx_configure_pcix_POMs(hose, reg);
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/* Configure inbound ranges PIMs */
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ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
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/* We don't need the registers anymore */
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iounmap(reg);
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return;
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fail:
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if (hose)
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pcibios_free_controller(hose);
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if (reg)
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iounmap(reg);
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}
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/*
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* 4xx PCI-Express part
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*/
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static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
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{
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/* NYI */
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}
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static int __init ppc4xx_pci_find_bridges(void)
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{
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struct device_node *np;
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for_each_compatible_node(np, NULL, "ibm,plb-pciex")
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ppc4xx_probe_pciex_bridge(np);
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for_each_compatible_node(np, NULL, "ibm,plb-pcix")
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ppc4xx_probe_pcix_bridge(np);
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for_each_compatible_node(np, NULL, "ibm,plb-pci")
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ppc4xx_probe_pci_bridge(np);
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return 0;
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}
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arch_initcall(ppc4xx_pci_find_bridges);
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@ -0,0 +1,106 @@
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/*
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* PCI / PCI-X / PCI-Express support for 4xx parts
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*
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* Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
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*
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* Bits and pieces extracted from arch/ppc support by
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*
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* Matt Porter <mporter@kernel.crashing.org>
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*
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* Copyright 2002-2005 MontaVista Software Inc.
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*/
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#ifndef __PPC4XX_PCI_H__
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#define __PPC4XX_PCI_H__
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/*
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* 4xx PCI-X bridge register definitions
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*/
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#define PCIX0_VENDID 0x000
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#define PCIX0_DEVID 0x002
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#define PCIX0_COMMAND 0x004
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#define PCIX0_STATUS 0x006
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#define PCIX0_REVID 0x008
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#define PCIX0_CLS 0x009
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#define PCIX0_CACHELS 0x00c
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#define PCIX0_LATTIM 0x00d
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#define PCIX0_HDTYPE 0x00e
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#define PCIX0_BIST 0x00f
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#define PCIX0_BAR0L 0x010
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#define PCIX0_BAR0H 0x014
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#define PCIX0_BAR1 0x018
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#define PCIX0_BAR2L 0x01c
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#define PCIX0_BAR2H 0x020
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#define PCIX0_BAR3 0x024
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#define PCIX0_CISPTR 0x028
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#define PCIX0_SBSYSVID 0x02c
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#define PCIX0_SBSYSID 0x02e
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#define PCIX0_EROMBA 0x030
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#define PCIX0_CAP 0x034
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#define PCIX0_RES0 0x035
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#define PCIX0_RES1 0x036
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#define PCIX0_RES2 0x038
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#define PCIX0_INTLN 0x03c
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#define PCIX0_INTPN 0x03d
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#define PCIX0_MINGNT 0x03e
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#define PCIX0_MAXLTNCY 0x03f
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#define PCIX0_BRDGOPT1 0x040
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#define PCIX0_BRDGOPT2 0x044
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#define PCIX0_ERREN 0x050
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#define PCIX0_ERRSTS 0x054
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#define PCIX0_PLBBESR 0x058
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#define PCIX0_PLBBEARL 0x05c
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#define PCIX0_PLBBEARH 0x060
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#define PCIX0_POM0LAL 0x068
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#define PCIX0_POM0LAH 0x06c
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#define PCIX0_POM0SA 0x070
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#define PCIX0_POM0PCIAL 0x074
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#define PCIX0_POM0PCIAH 0x078
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#define PCIX0_POM1LAL 0x07c
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#define PCIX0_POM1LAH 0x080
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#define PCIX0_POM1SA 0x084
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#define PCIX0_POM1PCIAL 0x088
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#define PCIX0_POM1PCIAH 0x08c
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#define PCIX0_POM2SA 0x090
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#define PCIX0_PIM0SAL 0x098
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#define PCIX0_PIM0SA PCIX0_PIM0SAL
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#define PCIX0_PIM0LAL 0x09c
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#define PCIX0_PIM0LAH 0x0a0
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#define PCIX0_PIM1SA 0x0a4
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#define PCIX0_PIM1LAL 0x0a8
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#define PCIX0_PIM1LAH 0x0ac
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#define PCIX0_PIM2SAL 0x0b0
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#define PCIX0_PIM2SA PCIX0_PIM2SAL
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#define PCIX0_PIM2LAL 0x0b4
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#define PCIX0_PIM2LAH 0x0b8
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#define PCIX0_OMCAPID 0x0c0
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#define PCIX0_OMNIPTR 0x0c1
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#define PCIX0_OMMC 0x0c2
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#define PCIX0_OMMA 0x0c4
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#define PCIX0_OMMUA 0x0c8
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#define PCIX0_OMMDATA 0x0cc
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#define PCIX0_OMMEOI 0x0ce
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#define PCIX0_PMCAPID 0x0d0
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#define PCIX0_PMNIPTR 0x0d1
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#define PCIX0_PMC 0x0d2
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#define PCIX0_PMCSR 0x0d4
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#define PCIX0_PMCSRBSE 0x0d6
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#define PCIX0_PMDATA 0x0d7
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#define PCIX0_PMSCRR 0x0d8
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#define PCIX0_CAPID 0x0dc
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#define PCIX0_NIPTR 0x0dd
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#define PCIX0_CMD 0x0de
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#define PCIX0_STS 0x0e0
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#define PCIX0_IDR 0x0e4
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#define PCIX0_CID 0x0e8
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#define PCIX0_RID 0x0ec
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#define PCIX0_PIM0SAH 0x0f8
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#define PCIX0_PIM2SAH 0x0fc
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||||
#define PCIX0_MSGIL 0x100
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||||
#define PCIX0_MSGIH 0x104
|
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#define PCIX0_MSGOL 0x108
|
||||
#define PCIX0_MSGOH 0x10c
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||||
#define PCIX0_IM 0x1f8
|
||||
|
||||
|
||||
|
||||
#endif /* __PPC4XX_PCI_H__ */
|
||||
Loading…
Reference in New Issue