drm/i915/gem: Zap the client blt code
It's not used anywhere. Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210617063018.92802-12-thomas.hellstrom@linux.intel.com
This commit is contained in:
parent
50331a7b50
commit
57143f2e5b
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@ -136,7 +136,6 @@ i915-y += $(gt-y)
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gem-y += \
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gem/i915_gem_busy.o \
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gem/i915_gem_clflush.o \
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gem/i915_gem_client_blt.o \
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gem/i915_gem_context.o \
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gem/i915_gem_create.o \
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gem/i915_gem_dmabuf.o \
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@ -281,6 +280,7 @@ i915-y += i915_perf.o
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# Post-mortem debug and GPU hang state capture
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i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
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i915-$(CONFIG_DRM_I915_SELFTEST) += \
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gem/selftests/i915_gem_client_blt.o \
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gem/selftests/igt_gem_utils.o \
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selftests/i915_random.o \
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selftests/i915_selftest.o \
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@ -1,355 +0,0 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "gt/intel_context.h"
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#include "gt/intel_engine_pm.h"
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#include "i915_gem_client_blt.h"
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#include "i915_gem_object_blt.h"
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struct i915_sleeve {
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struct i915_vma *vma;
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struct drm_i915_gem_object *obj;
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struct sg_table *pages;
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struct i915_page_sizes page_sizes;
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};
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static int vma_set_pages(struct i915_vma *vma)
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{
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struct i915_sleeve *sleeve = vma->private;
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vma->pages = sleeve->pages;
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vma->page_sizes = sleeve->page_sizes;
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return 0;
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}
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static void vma_clear_pages(struct i915_vma *vma)
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{
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GEM_BUG_ON(!vma->pages);
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vma->pages = NULL;
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}
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static void vma_bind(struct i915_address_space *vm,
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struct i915_vm_pt_stash *stash,
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struct i915_vma *vma,
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enum i915_cache_level cache_level,
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u32 flags)
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{
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vm->vma_ops.bind_vma(vm, stash, vma, cache_level, flags);
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}
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static void vma_unbind(struct i915_address_space *vm, struct i915_vma *vma)
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{
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vm->vma_ops.unbind_vma(vm, vma);
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}
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static const struct i915_vma_ops proxy_vma_ops = {
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.set_pages = vma_set_pages,
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.clear_pages = vma_clear_pages,
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.bind_vma = vma_bind,
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.unbind_vma = vma_unbind,
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};
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static struct i915_sleeve *create_sleeve(struct i915_address_space *vm,
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struct drm_i915_gem_object *obj,
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struct sg_table *pages,
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struct i915_page_sizes *page_sizes)
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{
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struct i915_sleeve *sleeve;
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struct i915_vma *vma;
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int err;
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sleeve = kzalloc(sizeof(*sleeve), GFP_KERNEL);
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if (!sleeve)
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return ERR_PTR(-ENOMEM);
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vma = i915_vma_instance(obj, vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err_free;
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}
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vma->private = sleeve;
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vma->ops = &proxy_vma_ops;
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sleeve->vma = vma;
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sleeve->pages = pages;
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sleeve->page_sizes = *page_sizes;
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return sleeve;
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err_free:
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kfree(sleeve);
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return ERR_PTR(err);
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}
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static void destroy_sleeve(struct i915_sleeve *sleeve)
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{
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kfree(sleeve);
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}
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struct clear_pages_work {
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struct dma_fence dma;
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struct dma_fence_cb cb;
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struct i915_sw_fence wait;
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struct work_struct work;
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struct irq_work irq_work;
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struct i915_sleeve *sleeve;
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struct intel_context *ce;
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u32 value;
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};
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static const char *clear_pages_work_driver_name(struct dma_fence *fence)
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{
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return DRIVER_NAME;
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}
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static const char *clear_pages_work_timeline_name(struct dma_fence *fence)
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{
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return "clear";
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}
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static void clear_pages_work_release(struct dma_fence *fence)
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{
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struct clear_pages_work *w = container_of(fence, typeof(*w), dma);
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destroy_sleeve(w->sleeve);
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i915_sw_fence_fini(&w->wait);
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BUILD_BUG_ON(offsetof(typeof(*w), dma));
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dma_fence_free(&w->dma);
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}
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static const struct dma_fence_ops clear_pages_work_ops = {
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.get_driver_name = clear_pages_work_driver_name,
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.get_timeline_name = clear_pages_work_timeline_name,
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.release = clear_pages_work_release,
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};
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static void clear_pages_signal_irq_worker(struct irq_work *work)
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{
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struct clear_pages_work *w = container_of(work, typeof(*w), irq_work);
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dma_fence_signal(&w->dma);
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dma_fence_put(&w->dma);
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}
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static void clear_pages_dma_fence_cb(struct dma_fence *fence,
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struct dma_fence_cb *cb)
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{
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struct clear_pages_work *w = container_of(cb, typeof(*w), cb);
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if (fence->error)
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dma_fence_set_error(&w->dma, fence->error);
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/*
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* Push the signalling of the fence into yet another worker to avoid
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* the nightmare locking around the fence spinlock.
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*/
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irq_work_queue(&w->irq_work);
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}
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static void clear_pages_worker(struct work_struct *work)
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{
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struct clear_pages_work *w = container_of(work, typeof(*w), work);
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struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
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struct i915_vma *vma = w->sleeve->vma;
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struct i915_gem_ww_ctx ww;
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struct i915_request *rq;
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struct i915_vma *batch;
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int err = w->dma.error;
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if (unlikely(err))
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goto out_signal;
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if (obj->cache_dirty) {
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if (i915_gem_object_has_struct_page(obj))
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drm_clflush_sg(w->sleeve->pages);
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obj->cache_dirty = false;
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}
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obj->read_domains = I915_GEM_GPU_DOMAINS;
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obj->write_domain = 0;
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i915_gem_ww_ctx_init(&ww, false);
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intel_engine_pm_get(w->ce->engine);
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retry:
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err = intel_context_pin_ww(w->ce, &ww);
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if (err)
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goto out_signal;
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batch = intel_emit_vma_fill_blt(w->ce, vma, &ww, w->value);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_ctx;
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}
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rq = i915_request_create(w->ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto out_batch;
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}
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/* There's no way the fence has signalled */
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if (dma_fence_add_callback(&rq->fence, &w->cb,
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clear_pages_dma_fence_cb))
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GEM_BUG_ON(1);
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err = intel_emit_vma_mark_active(batch, rq);
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if (unlikely(err))
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goto out_request;
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/*
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* w->dma is already exported via (vma|obj)->resv we need only
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* keep track of the GPU activity within this vma/request, and
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* propagate the signal from the request to w->dma.
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*/
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err = __i915_vma_move_to_active(vma, rq);
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if (err)
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goto out_request;
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if (rq->engine->emit_init_breadcrumb) {
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err = rq->engine->emit_init_breadcrumb(rq);
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if (unlikely(err))
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goto out_request;
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}
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err = rq->engine->emit_bb_start(rq,
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batch->node.start, batch->node.size,
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0);
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out_request:
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if (unlikely(err)) {
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i915_request_set_error_once(rq, err);
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err = 0;
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}
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i915_request_add(rq);
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out_batch:
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intel_emit_vma_release(w->ce, batch);
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out_ctx:
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intel_context_unpin(w->ce);
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out_signal:
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if (err == -EDEADLK) {
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err = i915_gem_ww_ctx_backoff(&ww);
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if (!err)
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goto retry;
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}
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i915_gem_ww_ctx_fini(&ww);
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i915_vma_unpin(w->sleeve->vma);
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intel_engine_pm_put(w->ce->engine);
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if (unlikely(err)) {
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dma_fence_set_error(&w->dma, err);
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dma_fence_signal(&w->dma);
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dma_fence_put(&w->dma);
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}
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}
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static int pin_wait_clear_pages_work(struct clear_pages_work *w,
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struct intel_context *ce)
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{
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struct i915_vma *vma = w->sleeve->vma;
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struct i915_gem_ww_ctx ww;
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int err;
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i915_gem_ww_ctx_init(&ww, false);
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retry:
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err = i915_gem_object_lock(vma->obj, &ww);
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if (err)
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goto out;
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err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER);
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if (unlikely(err))
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goto out;
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err = i915_sw_fence_await_reservation(&w->wait,
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vma->obj->base.resv, NULL,
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true, 0, I915_FENCE_GFP);
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if (err)
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goto err_unpin_vma;
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dma_resv_add_excl_fence(vma->obj->base.resv, &w->dma);
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err_unpin_vma:
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if (err)
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i915_vma_unpin(vma);
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out:
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if (err == -EDEADLK) {
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err = i915_gem_ww_ctx_backoff(&ww);
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if (!err)
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goto retry;
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}
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i915_gem_ww_ctx_fini(&ww);
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return err;
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}
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static int __i915_sw_fence_call
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clear_pages_work_notify(struct i915_sw_fence *fence,
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enum i915_sw_fence_notify state)
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{
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struct clear_pages_work *w = container_of(fence, typeof(*w), wait);
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switch (state) {
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case FENCE_COMPLETE:
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schedule_work(&w->work);
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break;
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case FENCE_FREE:
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dma_fence_put(&w->dma);
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break;
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}
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return NOTIFY_DONE;
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}
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static DEFINE_SPINLOCK(fence_lock);
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/* XXX: better name please */
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int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj,
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struct intel_context *ce,
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struct sg_table *pages,
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struct i915_page_sizes *page_sizes,
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u32 value)
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{
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struct clear_pages_work *work;
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struct i915_sleeve *sleeve;
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int err;
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sleeve = create_sleeve(ce->vm, obj, pages, page_sizes);
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if (IS_ERR(sleeve))
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return PTR_ERR(sleeve);
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work = kmalloc(sizeof(*work), GFP_KERNEL);
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if (!work) {
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destroy_sleeve(sleeve);
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return -ENOMEM;
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}
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work->value = value;
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work->sleeve = sleeve;
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work->ce = ce;
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INIT_WORK(&work->work, clear_pages_worker);
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init_irq_work(&work->irq_work, clear_pages_signal_irq_worker);
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dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0);
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i915_sw_fence_init(&work->wait, clear_pages_work_notify);
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err = pin_wait_clear_pages_work(work, ce);
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if (err < 0)
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dma_fence_set_error(&work->dma, err);
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dma_fence_get(&work->dma);
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i915_sw_fence_commit(&work->wait);
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return err;
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}
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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#include "selftests/i915_gem_client_blt.c"
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#endif
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@ -1,21 +0,0 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __I915_GEM_CLIENT_BLT_H__
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#define __I915_GEM_CLIENT_BLT_H__
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#include <linux/types.h>
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struct drm_i915_gem_object;
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struct i915_page_sizes;
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struct intel_context;
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struct sg_table;
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int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj,
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struct intel_context *ce,
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struct sg_table *pages,
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struct i915_page_sizes *page_sizes,
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u32 value);
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#endif
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@ -5,6 +5,7 @@
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#include "i915_selftest.h"
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#include "gt/intel_context.h"
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#include "gt/intel_engine_user.h"
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#include "gt/intel_gt.h"
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#include "gt/intel_gpu_commands.h"
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@ -16,118 +17,6 @@
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#include "huge_gem_object.h"
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#include "mock_context.h"
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static int __igt_client_fill(struct intel_engine_cs *engine)
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{
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struct intel_context *ce = engine->kernel_context;
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struct drm_i915_gem_object *obj;
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I915_RND_STATE(prng);
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IGT_TIMEOUT(end);
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u32 *vaddr;
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int err = 0;
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intel_engine_pm_get(engine);
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do {
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const u32 max_block_size = S16_MAX * PAGE_SIZE;
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u32 sz = min_t(u64, ce->vm->total >> 4, prandom_u32_state(&prng));
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u32 phys_sz = sz % (max_block_size + 1);
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u32 val = prandom_u32_state(&prng);
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u32 i;
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sz = round_up(sz, PAGE_SIZE);
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phys_sz = round_up(phys_sz, PAGE_SIZE);
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pr_debug("%s with phys_sz= %x, sz=%x, val=%x\n", __func__,
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phys_sz, sz, val);
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obj = huge_gem_object(engine->i915, phys_sz, sz);
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if (IS_ERR(obj)) {
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err = PTR_ERR(obj);
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goto err_flush;
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}
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vaddr = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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err = PTR_ERR(vaddr);
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goto err_put;
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}
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/*
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* XXX: The goal is move this to get_pages, so try to dirty the
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* CPU cache first to check that we do the required clflush
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* before scheduling the blt for !llc platforms. This matches
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* some version of reality where at get_pages the pages
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* themselves may not yet be coherent with the GPU(swap-in). If
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* we are missing the flush then we should see the stale cache
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* values after we do the set_to_cpu_domain and pick it up as a
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* test failure.
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*/
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memset32(vaddr, val ^ 0xdeadbeaf,
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huge_gem_object_phys_size(obj) / sizeof(u32));
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if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE))
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obj->cache_dirty = true;
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err = i915_gem_schedule_fill_pages_blt(obj, ce, obj->mm.pages,
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&obj->mm.page_sizes,
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val);
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if (err)
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goto err_unpin;
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i915_gem_object_lock(obj, NULL);
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err = i915_gem_object_set_to_cpu_domain(obj, false);
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i915_gem_object_unlock(obj);
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if (err)
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goto err_unpin;
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for (i = 0; i < huge_gem_object_phys_size(obj) / sizeof(u32); ++i) {
|
||||
if (vaddr[i] != val) {
|
||||
pr_err("vaddr[%u]=%x, expected=%x\n", i,
|
||||
vaddr[i], val);
|
||||
err = -EINVAL;
|
||||
goto err_unpin;
|
||||
}
|
||||
}
|
||||
|
||||
i915_gem_object_unpin_map(obj);
|
||||
i915_gem_object_put(obj);
|
||||
} while (!time_after(jiffies, end));
|
||||
|
||||
goto err_flush;
|
||||
|
||||
err_unpin:
|
||||
i915_gem_object_unpin_map(obj);
|
||||
err_put:
|
||||
i915_gem_object_put(obj);
|
||||
err_flush:
|
||||
if (err == -ENOMEM)
|
||||
err = 0;
|
||||
intel_engine_pm_put(engine);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int igt_client_fill(void *arg)
|
||||
{
|
||||
int inst = 0;
|
||||
|
||||
do {
|
||||
struct intel_engine_cs *engine;
|
||||
int err;
|
||||
|
||||
engine = intel_engine_lookup_user(arg,
|
||||
I915_ENGINE_CLASS_COPY,
|
||||
inst++);
|
||||
if (!engine)
|
||||
return 0;
|
||||
|
||||
err = __igt_client_fill(engine);
|
||||
if (err == -ENOMEM)
|
||||
err = 0;
|
||||
if (err)
|
||||
return err;
|
||||
} while (1);
|
||||
}
|
||||
|
||||
#define WIDTH 512
|
||||
#define HEIGHT 32
|
||||
|
||||
|
@ -693,7 +582,6 @@ static int igt_client_tiled_blits(void *arg)
|
|||
int i915_gem_client_blt_live_selftests(struct drm_i915_private *i915)
|
||||
{
|
||||
static const struct i915_subtest tests[] = {
|
||||
SUBTEST(igt_client_fill),
|
||||
SUBTEST(igt_client_tiled_blits),
|
||||
};
|
||||
|
||||
|
|
Loading…
Reference in New Issue