pinctrl: renesas: Updates for v5.16 (take two)
- Add MediaLB pins on R-Car H3, M3-W/W+, and M3-N. - Miscellaneous fixes and improvements. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYWloXQAKCRCKwlD9ZEnx cHh6AQCmWteue6fSAA99ZF+Hpt+kZf/Jq0PiO4F6sY0vszj1GAEAyWUBsvcT9yYx 8tFd2m9504x0BdT9D/G9vI0e7EX0uQ4= =aNEI -----END PGP SIGNATURE----- Merge tag 'renesas-pinctrl-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.16 (take two) - Add MediaLB pins on R-Car H3, M3-W/W+, and M3-N. - Miscellaneous fixes and improvements.
This commit is contained in:
Linus Walleij
commit
57135c2810
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@ -675,7 +675,9 @@ static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
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do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
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if (pfc->info->bias_regs)
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for (i = 0; pfc->info->bias_regs[i].puen; i++) {
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for (i = 0; pfc->info->bias_regs[i].puen ||
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pfc->info->bias_regs[i].pud; i++) {
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if (pfc->info->bias_regs[i].puen)
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do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
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if (pfc->info->bias_regs[i].pud)
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do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
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@ -743,7 +745,10 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
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static unsigned int sh_pfc_errors __initdata;
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static unsigned int sh_pfc_warnings __initdata;
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static u32 *sh_pfc_regs __initdata;
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static struct {
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u32 reg;
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u32 bits;
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} *sh_pfc_regs __initdata;
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static u32 sh_pfc_num_regs __initdata;
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static u16 *sh_pfc_enums __initdata;
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static u32 sh_pfc_num_enums __initdata;
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@ -778,13 +783,19 @@ static bool __init same_name(const char *a, const char *b)
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return !strcmp(a, b);
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}
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static void __init sh_pfc_check_reg(const char *drvname, u32 reg)
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static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits)
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{
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unsigned int i;
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for (i = 0; i < sh_pfc_num_regs; i++)
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if (reg == sh_pfc_regs[i]) {
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sh_pfc_err("reg 0x%x conflict\n", reg);
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for (i = 0; i < sh_pfc_num_regs; i++) {
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if (reg != sh_pfc_regs[i].reg)
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continue;
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if (bits & sh_pfc_regs[i].bits)
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sh_pfc_err("reg 0x%x: bits 0x%x conflict\n", reg,
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bits & sh_pfc_regs[i].bits);
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sh_pfc_regs[i].bits |= bits;
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return;
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}
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@ -793,7 +804,9 @@ static void __init sh_pfc_check_reg(const char *drvname, u32 reg)
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return;
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}
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sh_pfc_regs[sh_pfc_num_regs++] = reg;
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sh_pfc_regs[sh_pfc_num_regs].reg = reg;
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sh_pfc_regs[sh_pfc_num_regs].bits = bits;
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sh_pfc_num_regs++;
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}
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static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id)
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@ -848,7 +861,8 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname,
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{
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unsigned int i, n, rw, fw;
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sh_pfc_check_reg(drvname, cfg_reg->reg);
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sh_pfc_check_reg(drvname, cfg_reg->reg,
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GENMASK(cfg_reg->reg_width - 1, 0));
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if (cfg_reg->field_width) {
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n = cfg_reg->reg_width / cfg_reg->field_width;
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@ -879,22 +893,17 @@ check_enum_ids:
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static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
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const struct pinmux_drive_reg *drive)
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{
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const char *drvname = info->name;
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unsigned long seen = 0, mask;
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unsigned int i;
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sh_pfc_check_reg(info->name, drive->reg);
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for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
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const struct pinmux_drive_reg_field *field = &drive->fields[i];
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if (!field->pin && !field->offset && !field->size)
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continue;
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mask = GENMASK(field->offset + field->size, field->offset);
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if (mask & seen)
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sh_pfc_err("drive_reg 0x%x: field %u overlap\n",
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drive->reg, i);
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seen |= mask;
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sh_pfc_check_reg(info->name, drive->reg,
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GENMASK(field->offset + field->size - 1,
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field->offset));
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sh_pfc_check_pin(info, drive->reg, field->pin);
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}
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@ -904,21 +913,28 @@ static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
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const struct pinmux_bias_reg *bias)
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{
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unsigned int i;
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u32 bits;
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sh_pfc_check_reg(info->name, bias->puen);
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for (i = 0, bits = 0; i < ARRAY_SIZE(bias->pins); i++)
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if (bias->pins[i] != SH_PFC_PIN_NONE)
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bits |= BIT(i);
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if (bias->puen)
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sh_pfc_check_reg(info->name, bias->puen, bits);
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if (bias->pud)
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sh_pfc_check_reg(info->name, bias->pud);
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sh_pfc_check_reg(info->name, bias->pud, bits);
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for (i = 0; i < ARRAY_SIZE(bias->pins); i++)
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sh_pfc_check_pin(info, bias->puen, bias->pins[i]);
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}
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static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
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{
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const struct pinmux_bias_reg *bias_regs = info->bias_regs;
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const char *drvname = info->name;
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unsigned int *refcnts;
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unsigned int i, j, k;
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pr_info("Checking %s\n", drvname);
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pr_info("sh_pfc: Checking %s\n", drvname);
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sh_pfc_num_regs = 0;
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sh_pfc_num_enums = 0;
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@ -1010,16 +1026,17 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
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sh_pfc_check_drive_reg(info, &info->drive_regs[i]);
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/* Check bias registers */
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for (i = 0; info->bias_regs && info->bias_regs[i].puen; i++)
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sh_pfc_check_bias_reg(info, &info->bias_regs[i]);
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for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)
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sh_pfc_check_bias_reg(info, &bias_regs[i]);
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/* Check ioctrl registers */
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for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
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sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg);
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sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX);
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/* Check data registers */
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for (i = 0; info->data_regs && info->data_regs[i].reg; i++) {
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sh_pfc_check_reg(drvname, info->data_regs[i].reg);
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sh_pfc_check_reg(drvname, info->data_regs[i].reg,
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GENMASK(info->data_regs[i].reg_width - 1, 0));
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sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg,
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info->data_regs[i].enum_ids,
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info->data_regs[i].reg_width);
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@ -1064,7 +1081,7 @@ static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
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if (!sh_pfc_enums)
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goto free_regs;
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pr_warn("Checking builtin pinmux tables\n");
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pr_warn("sh_pfc: Checking builtin pinmux tables\n");
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for (i = 0; pdrv->id_table[i].name[0]; i++)
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sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
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@ -1074,7 +1091,7 @@ static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
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sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
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#endif
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pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
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pr_warn("sh_pfc: Detected %u errors and %u warnings\n", sh_pfc_errors,
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sh_pfc_warnings);
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kfree(sh_pfc_enums);
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@ -2369,6 +2369,14 @@ static const unsigned int intc_ex_irq5_mux[] = {
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IRQ5_MARK,
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};
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/* - MLB+ ------------------------------------------------------------------- */
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static const unsigned int mlb_3pin_pins[] = {
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RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
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};
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static const unsigned int mlb_3pin_mux[] = {
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MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
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};
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/* - MSIOF0 ----------------------------------------------------------------- */
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static const unsigned int msiof0_clk_pins[] = {
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/* SCK */
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@ -3987,6 +3995,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(intc_ex_irq3),
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SH_PFC_PIN_GROUP(intc_ex_irq4),
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SH_PFC_PIN_GROUP(intc_ex_irq5),
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SH_PFC_PIN_GROUP(mlb_3pin),
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SH_PFC_PIN_GROUP(msiof0_clk),
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SH_PFC_PIN_GROUP(msiof0_sync),
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SH_PFC_PIN_GROUP(msiof0_ss1),
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@ -4380,6 +4389,10 @@ static const char * const intc_ex_groups[] = {
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"intc_ex_irq5",
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};
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static const char * const mlb_3pin_groups[] = {
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"mlb_3pin",
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};
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static const char * const msiof0_groups[] = {
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"msiof0_clk",
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"msiof0_sync",
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@ -4709,6 +4722,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(i2c5),
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SH_PFC_FUNCTION(i2c6),
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SH_PFC_FUNCTION(intc_ex),
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SH_PFC_FUNCTION(mlb_3pin),
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SH_PFC_FUNCTION(msiof0),
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SH_PFC_FUNCTION(msiof1),
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SH_PFC_FUNCTION(msiof2),
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@ -2453,6 +2453,16 @@ static const unsigned int intc_ex_irq5_mux[] = {
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IRQ5_MARK,
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};
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#ifdef CONFIG_PINCTRL_PFC_R8A77951
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/* - MLB+ ------------------------------------------------------------------- */
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static const unsigned int mlb_3pin_pins[] = {
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RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
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};
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static const unsigned int mlb_3pin_mux[] = {
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MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
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};
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#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
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/* - MSIOF0 ----------------------------------------------------------------- */
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static const unsigned int msiof0_clk_pins[] = {
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/* SCK */
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@ -4235,7 +4245,7 @@ static const unsigned int vin5_clk_mux[] = {
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static const struct {
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struct sh_pfc_pin_group common[328];
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#ifdef CONFIG_PINCTRL_PFC_R8A77951
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struct sh_pfc_pin_group automotive[30];
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struct sh_pfc_pin_group automotive[31];
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#endif
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} pinmux_groups = {
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.common = {
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@ -4600,6 +4610,7 @@ static const struct {
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SH_PFC_PIN_GROUP(drif3_ctrl_b),
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SH_PFC_PIN_GROUP(drif3_data0_b),
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SH_PFC_PIN_GROUP(drif3_data1_b),
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SH_PFC_PIN_GROUP(mlb_3pin),
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}
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#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
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};
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@ -4795,6 +4806,12 @@ static const char * const intc_ex_groups[] = {
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"intc_ex_irq5",
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};
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#ifdef CONFIG_PINCTRL_PFC_R8A77951
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static const char * const mlb_3pin_groups[] = {
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"mlb_3pin",
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};
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#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
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static const char * const msiof0_groups[] = {
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"msiof0_clk",
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"msiof0_sync",
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@ -5144,7 +5161,7 @@ static const char * const vin5_groups[] = {
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static const struct {
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struct sh_pfc_function common[55];
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#ifdef CONFIG_PINCTRL_PFC_R8A77951
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struct sh_pfc_function automotive[4];
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struct sh_pfc_function automotive[5];
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#endif
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} pinmux_functions = {
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.common = {
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@ -5210,6 +5227,7 @@ static const struct {
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SH_PFC_FUNCTION(drif1),
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SH_PFC_FUNCTION(drif2),
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SH_PFC_FUNCTION(drif3),
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SH_PFC_FUNCTION(mlb_3pin),
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}
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#endif /* CONFIG_PINCTRL_PFC_R8A77951 */
|
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};
|
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|
|
|
|||
|
|
@ -2458,6 +2458,16 @@ static const unsigned int intc_ex_irq5_mux[] = {
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IRQ5_MARK,
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};
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#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
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/* - MLB+ ------------------------------------------------------------------- */
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static const unsigned int mlb_3pin_pins[] = {
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RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
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};
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static const unsigned int mlb_3pin_mux[] = {
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MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
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};
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#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
|
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|
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/* - MSIOF0 ----------------------------------------------------------------- */
|
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static const unsigned int msiof0_clk_pins[] = {
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/* SCK */
|
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|
|
@ -4210,7 +4220,7 @@ static const unsigned int vin5_clk_mux[] = {
|
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static const struct {
|
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struct sh_pfc_pin_group common[324];
|
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#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
|
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struct sh_pfc_pin_group automotive[30];
|
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struct sh_pfc_pin_group automotive[31];
|
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#endif
|
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} pinmux_groups = {
|
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.common = {
|
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|
|
@ -4571,6 +4581,7 @@ static const struct {
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SH_PFC_PIN_GROUP(drif3_ctrl_b),
|
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SH_PFC_PIN_GROUP(drif3_data0_b),
|
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SH_PFC_PIN_GROUP(drif3_data1_b),
|
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SH_PFC_PIN_GROUP(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
|
||||
};
|
||||
|
|
@ -4766,6 +4777,12 @@ static const char * const intc_ex_groups[] = {
|
|||
"intc_ex_irq5",
|
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};
|
||||
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
|
||||
static const char * const mlb_3pin_groups[] = {
|
||||
"mlb_3pin",
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
"msiof0_clk",
|
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"msiof0_sync",
|
||||
|
|
@ -5102,7 +5119,7 @@ static const char * const vin5_groups[] = {
|
|||
static const struct {
|
||||
struct sh_pfc_function common[52];
|
||||
#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
|
||||
struct sh_pfc_function automotive[4];
|
||||
struct sh_pfc_function automotive[5];
|
||||
#endif
|
||||
} pinmux_functions = {
|
||||
.common = {
|
||||
|
|
@ -5165,6 +5182,7 @@ static const struct {
|
|||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2609,6 +2609,16 @@ static const unsigned int intc_ex_irq5_mux[] = {
|
|||
IRQ5_MARK,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
/* - MLB+ ------------------------------------------------------------------- */
|
||||
static const unsigned int mlb_3pin_pins[] = {
|
||||
RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
|
||||
};
|
||||
static const unsigned int mlb_3pin_mux[] = {
|
||||
MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
|
||||
|
||||
/* - MSIOF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof0_clk_pins[] = {
|
||||
/* SCK */
|
||||
|
|
@ -4460,7 +4470,7 @@ static const unsigned int vin5_clk_mux[] = {
|
|||
static const struct {
|
||||
struct sh_pfc_pin_group common[326];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
struct sh_pfc_pin_group automotive[30];
|
||||
struct sh_pfc_pin_group automotive[31];
|
||||
#endif
|
||||
} pinmux_groups = {
|
||||
.common = {
|
||||
|
|
@ -4823,6 +4833,7 @@ static const struct {
|
|||
SH_PFC_PIN_GROUP(drif3_ctrl_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data0_b),
|
||||
SH_PFC_PIN_GROUP(drif3_data1_b),
|
||||
SH_PFC_PIN_GROUP(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
|
||||
};
|
||||
|
|
@ -5018,6 +5029,12 @@ static const char * const intc_ex_groups[] = {
|
|||
"intc_ex_irq5",
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
static const char * const mlb_3pin_groups[] = {
|
||||
"mlb_3pin",
|
||||
};
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
"msiof0_clk",
|
||||
"msiof0_sync",
|
||||
|
|
@ -5358,7 +5375,7 @@ static const char * const vin5_groups[] = {
|
|||
static const struct {
|
||||
struct sh_pfc_function common[53];
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
struct sh_pfc_function automotive[4];
|
||||
struct sh_pfc_function automotive[5];
|
||||
#endif
|
||||
} pinmux_functions = {
|
||||
.common = {
|
||||
|
|
@ -5422,6 +5439,7 @@ static const struct {
|
|||
SH_PFC_FUNCTION(drif1),
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(mlb_3pin),
|
||||
}
|
||||
#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue