From ce34fb3cb4a8165a51a90d0ea437d75f34a6d031 Mon Sep 17 00:00:00 2001 From: Andrey Gusakov Date: Thu, 7 Oct 2021 23:02:50 +0300 Subject: [PATCH 1/6] pinctrl: renesas: r8a779[56]x: Add MediaLB pins This adds pins, groups, and functions for MediaLB devices on Renesas R-Car H3 and M3-W/N SoCs. Signed-off-by: Andrey Gusakov Signed-off-by: Vladimir Barinov Signed-off-by: LUU HOAI Signed-off-by: Nikita Yushchenko Link: https://lore.kernel.org/r/20211007200250.20661-1-nikita.yoush@cogentembedded.com [geert: Fix automotive handling] Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pfc-r8a77950.c | 14 ++++++++++++++ drivers/pinctrl/renesas/pfc-r8a77951.c | 22 ++++++++++++++++++++-- drivers/pinctrl/renesas/pfc-r8a7796.c | 22 ++++++++++++++++++++-- drivers/pinctrl/renesas/pfc-r8a77965.c | 22 ++++++++++++++++++++-- 4 files changed, 74 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c index ee4ce9349aae..c86064900c6e 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77950.c +++ b/drivers/pinctrl/renesas/pfc-r8a77950.c @@ -2369,6 +2369,14 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3987,6 +3995,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), + SH_PFC_PIN_GROUP(mlb_3pin), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -4380,6 +4389,10 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4709,6 +4722,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(mlb_3pin), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index 84c0ea5d59c1..ee9ce5f8eb86 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -2453,6 +2453,16 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77951 +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -4235,7 +4245,7 @@ static const unsigned int vin5_clk_mux[] = { static const struct { struct sh_pfc_pin_group common[328]; #ifdef CONFIG_PINCTRL_PFC_R8A77951 - struct sh_pfc_pin_group automotive[30]; + struct sh_pfc_pin_group automotive[31]; #endif } pinmux_groups = { .common = { @@ -4600,6 +4610,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ }; @@ -4795,6 +4806,12 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77951 +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5144,7 +5161,7 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[55]; #ifdef CONFIG_PINCTRL_PFC_R8A77951 - struct sh_pfc_function automotive[4]; + struct sh_pfc_function automotive[5]; #endif } pinmux_functions = { .common = { @@ -5210,6 +5227,7 @@ static const struct { SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77951 */ }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index a4d74df3d201..de3df502f971 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -2458,6 +2458,16 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -4210,7 +4220,7 @@ static const unsigned int vin5_clk_mux[] = { static const struct { struct sh_pfc_pin_group common[324]; #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) - struct sh_pfc_pin_group automotive[30]; + struct sh_pfc_pin_group automotive[31]; #endif } pinmux_groups = { .common = { @@ -4571,6 +4581,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ }; @@ -4766,6 +4777,12 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5102,7 +5119,7 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[52]; #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) - struct sh_pfc_function automotive[4]; + struct sh_pfc_function automotive[5]; #endif } pinmux_functions = { .common = { @@ -5165,6 +5182,7 @@ static const struct { SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ }; diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index a7607a679886..268129f82929 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -2609,6 +2609,16 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -4460,7 +4470,7 @@ static const unsigned int vin5_clk_mux[] = { static const struct { struct sh_pfc_pin_group common[326]; #ifdef CONFIG_PINCTRL_PFC_R8A77965 - struct sh_pfc_pin_group automotive[30]; + struct sh_pfc_pin_group automotive[31]; #endif } pinmux_groups = { .common = { @@ -4823,6 +4833,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ }; @@ -5018,6 +5029,12 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5358,7 +5375,7 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[53]; #ifdef CONFIG_PINCTRL_PFC_R8A77965 - struct sh_pfc_function automotive[4]; + struct sh_pfc_function automotive[5]; #endif } pinmux_functions = { .common = { @@ -5422,6 +5439,7 @@ static const struct { SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ }; From 412da8c7224af6888ed8b2a94ee16bb34a4200a6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 Oct 2021 16:38:46 +0200 Subject: [PATCH 2/6] pinctrl: renesas: Fix save/restore on SoCs with pull-down only pins If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be saved/restored during PSCI system suspend. Fortunately this does not trigger on any supported system yet, as PSCI is only used on R-Car Gen3 and RZ/G2 systems, which all have separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers. Avoid this ever becoming a problem by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Note that a register controlling both pull-up and pull-down pins would be saved and restored twice, which is harmless. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/59d2fbddff685b6a7a82ff17d2b37633e30e8860.1633615652.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index ef8ef05ba930..b0d6103d012e 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -675,8 +675,10 @@ static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc, do_reg(pfc, pfc->info->drive_regs[i].reg, n++); if (pfc->info->bias_regs) - for (i = 0; pfc->info->bias_regs[i].puen; i++) { - do_reg(pfc, pfc->info->bias_regs[i].puen, n++); + for (i = 0; pfc->info->bias_regs[i].puen || + pfc->info->bias_regs[i].pud; i++) { + if (pfc->info->bias_regs[i].puen) + do_reg(pfc, pfc->info->bias_regs[i].puen, n++); if (pfc->info->bias_regs[i].pud) do_reg(pfc, pfc->info->bias_regs[i].pud, n++); } From 28e7f8ff90583791a034d43b5d2e3fe394142e13 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 Oct 2021 16:38:47 +0200 Subject: [PATCH 3/6] pinctrl: renesas: checker: Fix off-by-one bug in drive register check The GENMASK(h, l) macro creates a contiguous bitmask starting at bit position @l and ending at position @h, inclusive. This did not trigger any error checks, as the individual register fields cover at most 3 of the 4 available bits. Fixes: 08df16e07ad0a1ec ("pinctrl: sh-pfc: checker: Add drive strength register checks") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/8f82d6147fbe3367d4c83962480e97f58d9c96a2.1633615652.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index b0d6103d012e..464d07ead568 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -892,7 +892,7 @@ static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info, if (!field->pin && !field->offset && !field->size) continue; - mask = GENMASK(field->offset + field->size, field->offset); + mask = GENMASK(field->offset + field->size - 1, field->offset); if (mask & seen) sh_pfc_err("drive_reg 0x%x: field %u overlap\n", drive->reg, i); From e212923e74076f423555947eff6f14355487cd21 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 Oct 2021 16:38:48 +0200 Subject: [PATCH 4/6] pinctrl: renesas: checker: Move overlapping field check Move the check for overlapping drive register fields from sh_pfc_check_drive_reg() to sh_pfc_check_reg(), so it can be used for other register types, too. This requires passing the covered register bits to sh_pfc_check_reg(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/9d75057200890bbf31e226ffcc4514ecc5bc2c34.1633615652.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/core.c | 55 +++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 464d07ead568..ab8bdb81e8df 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -745,7 +745,10 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } static unsigned int sh_pfc_errors __initdata; static unsigned int sh_pfc_warnings __initdata; -static u32 *sh_pfc_regs __initdata; +static struct { + u32 reg; + u32 bits; +} *sh_pfc_regs __initdata; static u32 sh_pfc_num_regs __initdata; static u16 *sh_pfc_enums __initdata; static u32 sh_pfc_num_enums __initdata; @@ -780,22 +783,30 @@ static bool __init same_name(const char *a, const char *b) return !strcmp(a, b); } -static void __init sh_pfc_check_reg(const char *drvname, u32 reg) +static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits) { unsigned int i; - for (i = 0; i < sh_pfc_num_regs; i++) - if (reg == sh_pfc_regs[i]) { - sh_pfc_err("reg 0x%x conflict\n", reg); - return; - } + for (i = 0; i < sh_pfc_num_regs; i++) { + if (reg != sh_pfc_regs[i].reg) + continue; + + if (bits & sh_pfc_regs[i].bits) + sh_pfc_err("reg 0x%x: bits 0x%x conflict\n", reg, + bits & sh_pfc_regs[i].bits); + + sh_pfc_regs[i].bits |= bits; + return; + } if (sh_pfc_num_regs == SH_PFC_MAX_REGS) { pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname); return; } - sh_pfc_regs[sh_pfc_num_regs++] = reg; + sh_pfc_regs[sh_pfc_num_regs].reg = reg; + sh_pfc_regs[sh_pfc_num_regs].bits = bits; + sh_pfc_num_regs++; } static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id) @@ -850,7 +861,8 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname, { unsigned int i, n, rw, fw; - sh_pfc_check_reg(drvname, cfg_reg->reg); + sh_pfc_check_reg(drvname, cfg_reg->reg, + GENMASK(cfg_reg->reg_width - 1, 0)); if (cfg_reg->field_width) { n = cfg_reg->reg_width / cfg_reg->field_width; @@ -881,22 +893,17 @@ check_enum_ids: static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info, const struct pinmux_drive_reg *drive) { - const char *drvname = info->name; - unsigned long seen = 0, mask; unsigned int i; - sh_pfc_check_reg(info->name, drive->reg); for (i = 0; i < ARRAY_SIZE(drive->fields); i++) { const struct pinmux_drive_reg_field *field = &drive->fields[i]; if (!field->pin && !field->offset && !field->size) continue; - mask = GENMASK(field->offset + field->size - 1, field->offset); - if (mask & seen) - sh_pfc_err("drive_reg 0x%x: field %u overlap\n", - drive->reg, i); - seen |= mask; + sh_pfc_check_reg(info->name, drive->reg, + GENMASK(field->offset + field->size - 1, + field->offset)); sh_pfc_check_pin(info, drive->reg, field->pin); } @@ -906,10 +913,15 @@ static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, const struct pinmux_bias_reg *bias) { unsigned int i; + u32 bits; - sh_pfc_check_reg(info->name, bias->puen); + for (i = 0, bits = 0; i < ARRAY_SIZE(bias->pins); i++) + if (bias->pins[i] != SH_PFC_PIN_NONE) + bits |= BIT(i); + + sh_pfc_check_reg(info->name, bias->puen, bits); if (bias->pud) - sh_pfc_check_reg(info->name, bias->pud); + sh_pfc_check_reg(info->name, bias->pud, bits); for (i = 0; i < ARRAY_SIZE(bias->pins); i++) sh_pfc_check_pin(info, bias->puen, bias->pins[i]); } @@ -1017,11 +1029,12 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) /* Check ioctrl registers */ for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++) - sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg); + sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX); /* Check data registers */ for (i = 0; info->data_regs && info->data_regs[i].reg; i++) { - sh_pfc_check_reg(drvname, info->data_regs[i].reg); + sh_pfc_check_reg(drvname, info->data_regs[i].reg, + GENMASK(info->data_regs[i].reg_width - 1, 0)); sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg, info->data_regs[i].enum_ids, info->data_regs[i].reg_width); From f31a5ffbd11d9886093a6531e5a6d60e0605ce30 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 Oct 2021 16:38:49 +0200 Subject: [PATCH 5/6] pinctrl: renesas: checker: Fix bias checks on SoCs with pull-down only pins If some bits in a pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up, there are two pinmux_bias_reg entries: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. On encountering the second entry, where puen is NULL, the for-loop terminates early, causing the remaining bias registers not to be checked. In addition, sh_pfc_check_bias_reg() does not handle such entries. Fix this by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the same. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/29526d06fa223cffd785cdb264b756a202b11cea.1633615652.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/core.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index ab8bdb81e8df..9d791a5a5f95 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -919,7 +919,8 @@ static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, if (bias->pins[i] != SH_PFC_PIN_NONE) bits |= BIT(i); - sh_pfc_check_reg(info->name, bias->puen, bits); + if (bias->puen) + sh_pfc_check_reg(info->name, bias->puen, bits); if (bias->pud) sh_pfc_check_reg(info->name, bias->pud, bits); for (i = 0; i < ARRAY_SIZE(bias->pins); i++) @@ -928,6 +929,7 @@ static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) { + const struct pinmux_bias_reg *bias_regs = info->bias_regs; const char *drvname = info->name; unsigned int *refcnts; unsigned int i, j, k; @@ -1024,8 +1026,8 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) sh_pfc_check_drive_reg(info, &info->drive_regs[i]); /* Check bias registers */ - for (i = 0; info->bias_regs && info->bias_regs[i].puen; i++) - sh_pfc_check_bias_reg(info, &info->bias_regs[i]); + for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++) + sh_pfc_check_bias_reg(info, &bias_regs[i]); /* Check ioctrl registers */ for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++) From f4e260bffcf367523b77f936fe0dbd278581305e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 Oct 2021 16:38:50 +0200 Subject: [PATCH 6/6] pinctrl: renesas: checker: Prefix common checker output Add a "sh_pfc: " prefix to common checker output that is not yet prefixed by a subdriver-specific prefix ("_pfc: "), for easier grepping. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/9cf1dc9f895dc5fa74125dabddfe46fecf438b4f.1633615652.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 9d791a5a5f95..0d4ea2e22a53 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -934,7 +934,7 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) unsigned int *refcnts; unsigned int i, j, k; - pr_info("Checking %s\n", drvname); + pr_info("sh_pfc: Checking %s\n", drvname); sh_pfc_num_regs = 0; sh_pfc_num_enums = 0; @@ -1081,7 +1081,7 @@ static void __init sh_pfc_check_driver(const struct platform_driver *pdrv) if (!sh_pfc_enums) goto free_regs; - pr_warn("Checking builtin pinmux tables\n"); + pr_warn("sh_pfc: Checking builtin pinmux tables\n"); for (i = 0; pdrv->id_table[i].name[0]; i++) sh_pfc_check_info((void *)pdrv->id_table[i].driver_data); @@ -1091,7 +1091,7 @@ static void __init sh_pfc_check_driver(const struct platform_driver *pdrv) sh_pfc_check_info(pdrv->driver.of_match_table[i].data); #endif - pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors, + pr_warn("sh_pfc: Detected %u errors and %u warnings\n", sh_pfc_errors, sh_pfc_warnings); kfree(sh_pfc_enums);