drm/amd/display: HP Reverb G2 VR fails to light up

[Why]
Many VR headsets require a HSYNC width of 4, but DCN
has default minimum of 8.

[How]
Change the arbitrary minimum HSYNC width to 4 to match
DCN20.

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aric Cyr 2020-12-01 11:25:50 -05:00 committed by Alex Deucher
parent 41aa4d3ded
commit 570b302ba1
3 changed files with 3 additions and 3 deletions

View File

@ -1268,7 +1268,7 @@ void dce120_timing_generator_construct(
tg110->min_h_front_porch = 0;
tg110->min_h_back_porch = 0;
tg110->min_h_sync_width = 8;
tg110->min_h_sync_width = 4;
tg110->min_v_sync_width = 1;
tg110->min_v_blank = 3;
}

View File

@ -1540,7 +1540,7 @@ void dcn10_timing_generator_init(struct optc *optc1)
optc1->min_h_blank = 32;
optc1->min_v_blank = 3;
optc1->min_v_blank_interlace = 5;
optc1->min_h_sync_width = 8;
optc1->min_h_sync_width = 4;
optc1->min_v_sync_width = 1;
}

View File

@ -350,7 +350,7 @@ void dcn30_timing_generator_init(struct optc *optc1)
optc1->min_h_blank = 32;
optc1->min_v_blank = 3;
optc1->min_v_blank_interlace = 5;
optc1->min_h_sync_width = 8;
optc1->min_h_sync_width = 4;
optc1->min_v_sync_width = 1;
}