iwlagn: move ucode_write_complete from priv to trans structure
ucode_write_complete is used for ucode loading. Move it as part of restructuring work out of the priv structure. Signed-off-by: Don Fry <donald.h.fry@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -75,48 +75,49 @@ static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
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/*
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/*
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* ucode
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* ucode
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*/
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*/
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static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
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static int iwlagn_load_section(struct iwl_trans *trans, const char *name,
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struct fw_desc *image, u32 dst_addr)
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struct fw_desc *image, u32 dst_addr)
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{
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{
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struct iwl_bus *bus = bus(trans);
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dma_addr_t phy_addr = image->p_addr;
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dma_addr_t phy_addr = image->p_addr;
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u32 byte_cnt = image->len;
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u32 byte_cnt = image->len;
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int ret;
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int ret;
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priv->ucode_write_complete = 0;
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trans->ucode_write_complete = 0;
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iwl_write_direct32(bus(priv),
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iwl_write_direct32(bus,
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FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
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iwl_write_direct32(bus(priv),
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iwl_write_direct32(bus,
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FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
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FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
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iwl_write_direct32(bus(priv),
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iwl_write_direct32(bus,
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FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
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FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
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phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
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phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
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iwl_write_direct32(bus(priv),
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iwl_write_direct32(bus,
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FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
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FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
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(iwl_get_dma_hi_addr(phy_addr)
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(iwl_get_dma_hi_addr(phy_addr)
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<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
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<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
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iwl_write_direct32(bus(priv),
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iwl_write_direct32(bus,
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FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
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FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
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1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
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1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
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1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
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1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
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FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
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FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
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iwl_write_direct32(bus(priv),
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iwl_write_direct32(bus,
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FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
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FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
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IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
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IWL_DEBUG_FW(bus, "%s uCode section being loaded...\n", name);
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ret = wait_event_timeout(priv->shrd->wait_command_queue,
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ret = wait_event_timeout(trans->shrd->wait_command_queue,
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priv->ucode_write_complete, 5 * HZ);
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trans->ucode_write_complete, 5 * HZ);
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if (!ret) {
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if (!ret) {
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IWL_ERR(priv, "Could not load the %s uCode section\n",
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IWL_ERR(trans, "Could not load the %s uCode section\n",
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name);
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name);
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return -ETIMEDOUT;
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return -ETIMEDOUT;
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}
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}
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@ -129,12 +130,12 @@ static int iwlagn_load_given_ucode(struct iwl_priv *priv,
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{
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{
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int ret = 0;
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int ret = 0;
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ret = iwlagn_load_section(priv, "INST", &image->code,
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ret = iwlagn_load_section(trans(priv), "INST", &image->code,
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IWLAGN_RTC_INST_LOWER_BOUND);
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IWLAGN_RTC_INST_LOWER_BOUND);
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if (ret)
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if (ret)
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return ret;
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return ret;
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return iwlagn_load_section(priv, "DATA", &image->data,
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return iwlagn_load_section(trans(priv), "DATA", &image->data,
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IWLAGN_RTC_DATA_LOWER_BOUND);
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IWLAGN_RTC_DATA_LOWER_BOUND);
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}
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}
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@ -920,7 +920,6 @@ struct iwl_priv {
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struct fw_img ucode_wowlan;
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struct fw_img ucode_wowlan;
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enum iwlagn_ucode_type ucode_type;
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enum iwlagn_ucode_type ucode_type;
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u8 ucode_write_complete; /* the image write is complete */
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char firmware_name[25];
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char firmware_name[25];
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struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
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struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
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@ -1108,7 +1108,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
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isr_stats->tx++;
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isr_stats->tx++;
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handled |= CSR_INT_BIT_FH_TX;
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handled |= CSR_INT_BIT_FH_TX;
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/* Wake up uCode load routine, now that load is complete */
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/* Wake up uCode load routine, now that load is complete */
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priv(trans)->ucode_write_complete = 1;
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trans->ucode_write_complete = 1;
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wake_up(&trans->shrd->wait_command_queue);
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wake_up(&trans->shrd->wait_command_queue);
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}
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}
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@ -212,12 +212,15 @@ struct iwl_trans_ops {
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* @ops - pointer to iwl_trans_ops
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* @ops - pointer to iwl_trans_ops
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* @shrd - pointer to iwl_shared which holds shared data from the upper layer
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* @shrd - pointer to iwl_shared which holds shared data from the upper layer
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* @hcmd_lock: protects HCMD
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* @hcmd_lock: protects HCMD
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* @ucode_write_complete: indicates that the ucode has been copied.
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*/
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*/
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struct iwl_trans {
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struct iwl_trans {
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const struct iwl_trans_ops *ops;
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const struct iwl_trans_ops *ops;
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struct iwl_shared *shrd;
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struct iwl_shared *shrd;
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spinlock_t hcmd_lock;
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spinlock_t hcmd_lock;
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u8 ucode_write_complete; /* the image write is complete */
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/* pointer to trans specific struct */
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/* pointer to trans specific struct */
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/*Ensure that this pointer will always be aligned to sizeof pointer */
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/*Ensure that this pointer will always be aligned to sizeof pointer */
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char trans_specific[0] __attribute__((__aligned__(sizeof(void *))));
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char trans_specific[0] __attribute__((__aligned__(sizeof(void *))));
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