net: stmmac: Implement Safety Features in XGMAC core
XGMAC also supports Safety Features. This patch implements the configuration and handling of this feature in XGMAC core. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jose Abreu
David S. Miller
parent
74043f6b22
commit
56e58d6c8a
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@ -110,6 +110,12 @@
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#define XGMAC_HWFEAT_RXCHCNT GENMASK(15, 12)
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#define XGMAC_HWFEAT_TXQCNT GENMASK(9, 6)
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#define XGMAC_HWFEAT_RXQCNT GENMASK(3, 0)
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#define XGMAC_HW_FEATURE3 0x00000128
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#define XGMAC_HWFEAT_ASP GENMASK(15, 14)
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#define XGMAC_MAC_DPP_FSM_INT_STATUS 0x00000150
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#define XGMAC_MAC_FSM_CONTROL 0x00000158
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#define XGMAC_PRTYEN BIT(1)
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#define XGMAC_TMOUTEN BIT(0)
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#define XGMAC_MDIO_ADDR 0x00000200
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#define XGMAC_MDIO_DATA 0x00000204
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#define XGMAC_MDIO_C22P 0x00000220
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@ -154,6 +160,16 @@
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#define XGMAC_TC_PRTY_MAP1 0x00001044
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#define XGMAC_PSTC(x) GENMASK((x) * 8 + 7, (x) * 8)
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#define XGMAC_PSTC_SHIFT(x) ((x) * 8)
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#define XGMAC_MTL_ECC_CONTROL 0x000010c0
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#define XGMAC_MTL_SAFETY_INT_STATUS 0x000010c4
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#define XGMAC_MEUIS BIT(1)
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#define XGMAC_MECIS BIT(0)
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#define XGMAC_MTL_ECC_INT_ENABLE 0x000010c8
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#define XGMAC_RPCEIE BIT(12)
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#define XGMAC_ECEIE BIT(8)
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#define XGMAC_RXCEIE BIT(4)
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#define XGMAC_TXCEIE BIT(0)
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#define XGMAC_MTL_ECC_INT_STATUS 0x000010cc
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#define XGMAC_MTL_TXQ_OPMODE(x) (0x00001100 + (0x80 * (x)))
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#define XGMAC_TQS GENMASK(25, 16)
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#define XGMAC_TQS_SHIFT 16
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@ -218,6 +234,16 @@
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#define XGMAC_TDPS GENMASK(29, 0)
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#define XGMAC_RX_EDMA_CTRL 0x00003044
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#define XGMAC_RDPS GENMASK(29, 0)
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#define XGMAC_DMA_SAFETY_INT_STATUS 0x00003064
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#define XGMAC_MCSIS BIT(31)
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#define XGMAC_MSUIS BIT(29)
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#define XGMAC_MSCIS BIT(28)
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#define XGMAC_DEUIS BIT(1)
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#define XGMAC_DECIS BIT(0)
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#define XGMAC_DMA_ECC_INT_ENABLE 0x00003068
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#define XGMAC_DCEIE BIT(1)
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#define XGMAC_TCEIE BIT(0)
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#define XGMAC_DMA_ECC_INT_STATUS 0x0000306c
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#define XGMAC_DMA_CH_CONTROL(x) (0x00003100 + (0x80 * (x)))
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#define XGMAC_PBLx8 BIT(16)
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#define XGMAC_DMA_CH_TX_CONTROL(x) (0x00003104 + (0x80 * (x)))
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@ -530,6 +530,284 @@ static void dwxgmac2_update_vlan_hash(struct mac_device_info *hw, u32 hash,
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}
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}
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struct dwxgmac3_error_desc {
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bool valid;
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const char *desc;
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const char *detailed_desc;
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};
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#define STAT_OFF(field) offsetof(struct stmmac_safety_stats, field)
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static void dwxgmac3_log_error(struct net_device *ndev, u32 value, bool corr,
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const char *module_name,
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const struct dwxgmac3_error_desc *desc,
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unsigned long field_offset,
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struct stmmac_safety_stats *stats)
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{
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unsigned long loc, mask;
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u8 *bptr = (u8 *)stats;
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unsigned long *ptr;
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ptr = (unsigned long *)(bptr + field_offset);
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mask = value;
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for_each_set_bit(loc, &mask, 32) {
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netdev_err(ndev, "Found %s error in %s: '%s: %s'\n", corr ?
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"correctable" : "uncorrectable", module_name,
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desc[loc].desc, desc[loc].detailed_desc);
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/* Update counters */
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ptr[loc]++;
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}
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}
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static const struct dwxgmac3_error_desc dwxgmac3_mac_errors[32]= {
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{ true, "ATPES", "Application Transmit Interface Parity Check Error" },
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{ true, "DPES", "Descriptor Cache Data Path Parity Check Error" },
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{ true, "TPES", "TSO Data Path Parity Check Error" },
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{ true, "TSOPES", "TSO Header Data Path Parity Check Error" },
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{ true, "MTPES", "MTL Data Path Parity Check Error" },
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{ true, "MTSPES", "MTL TX Status Data Path Parity Check Error" },
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{ true, "MTBUPES", "MAC TBU Data Path Parity Check Error" },
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{ true, "MTFCPES", "MAC TFC Data Path Parity Check Error" },
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{ true, "ARPES", "Application Receive Interface Data Path Parity Check Error" },
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{ true, "MRWCPES", "MTL RWC Data Path Parity Check Error" },
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{ true, "MRRCPES", "MTL RCC Data Path Parity Check Error" },
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{ true, "CWPES", "CSR Write Data Path Parity Check Error" },
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{ true, "ASRPES", "AXI Slave Read Data Path Parity Check Error" },
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{ true, "TTES", "TX FSM Timeout Error" },
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{ true, "RTES", "RX FSM Timeout Error" },
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{ true, "CTES", "CSR FSM Timeout Error" },
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{ true, "ATES", "APP FSM Timeout Error" },
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{ true, "PTES", "PTP FSM Timeout Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 18 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 19 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 20 */
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{ true, "MSTTES", "Master Read/Write Timeout Error" },
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{ true, "SLVTES", "Slave Read/Write Timeout Error" },
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{ true, "ATITES", "Application Timeout on ATI Interface Error" },
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{ true, "ARITES", "Application Timeout on ARI Interface Error" },
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{ true, "FSMPES", "FSM State Parity Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 26 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 27 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 28 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 29 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 30 */
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{ true, "CPI", "Control Register Parity Check Error" },
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};
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static void dwxgmac3_handle_mac_err(struct net_device *ndev,
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void __iomem *ioaddr, bool correctable,
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struct stmmac_safety_stats *stats)
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{
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u32 value;
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value = readl(ioaddr + XGMAC_MAC_DPP_FSM_INT_STATUS);
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writel(value, ioaddr + XGMAC_MAC_DPP_FSM_INT_STATUS);
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dwxgmac3_log_error(ndev, value, correctable, "MAC",
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dwxgmac3_mac_errors, STAT_OFF(mac_errors), stats);
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}
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static const struct dwxgmac3_error_desc dwxgmac3_mtl_errors[32]= {
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{ true, "TXCES", "MTL TX Memory Error" },
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{ true, "TXAMS", "MTL TX Memory Address Mismatch Error" },
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{ true, "TXUES", "MTL TX Memory Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 3 */
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{ true, "RXCES", "MTL RX Memory Error" },
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{ true, "RXAMS", "MTL RX Memory Address Mismatch Error" },
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{ true, "RXUES", "MTL RX Memory Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 7 */
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{ true, "ECES", "MTL EST Memory Error" },
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{ true, "EAMS", "MTL EST Memory Address Mismatch Error" },
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{ true, "EUES", "MTL EST Memory Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 11 */
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{ true, "RPCES", "MTL RX Parser Memory Error" },
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{ true, "RPAMS", "MTL RX Parser Memory Address Mismatch Error" },
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{ true, "RPUES", "MTL RX Parser Memory Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 15 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 16 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 17 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 18 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 19 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 20 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 21 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 22 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 23 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 24 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 25 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 26 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 27 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 28 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 29 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 30 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 31 */
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};
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static void dwxgmac3_handle_mtl_err(struct net_device *ndev,
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void __iomem *ioaddr, bool correctable,
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struct stmmac_safety_stats *stats)
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{
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u32 value;
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value = readl(ioaddr + XGMAC_MTL_ECC_INT_STATUS);
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writel(value, ioaddr + XGMAC_MTL_ECC_INT_STATUS);
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dwxgmac3_log_error(ndev, value, correctable, "MTL",
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dwxgmac3_mtl_errors, STAT_OFF(mtl_errors), stats);
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}
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static const struct dwxgmac3_error_desc dwxgmac3_dma_errors[32]= {
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{ true, "TCES", "DMA TSO Memory Error" },
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{ true, "TAMS", "DMA TSO Memory Address Mismatch Error" },
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{ true, "TUES", "DMA TSO Memory Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 3 */
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{ true, "DCES", "DMA DCACHE Memory Error" },
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{ true, "DAMS", "DMA DCACHE Address Mismatch Error" },
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{ true, "DUES", "DMA DCACHE Memory Error" },
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{ false, "UNKNOWN", "Unknown Error" }, /* 7 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 8 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 9 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 10 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 11 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 12 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 13 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 14 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 15 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 16 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 17 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 18 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 19 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 20 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 21 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 22 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 23 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 24 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 25 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 26 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 27 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 28 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 29 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 30 */
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{ false, "UNKNOWN", "Unknown Error" }, /* 31 */
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};
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static void dwxgmac3_handle_dma_err(struct net_device *ndev,
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void __iomem *ioaddr, bool correctable,
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struct stmmac_safety_stats *stats)
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{
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u32 value;
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value = readl(ioaddr + XGMAC_DMA_ECC_INT_STATUS);
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writel(value, ioaddr + XGMAC_DMA_ECC_INT_STATUS);
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dwxgmac3_log_error(ndev, value, correctable, "DMA",
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dwxgmac3_dma_errors, STAT_OFF(dma_errors), stats);
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}
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static int dwxgmac3_safety_feat_config(void __iomem *ioaddr, unsigned int asp)
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{
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u32 value;
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if (!asp)
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return -EINVAL;
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/* 1. Enable Safety Features */
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writel(0x0, ioaddr + XGMAC_MTL_ECC_CONTROL);
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/* 2. Enable MTL Safety Interrupts */
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value = readl(ioaddr + XGMAC_MTL_ECC_INT_ENABLE);
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value |= XGMAC_RPCEIE; /* RX Parser Memory Correctable Error */
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value |= XGMAC_ECEIE; /* EST Memory Correctable Error */
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value |= XGMAC_RXCEIE; /* RX Memory Correctable Error */
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value |= XGMAC_TXCEIE; /* TX Memory Correctable Error */
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writel(value, ioaddr + XGMAC_MTL_ECC_INT_ENABLE);
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/* 3. Enable DMA Safety Interrupts */
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value = readl(ioaddr + XGMAC_DMA_ECC_INT_ENABLE);
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value |= XGMAC_DCEIE; /* Descriptor Cache Memory Correctable Error */
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value |= XGMAC_TCEIE; /* TSO Memory Correctable Error */
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writel(value, ioaddr + XGMAC_DMA_ECC_INT_ENABLE);
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/* Only ECC Protection for External Memory feature is selected */
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if (asp <= 0x1)
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return 0;
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/* 4. Enable Parity and Timeout for FSM */
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value = readl(ioaddr + XGMAC_MAC_FSM_CONTROL);
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value |= XGMAC_PRTYEN; /* FSM Parity Feature */
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value |= XGMAC_TMOUTEN; /* FSM Timeout Feature */
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writel(value, ioaddr + XGMAC_MAC_FSM_CONTROL);
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return 0;
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}
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static int dwxgmac3_safety_feat_irq_status(struct net_device *ndev,
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void __iomem *ioaddr,
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unsigned int asp,
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struct stmmac_safety_stats *stats)
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{
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bool err, corr;
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u32 mtl, dma;
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int ret = 0;
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if (!asp)
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return -EINVAL;
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mtl = readl(ioaddr + XGMAC_MTL_SAFETY_INT_STATUS);
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dma = readl(ioaddr + XGMAC_DMA_SAFETY_INT_STATUS);
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err = (mtl & XGMAC_MCSIS) || (dma & XGMAC_MCSIS);
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corr = false;
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if (err) {
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dwxgmac3_handle_mac_err(ndev, ioaddr, corr, stats);
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ret |= !corr;
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}
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err = (mtl & (XGMAC_MEUIS | XGMAC_MECIS)) ||
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(dma & (XGMAC_MSUIS | XGMAC_MSCIS));
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corr = (mtl & XGMAC_MECIS) || (dma & XGMAC_MSCIS);
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if (err) {
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dwxgmac3_handle_mtl_err(ndev, ioaddr, corr, stats);
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ret |= !corr;
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}
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err = dma & (XGMAC_DEUIS | XGMAC_DECIS);
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corr = dma & XGMAC_DECIS;
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if (err) {
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dwxgmac3_handle_dma_err(ndev, ioaddr, corr, stats);
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ret |= !corr;
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}
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return ret;
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}
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static const struct dwxgmac3_error {
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const struct dwxgmac3_error_desc *desc;
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} dwxgmac3_all_errors[] = {
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{ dwxgmac3_mac_errors },
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{ dwxgmac3_mtl_errors },
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{ dwxgmac3_dma_errors },
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};
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static int dwxgmac3_safety_feat_dump(struct stmmac_safety_stats *stats,
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int index, unsigned long *count,
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const char **desc)
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{
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int module = index / 32, offset = index % 32;
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unsigned long *ptr = (unsigned long *)stats;
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if (module >= ARRAY_SIZE(dwxgmac3_all_errors))
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return -EINVAL;
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if (!dwxgmac3_all_errors[module].desc[offset].valid)
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return -EINVAL;
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if (count)
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*count = *(ptr + index);
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if (desc)
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*desc = dwxgmac3_all_errors[module].desc[offset].desc;
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return 0;
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}
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const struct stmmac_ops dwxgmac210_ops = {
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.core_init = dwxgmac2_core_init,
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.set_mac = dwxgmac2_set_mac,
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@ -559,6 +837,9 @@ const struct stmmac_ops dwxgmac210_ops = {
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.pcs_get_adv_lp = NULL,
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.debug = NULL,
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.set_filter = dwxgmac2_set_filter,
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.safety_feat_config = dwxgmac3_safety_feat_config,
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.safety_feat_irq_status = dwxgmac3_safety_feat_irq_status,
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.safety_feat_dump = dwxgmac3_safety_feat_dump,
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.set_mac_loopback = dwxgmac2_set_mac_loopback,
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.rss_configure = dwxgmac2_rss_configure,
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.update_vlan_hash = dwxgmac2_update_vlan_hash,
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@ -399,6 +399,10 @@ static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
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((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
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dma_cap->number_rx_queues =
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((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
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/* MAC HW feature 3 */
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hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);
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dma_cap->asp = (hw_cap & XGMAC_HWFEAT_ASP) >> 14;
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}
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static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
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