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ARM: tegra: enhance timer.c to get IRQ info from device tree 

Modify Tegra's timer code to parse the Tegra timer IRQ from device tree,
and to instantiate the TWD from device tree, rather than relying on hard-
coded values from <mach/irqs.h>.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Stephen Warren 2012-09-19 13:13:33 -06:00
parent 58664f9052
commit 56415480e9
1 changed files with 23 additions and 18 deletions
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41
arch/arm/mach-tegra/timer.c
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@ -26,13 +26,12 @@
#include <linux/clocksource.h> #include <linux/clocksource.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/of_irq.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <asm/smp_twd.h> #include <asm/smp_twd.h>
#include <asm/sched_clock.h> #include <asm/sched_clock.h>
#include <mach/irqs.h>
#include "board.h" #include "board.h"
#include "clock.h" #include "clock.h"
#include "iomap.h" #include "iomap.h"
@ -158,30 +157,32 @@ static struct irqaction tegra_timer_irq = {
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH, .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
.handler = tegra_timer_interrupt, .handler = tegra_timer_interrupt,
.dev_id = &tegra_clockevent, .dev_id = &tegra_clockevent,
.irq = INT_TMR3,
}; };
#ifdef CONFIG_HAVE_ARM_TWD static const struct of_device_id timer_match[] __initconst = {
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, { .compatible = "nvidia,tegra20-timer" },
TEGRA_ARM_PERIF_BASE + 0x600, {}
IRQ_LOCALTIMER); };
static void __init tegra_twd_init(void)
{
int err = twd_local_timer_register(&twd_local_timer);
if (err)
pr_err("twd_local_timer_register failed %d\n", err);
}
#else
#define tegra_twd_init() do {} while(0)
#endif
static void __init tegra_init_timer(void) static void __init tegra_init_timer(void)
{ {
struct device_node *np;
struct clk *clk; struct clk *clk;
unsigned long rate; unsigned long rate;
int ret; int ret;
np = of_find_matching_node(NULL, timer_match);
if (!np) {
pr_err("Failed to find timer DT node\n");
BUG();
}
tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
if (tegra_timer_irq.irq <= 0) {
pr_err("Failed to map timer IRQ\n");
BUG();
}
clk = clk_get_sys("timer", NULL); clk = clk_get_sys("timer", NULL);
if (IS_ERR(clk)) { if (IS_ERR(clk)) {
pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
@ -201,6 +202,8 @@ static void __init tegra_init_timer(void)
else else
clk_prepare_enable(clk); clk_prepare_enable(clk);
of_node_put(np);
switch (rate) { switch (rate) {
case 12000000: case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG); timer_writel(0x000b, TIMERUS_USEC_CFG);
@ -240,7 +243,9 @@ static void __init tegra_init_timer(void)
tegra_clockevent.cpumask = cpu_all_mask; tegra_clockevent.cpumask = cpu_all_mask;
tegra_clockevent.irq = tegra_timer_irq.irq; tegra_clockevent.irq = tegra_timer_irq.irq;
clockevents_register_device(&tegra_clockevent); clockevents_register_device(&tegra_clockevent);
tegra_twd_init(); #ifdef CONFIG_HAVE_ARM_TWD
twd_local_timer_of_register();
#endif
register_persistent_clock(NULL, tegra_read_persistent_clock); register_persistent_clock(NULL, tegra_read_persistent_clock);
} }