drm/amd/display: update dml input population function
Update dcn20_populate_dml_pipes_from_context to correctly handle odm when no surface is provided. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1949,9 +1949,14 @@ int dcn20_populate_dml_pipes_from_context(
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}
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pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
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if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
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== res_ctx->pipe_ctx[i].plane_state) {
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struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
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while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
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== res_ctx->pipe_ctx[i].plane_state)
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pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
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else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
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first_pipe = first_pipe->top_pipe;
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pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
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} else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
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struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
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while (first_pipe->prev_odm_pipe)
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@ -2046,6 +2051,7 @@ int dcn20_populate_dml_pipes_from_context(
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pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
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if (!res_ctx->pipe_ctx[i].plane_state) {
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pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
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pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
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pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
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pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
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@ -2071,19 +2077,21 @@ int dcn20_populate_dml_pipes_from_context(
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pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
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pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
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pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
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pipes[pipe_cnt].pipe.src.is_hsplit = 0;
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pipes[pipe_cnt].pipe.dest.odm_combine = 0;
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pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
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pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
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if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
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pipes[pipe_cnt].pipe.src.viewport_width /= 2;
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pipes[pipe_cnt].pipe.dest.recout_width /= 2;
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}
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} else {
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struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
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struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
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pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
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pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
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&& res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
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|| (res_ctx->pipe_ctx[i].top_pipe
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&& res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
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pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
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|| (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
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|| pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
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pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
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|| pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
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pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
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@ -112,6 +112,7 @@ struct _vcs_dpi_soc_bounding_box_st {
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int use_urgent_burst_bw;
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unsigned int num_states;
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struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES];
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double min_dcfclk;
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bool do_urgent_latency_adjustment;
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double urgent_latency_adjustment_fabric_clock_component_us;
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double urgent_latency_adjustment_fabric_clock_reference_mhz;
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@ -266,8 +266,6 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
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mode_lib->vba.MaxDispclk[i] = soc->clock_limits[i].dispclk_mhz;
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mode_lib->vba.DTBCLKPerState[i] = soc->clock_limits[i].dtbclk_mhz;
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}
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mode_lib->vba.MinVoltageLevel = 0;
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mode_lib->vba.MaxVoltageLevel = mode_lib->vba.soc.num_states;
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mode_lib->vba.DoUrgentLatencyAdjustment =
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soc->do_urgent_latency_adjustment;
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@ -842,8 +842,6 @@ struct vba_vars_st {
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double DCCRateChroma[DC__NUM_DPP__MAX];
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double PHYCLKD18PerState[DC__VOLTAGE_STATES + 1];
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int MinVoltageLevel;
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int MaxVoltageLevel;
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bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
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bool NumberOfHDMIFRLSupport;
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@ -880,7 +878,6 @@ struct vba_vars_st {
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double TotalMetaRowBandwidth[DC__VOLTAGE_STATES + 1][2];
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double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES + 1][2];
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double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES + 1][2];
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bool UseMinimumRequiredDCFCLK;
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double WritebackDelayTime[DC__NUM_DPP__MAX];
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unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
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unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
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