mlx5-fixes-2022-03-09
-----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEGhZs6bAKwk/OTgTpSD+KveBX+j4FAmIpAngACgkQSD+KveBX +j6rMQf/fl7seXDl+rny/YyJ767P6fauh9kxPYt0eVOTa8hZ0nn3lmxP2m9UnsHL HQNrQwBmvjzmMffoTl5oUjDc+fxxWJgWk/WLThg8lZl2pghhnF2+IjJLE9ofvohW B0TYCOvjY61BoSi0PtjohD7rqUqONAQrMSmgyI79dIduHupcMw3ZOrr1SobUKWVg pP0vzXhb1TIPl1wT4Y+22KIfmzXHu7vyUDmKVLACrqh1nDsPC65P/yHcWzhXF1bO 2y/Pv1IK1DgjExfQ2m8HCg+XRlNmBJi7+1jc0QQ3Tfjj+oS6xDabxUAOuyS2S4ie KFYcftIYsUSSrQVJFGA2R2Td/bdhMg== =EDVx -----END PGP SIGNATURE----- Merge tag 'mlx5-fixes-2022-03-09' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5 fixes 2022-03-09 This series provides bug fixes to mlx5 driver. * tag 'mlx5-fixes-2022-03-09' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux: net/mlx5e: SHAMPO, reduce TIR indication net/mlx5e: Lag, Only handle events from highest priority multipath entry net/mlx5: Fix offloading with ESWITCH_IPV4_TTL_MODIFY_ENABLE net/mlx5: Fix a race on command flush flow net/mlx5: Fix size field in bufferx_reg struct ==================== Link: https://lore.kernel.org/r/20220309201517.589132-1-saeed@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
commit
55c4bf4d93
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@ -131,11 +131,8 @@ static int cmd_alloc_index(struct mlx5_cmd *cmd)
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static void cmd_free_index(struct mlx5_cmd *cmd, int idx)
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{
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unsigned long flags;
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spin_lock_irqsave(&cmd->alloc_lock, flags);
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lockdep_assert_held(&cmd->alloc_lock);
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set_bit(idx, &cmd->bitmask);
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spin_unlock_irqrestore(&cmd->alloc_lock, flags);
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}
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static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)
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@ -145,17 +142,21 @@ static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)
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static void cmd_ent_put(struct mlx5_cmd_work_ent *ent)
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{
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struct mlx5_cmd *cmd = ent->cmd;
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unsigned long flags;
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spin_lock_irqsave(&cmd->alloc_lock, flags);
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if (!refcount_dec_and_test(&ent->refcnt))
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return;
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goto out;
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if (ent->idx >= 0) {
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struct mlx5_cmd *cmd = ent->cmd;
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cmd_free_index(cmd, ent->idx);
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up(ent->page_queue ? &cmd->pages_sem : &cmd->sem);
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}
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cmd_free_ent(ent);
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out:
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spin_unlock_irqrestore(&cmd->alloc_lock, flags);
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}
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static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
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@ -88,9 +88,6 @@ void mlx5e_tir_builder_build_packet_merge(struct mlx5e_tir_builder *builder,
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(MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - rough_max_l2_l3_hdr_sz) >> 8);
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MLX5_SET(tirc, tirc, lro_timeout_period_usecs, pkt_merge_param->timeout);
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break;
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case MLX5E_PACKET_MERGE_SHAMPO:
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MLX5_SET(tirc, tirc, packet_merge_mask, MLX5_TIRC_PACKET_MERGE_MASK_SHAMPO);
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break;
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default:
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break;
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}
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@ -3616,8 +3616,7 @@ static int set_feature_hw_gro(struct net_device *netdev, bool enable)
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goto out;
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}
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err = mlx5e_safe_switch_params(priv, &new_params,
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mlx5e_modify_tirs_packet_merge_ctx, NULL, reset);
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err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset);
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out:
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mutex_unlock(&priv->state_lock);
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return err;
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@ -126,6 +126,10 @@ static void mlx5_lag_fib_route_event(struct mlx5_lag *ldev,
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return;
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}
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/* Handle multipath entry with lower priority value */
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if (mp->mfi && mp->mfi != fi && fi->fib_priority >= mp->mfi->fib_priority)
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return;
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/* Handle add/replace event */
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nhs = fib_info_num_path(fi);
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if (nhs == 1) {
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@ -135,12 +139,13 @@ static void mlx5_lag_fib_route_event(struct mlx5_lag *ldev,
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int i = mlx5_lag_dev_get_netdev_idx(ldev, nh_dev);
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if (i < 0)
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i = MLX5_LAG_NORMAL_AFFINITY;
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else
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++i;
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return;
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i++;
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mlx5_lag_set_port_affinity(ldev, i);
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}
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mp->mfi = fi;
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return;
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}
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@ -121,9 +121,6 @@ u32 mlx5_chains_get_nf_ft_chain(struct mlx5_fs_chains *chains)
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u32 mlx5_chains_get_prio_range(struct mlx5_fs_chains *chains)
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{
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if (!mlx5_chains_prios_supported(chains))
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return 1;
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if (mlx5_chains_ignore_flow_level_supported(chains))
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return UINT_MAX;
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@ -3434,7 +3434,6 @@ enum {
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enum {
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MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
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MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1),
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MLX5_TIRC_PACKET_MERGE_MASK_SHAMPO = BIT(2),
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};
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enum {
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@ -9900,8 +9899,8 @@ struct mlx5_ifc_bufferx_reg_bits {
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u8 reserved_at_0[0x6];
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u8 lossy[0x1];
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u8 epsb[0x1];
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u8 reserved_at_8[0xc];
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u8 size[0xc];
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u8 reserved_at_8[0x8];
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u8 size[0x10];
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u8 xoff_threshold[0x10];
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u8 xon_threshold[0x10];
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