drm/i915/dsi: remove old read/write functions in favor of new stuff
All of these are replaced by the drm core mipi dsi functions. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-By: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jani Nikula
Daniel Vetter
parent
759d10c2e1
commit
55a194ddc7
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@ -96,11 +96,6 @@ static void print_stat(struct intel_dsi *intel_dsi, enum port port)
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#undef STAT_BIT
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}
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enum dsi_type {
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DSI_DCS,
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DSI_GENERIC,
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};
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/* enable or disable command mode hs transmissions */
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void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
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enum port port)
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@ -121,260 +116,6 @@ void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
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intel_dsi->hs = enable;
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}
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static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
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u8 data_type, u16 data, enum port port)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 ctrl_reg;
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u32 ctrl;
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u32 mask;
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DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",
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channel, data_type, data);
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if (intel_dsi->hs) {
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ctrl_reg = MIPI_HS_GEN_CTRL(port);
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mask = HS_CTRL_FIFO_FULL;
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} else {
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ctrl_reg = MIPI_LP_GEN_CTRL(port);
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mask = LP_CTRL_FIFO_FULL;
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}
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if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) {
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DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
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print_stat(intel_dsi, port);
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}
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/*
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* Note: This function is also used for long packets, with length passed
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* as data, since SHORT_PACKET_PARAM_SHIFT ==
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* LONG_PACKET_WORD_COUNT_SHIFT.
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*/
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ctrl = data << SHORT_PACKET_PARAM_SHIFT |
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channel << VIRTUAL_CHANNEL_SHIFT |
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data_type << DATA_TYPE_SHIFT;
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I915_WRITE(ctrl_reg, ctrl);
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return 0;
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}
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static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
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u8 data_type, const u8 *data, int len, enum port port)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 data_reg;
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int i, j, n;
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u32 mask;
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DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",
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channel, data_type, len);
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if (intel_dsi->hs) {
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data_reg = MIPI_HS_GEN_DATA(port);
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mask = HS_DATA_FIFO_FULL;
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} else {
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data_reg = MIPI_LP_GEN_DATA(port);
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mask = LP_DATA_FIFO_FULL;
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}
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if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50))
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DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
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for (i = 0; i < len; i += n) {
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u32 val = 0;
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n = min_t(int, len - i, 4);
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for (j = 0; j < n; j++)
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val |= *data++ << 8 * j;
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I915_WRITE(data_reg, val);
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/* XXX: check for data fifo full, once that is set, write 4
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* dwords, then wait for not set, then continue. */
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}
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return dsi_vc_send_short(intel_dsi, channel, data_type, len, port);
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}
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static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
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int channel, const u8 *data, int len,
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enum dsi_type type, enum port port)
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{
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int ret;
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if (len == 0) {
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BUG_ON(type == DSI_GENERIC);
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ret = dsi_vc_send_short(intel_dsi, channel,
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MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
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0, port);
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} else if (len == 1) {
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ret = dsi_vc_send_short(intel_dsi, channel,
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type == DSI_GENERIC ?
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MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
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MIPI_DSI_DCS_SHORT_WRITE, data[0],
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port);
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} else if (len == 2) {
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ret = dsi_vc_send_short(intel_dsi, channel,
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type == DSI_GENERIC ?
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MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
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MIPI_DSI_DCS_SHORT_WRITE_PARAM,
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(data[1] << 8) | data[0], port);
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} else {
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ret = dsi_vc_send_long(intel_dsi, channel,
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type == DSI_GENERIC ?
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MIPI_DSI_GENERIC_LONG_WRITE :
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MIPI_DSI_DCS_LONG_WRITE, data, len,
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port);
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}
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return ret;
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}
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int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
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const u8 *data, int len, enum port port)
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{
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return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS,
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port);
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}
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int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
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const u8 *data, int len, enum port port)
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{
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return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC,
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port);
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}
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static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
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int channel, u8 dcs_cmd, enum port port)
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{
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return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
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dcs_cmd, port);
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}
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static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
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int channel, u8 *reqdata,
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int reqlen, enum port port)
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{
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u16 data;
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u8 data_type;
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switch (reqlen) {
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case 0:
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data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
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data = 0;
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break;
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case 1:
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data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
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data = reqdata[0];
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break;
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case 2:
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data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
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data = (reqdata[1] << 8) | reqdata[0];
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break;
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default:
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BUG();
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}
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return dsi_vc_send_short(intel_dsi, channel, data_type, data, port);
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}
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static int dsi_read_data_return(struct intel_dsi *intel_dsi,
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u8 *buf, int buflen, enum port port)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i, len = 0;
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u32 data_reg, val;
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if (intel_dsi->hs) {
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data_reg = MIPI_HS_GEN_DATA(port);
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} else {
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data_reg = MIPI_LP_GEN_DATA(port);
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}
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while (len < buflen) {
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val = I915_READ(data_reg);
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for (i = 0; i < 4 && len < buflen; i++, len++)
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buf[len] = val >> 8 * i;
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}
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return len;
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}
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int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
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u8 *buf, int buflen, enum port port)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 mask;
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int ret;
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/*
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* XXX: should issue multiple read requests and reads if request is
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* longer than MIPI_MAX_RETURN_PKT_SIZE
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*/
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I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
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ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd, port);
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if (ret)
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return ret;
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mask = GEN_READ_DATA_AVAIL;
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if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
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DRM_ERROR("Timeout waiting for read data.\n");
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ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
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if (ret < 0)
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return ret;
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if (ret != buflen)
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return -EIO;
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return 0;
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}
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int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
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u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 mask;
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int ret;
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/*
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* XXX: should issue multiple read requests and reads if request is
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* longer than MIPI_MAX_RETURN_PKT_SIZE
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*/
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I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
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ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
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reqlen, port);
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if (ret)
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return ret;
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mask = GEN_READ_DATA_AVAIL;
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if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
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DRM_ERROR("Timeout waiting for read data.\n");
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ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
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if (ret < 0)
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return ret;
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if (ret != buflen)
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return -EIO;
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return 0;
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}
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/*
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* send a video mode command
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*
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@ -39,78 +39,6 @@
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void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
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enum port port);
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int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
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const u8 *data, int len, enum port port);
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int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
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const u8 *data, int len, enum port port);
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int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
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u8 *buf, int buflen, enum port port);
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int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
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u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port);
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int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, enum port port);
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/* XXX: questionable write helpers */
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static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
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int channel, u8 dcs_cmd, enum port port)
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{
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return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1, port);
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}
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static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi,
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int channel, u8 dcs_cmd, u8 param, enum port port)
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{
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u8 buf[2] = { dcs_cmd, param };
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return dsi_vc_dcs_write(intel_dsi, channel, buf, 2, port);
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}
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static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi,
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int channel, enum port port)
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{
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return dsi_vc_generic_write(intel_dsi, channel, NULL, 0, port);
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}
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static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi,
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int channel, u8 param, enum port port)
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{
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return dsi_vc_generic_write(intel_dsi, channel, ¶m, 1, port);
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}
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static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi,
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int channel, u8 param1, u8 param2, enum port port)
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{
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u8 buf[2] = { param1, param2 };
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return dsi_vc_generic_write(intel_dsi, channel, buf, 2, port);
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}
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/* XXX: questionable read helpers */
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static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi,
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int channel, u8 *buf, int buflen, enum port port)
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{
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return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen,
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port);
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}
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static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi,
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int channel, u8 param, u8 *buf,
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int buflen, enum port port)
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{
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return dsi_vc_generic_read(intel_dsi, channel, ¶m, 1, buf, buflen,
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port);
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}
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static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi,
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int channel, u8 param1, u8 param2,
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u8 *buf, int buflen, enum port port)
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{
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u8 req[2] = { param1, param2 };
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return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen,
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port);
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}
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#endif /* _INTEL_DSI_DSI_H */
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