mlxsw: spectrum: Store local port to module mapping during init
The port netdevs are each associated with a different local port number in the device. These local ports are grouped into groups of 4 (e.g. (1-4), (5-8)) called clusters. The cluster constitutes the one of two possible modules they can be mapped to. This mapping is board-specific and done by the device's firmware during init. When splitting a port by 4, the device requires us to first unmap all the ports in the cluster and then map each to a single lane in the module associated with the port netdev used as the handle for the operation. This means that two port netdevs will disappear, as only 100Gb/s (4 lanes) ports can be split and we are guaranteed to have two of these ((1, 3), (5, 7) etc.) in a cluster. When unsplit occurs we need to reinstantiate the two original 100Gb/s ports and map each to its origianl module. Therefore, during driver init store the initial local port to module mapping, so it can be used later during unsplitting. Note that a by 2 split doesn't require us to store the mapping, as we only need to reinstantiate one port whose module is known. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -305,18 +305,19 @@ mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
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return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
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}
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static int mlxsw_sp_port_module_check(struct mlxsw_sp_port *mlxsw_sp_port,
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bool *p_usable)
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static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
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u8 local_port, u8 *p_module,
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u8 *p_width)
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{
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struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
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char pmlp_pl[MLXSW_REG_PMLP_LEN];
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int err;
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mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
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mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
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err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
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if (err)
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return err;
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*p_usable = mlxsw_reg_pmlp_width_get(pmlp_pl) ? true : false;
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*p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
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*p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
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return 0;
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}
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@ -1365,7 +1366,6 @@ static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port)
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struct mlxsw_sp_port *mlxsw_sp_port;
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struct devlink_port *devlink_port;
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struct net_device *dev;
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bool usable;
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size_t bytes;
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int err;
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@ -1416,19 +1416,6 @@ static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port)
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*/
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dev->hard_header_len += MLXSW_TXHDR_LEN;
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err = mlxsw_sp_port_module_check(mlxsw_sp_port, &usable);
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if (err) {
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dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to check module\n",
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mlxsw_sp_port->local_port);
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goto err_port_module_check;
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}
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if (!usable) {
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dev_dbg(mlxsw_sp->bus_info->dev, "Port %d: Not usable, skipping initialization\n",
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mlxsw_sp_port->local_port);
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goto port_not_usable;
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}
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devlink_port = &mlxsw_sp_port->devlink_port;
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err = devlink_port_register(devlink, devlink_port, local_port);
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if (err) {
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@ -1496,8 +1483,6 @@ err_port_swid_set:
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err_port_system_port_mapping_set:
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devlink_port_unregister(&mlxsw_sp_port->devlink_port);
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err_devlink_port_register:
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port_not_usable:
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err_port_module_check:
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err_dev_addr_init:
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free_percpu(mlxsw_sp_port->pcpu_stats);
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err_alloc_stats:
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@ -1559,6 +1544,7 @@ static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
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static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
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{
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size_t alloc_size;
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u8 module, width;
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int i;
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int err;
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@ -1568,6 +1554,13 @@ static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
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return -ENOMEM;
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for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
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err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
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&width);
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if (err)
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goto err_port_module_info_get;
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if (!width)
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continue;
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mlxsw_sp->port_to_module[i] = module;
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err = mlxsw_sp_port_create(mlxsw_sp, i);
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if (err)
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goto err_port_create;
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@ -1575,6 +1568,7 @@ static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
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return 0;
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err_port_create:
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err_port_module_info_get:
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for (i--; i >= 1; i--)
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mlxsw_sp_port_remove(mlxsw_sp, i);
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kfree(mlxsw_sp->ports);
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@ -123,6 +123,7 @@ struct mlxsw_sp {
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u32 ageing_time;
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struct mlxsw_sp_upper master_bridge;
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struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
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u8 port_to_module[MLXSW_PORT_MAX_PORTS];
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};
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static inline struct mlxsw_sp_upper *
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