omap3630: Set omap3630 MMC1 I/O speed to 52Mhz
The speed ctrl bit for MMC I/O is part of CONTROL_PROG_IO1 register in omap3630.This patch sets it up accordingly. Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -213,7 +213,7 @@ static int twl4030_mmc_get_context_loss(struct device *dev)
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static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
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static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
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int vdd)
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int vdd)
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{
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{
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u32 reg;
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u32 reg, prog_io;
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int ret = 0;
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int ret = 0;
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struct twl_mmc_controller *c = &hsmmc[0];
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struct twl_mmc_controller *c = &hsmmc[0];
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struct omap_mmc_platform_data *mmc = dev->platform_data;
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struct omap_mmc_platform_data *mmc = dev->platform_data;
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@ -245,7 +245,14 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
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}
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}
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reg = omap_ctrl_readl(control_pbias_offset);
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reg = omap_ctrl_readl(control_pbias_offset);
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if (cpu_is_omap3630()) {
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/* Set MMC I/O to 52Mhz */
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prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
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prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
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omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
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} else {
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reg |= OMAP2_PBIASSPEEDCTRL0;
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reg |= OMAP2_PBIASSPEEDCTRL0;
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}
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reg &= ~OMAP2_PBIASLITEPWRDNZ0;
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reg &= ~OMAP2_PBIASLITEPWRDNZ0;
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omap_ctrl_writel(reg, control_pbias_offset);
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omap_ctrl_writel(reg, control_pbias_offset);
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@ -241,6 +241,9 @@
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#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
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#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
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#define OMAP2_PBIASLITEVMODE0 (1 << 0)
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#define OMAP2_PBIASLITEVMODE0 (1 << 0)
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/* CONTROL_PROG_IO1 bits */
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#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
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/* CONTROL_IVA2_BOOTMOD bits */
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/* CONTROL_IVA2_BOOTMOD bits */
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#define OMAP3_IVA2_BOOTMOD_SHIFT 0
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#define OMAP3_IVA2_BOOTMOD_SHIFT 0
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#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
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#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)
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