staging: Add rtl8723bs sdio wifi driver
The rtl8723bs is found on quite a few systems used by Linux users, such as on Atom systems (Intel Computestick and various other Atom based devices) and on many (budget) ARM boards such as the CHIP. The plan moving forward with this is for the new clean, written from scratch, rtl8xxxu driver to eventually gain support for sdio devices. But there is no clear timeline for that, so lets add this driver included in staging for now. Cc: Bastien Nocera <hadess@hadess.net> Cc: Larry Finger <Larry.Finger@lwfinger.net> Cc: Jes Sorensen <jes.sorensen@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Hans de Goede
Greg Kroah-Hartman
parent
38ca74e58f
commit
554c0a3abf
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@ -34,6 +34,8 @@ source "drivers/staging/rtl8192u/Kconfig"
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source "drivers/staging/rtl8192e/Kconfig"
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source "drivers/staging/rtl8723bs/Kconfig"
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source "drivers/staging/rtl8712/Kconfig"
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source "drivers/staging/rtl8188eu/Kconfig"
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@ -6,6 +6,7 @@ obj-$(CONFIG_COMEDI) += comedi/
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obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/
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obj-$(CONFIG_RTL8192U) += rtl8192u/
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obj-$(CONFIG_RTL8192E) += rtl8192e/
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obj-$(CONFIG_RTL8723BS) += rtl8723bs/
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obj-$(CONFIG_R8712U) += rtl8712/
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obj-$(CONFIG_R8188EU) += rtl8188eu/
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obj-$(CONFIG_RTS5208) += rts5208/
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@ -0,0 +1,10 @@
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config RTL8723BS
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tristate "Realtek RTL8723BS SDIO Wireless LAN NIC driver"
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depends on WLAN && MMC && CFG80211
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select WIRELESS_EXT
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select WEXT_PRIV
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---help---
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This option enables support for RTL8723BS SDIO drivers, such as
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the wifi found on the 1st gen Intel Compute Stick, the CHIP
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and many other Intel Atom and ARM based devices.
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If built as a module, it will be called r8723bs.
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@ -0,0 +1,70 @@
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r8723bs-y = \
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core/rtw_ap.o \
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core/rtw_btcoex.o \
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core/rtw_cmd.o \
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core/rtw_debug.o \
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core/rtw_efuse.o \
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core/rtw_io.o \
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core/rtw_ioctl_set.o \
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core/rtw_ieee80211.o \
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core/rtw_mlme.o \
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core/rtw_mlme_ext.o \
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core/rtw_odm.o \
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core/rtw_pwrctrl.o \
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core/rtw_recv.o \
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core/rtw_rf.o \
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core/rtw_security.o \
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core/rtw_sta_mgt.o \
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core/rtw_wlan_util.o \
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core/rtw_xmit.o \
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hal/hal_intf.o \
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hal/hal_com.o \
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hal/hal_com_phycfg.o \
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hal/hal_btcoex.o \
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hal/hal_sdio.o \
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hal/Hal8723BPwrSeq.o \
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hal/HalPhyRf.o \
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hal/HalPwrSeqCmd.o \
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hal/odm.o \
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hal/odm_CfoTracking.o \
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hal/odm_debug.o \
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hal/odm_DIG.o \
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hal/odm_DynamicBBPowerSaving.o \
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hal/odm_DynamicTxPower.o \
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hal/odm_EdcaTurboCheck.o \
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hal/odm_HWConfig.o \
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hal/odm_NoiseMonitor.o \
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hal/odm_PathDiv.o \
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hal/odm_RegConfig8723B.o \
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hal/odm_RTL8723B.o \
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hal/rtl8723b_cmd.o \
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hal/rtl8723b_dm.o \
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hal/rtl8723b_hal_init.o \
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hal/rtl8723b_phycfg.o \
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hal/rtl8723b_rf6052.o \
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hal/rtl8723b_rxdesc.o \
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hal/rtl8723bs_recv.o \
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hal/rtl8723bs_xmit.o \
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hal/sdio_halinit.o \
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hal/sdio_ops.o \
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hal/HalBtc8723b1Ant.o \
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hal/HalBtc8723b2Ant.o \
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hal/HalHWImg8723B_BB.o \
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hal/HalHWImg8723B_MAC.o \
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hal/HalHWImg8723B_RF.o \
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hal/HalPhyRf_8723B.o \
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os_dep/ioctl_cfg80211.o \
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os_dep/ioctl_linux.o \
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os_dep/mlme_linux.o \
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os_dep/osdep_service.o \
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os_dep/os_intfs.o \
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os_dep/recv_linux.o \
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os_dep/rtw_proc.o \
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os_dep/sdio_intf.o \
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os_dep/sdio_ops_linux.o \
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os_dep/wifi_regd.o \
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os_dep/xmit_linux.o
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obj-$(CONFIG_RTL8723BS) := r8723bs.o
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ccflags-y += -I$(srctree)/$(src)/include -I$(srctree)/$(src)/hal
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@ -0,0 +1,16 @@
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TODO:
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- find and remove code blocks guarded by never set CONFIG_FOO defines
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- find and remove remaining code valid only for 5 HGz. Most of the obvious
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ones have been removed, but things like channel > 14 still exist.
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- find and remove any code for other chips that is left over
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- convert any remaining unusual variable types
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- find codes that can use %pM and %Nph formatting
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- checkpatch.pl fixes - most of the remaining ones are lines too long. Many
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of them will require refactoring
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- merge Realtek's bugfixes and new features into the driver
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- switch to use LIB80211
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- switch to use MAC80211
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Please send any patches to Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
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Bastien Nocera <hadess@hadess.net>, Hans de Goede <hdegoede@redhat.com>
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and Larry Finger <Larry.Finger@lwfinger.net>.
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,243 @@
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/******************************************************************************
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*
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* Copyright(c) 2013 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#include <drv_types.h>
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#include <rtw_debug.h>
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#include <rtw_btcoex.h>
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#include <hal_btcoex.h>
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void rtw_btcoex_Initialize(struct adapter *padapter)
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{
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hal_btcoex_Initialize(padapter);
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}
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void rtw_btcoex_PowerOnSetting(struct adapter *padapter)
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{
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hal_btcoex_PowerOnSetting(padapter);
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}
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void rtw_btcoex_HAL_Initialize(struct adapter *padapter, u8 bWifiOnly)
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{
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hal_btcoex_InitHwConfig(padapter, bWifiOnly);
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}
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void rtw_btcoex_IpsNotify(struct adapter *padapter, u8 type)
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{
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hal_btcoex_IpsNotify(padapter, type);
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}
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void rtw_btcoex_LpsNotify(struct adapter *padapter, u8 type)
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{
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hal_btcoex_LpsNotify(padapter, type);
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}
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void rtw_btcoex_ScanNotify(struct adapter *padapter, u8 type)
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{
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hal_btcoex_ScanNotify(padapter, type);
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}
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void rtw_btcoex_ConnectNotify(struct adapter *padapter, u8 action)
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{
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hal_btcoex_ConnectNotify(padapter, action);
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}
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void rtw_btcoex_MediaStatusNotify(struct adapter *padapter, u8 mediaStatus)
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{
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if ((RT_MEDIA_CONNECT == mediaStatus)
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&& (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == true)) {
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rtw_hal_set_hwreg(padapter, HW_VAR_DL_RSVD_PAGE, NULL);
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}
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hal_btcoex_MediaStatusNotify(padapter, mediaStatus);
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}
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void rtw_btcoex_SpecialPacketNotify(struct adapter *padapter, u8 pktType)
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{
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hal_btcoex_SpecialPacketNotify(padapter, pktType);
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}
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void rtw_btcoex_IQKNotify(struct adapter *padapter, u8 state)
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{
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hal_btcoex_IQKNotify(padapter, state);
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}
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void rtw_btcoex_BtInfoNotify(struct adapter *padapter, u8 length, u8 *tmpBuf)
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{
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hal_btcoex_BtInfoNotify(padapter, length, tmpBuf);
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}
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void rtw_btcoex_SuspendNotify(struct adapter *padapter, u8 state)
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{
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hal_btcoex_SuspendNotify(padapter, state);
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}
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void rtw_btcoex_HaltNotify(struct adapter *padapter)
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{
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if (false == padapter->bup) {
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DBG_871X(FUNC_ADPT_FMT ": bup =%d Skip!\n",
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FUNC_ADPT_ARG(padapter), padapter->bup);
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return;
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}
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if (true == padapter->bSurpriseRemoved) {
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DBG_871X(FUNC_ADPT_FMT ": bSurpriseRemoved =%d Skip!\n",
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FUNC_ADPT_ARG(padapter), padapter->bSurpriseRemoved);
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return;
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}
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hal_btcoex_HaltNotify(padapter);
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}
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u8 rtw_btcoex_IsBtDisabled(struct adapter *padapter)
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{
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return hal_btcoex_IsBtDisabled(padapter);
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}
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void rtw_btcoex_Handler(struct adapter *padapter)
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{
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hal_btcoex_Hanlder(padapter);
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}
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s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(struct adapter *padapter)
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{
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s32 coexctrl;
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coexctrl = hal_btcoex_IsBTCoexCtrlAMPDUSize(padapter);
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return coexctrl;
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}
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void rtw_btcoex_SetManualControl(struct adapter *padapter, u8 manual)
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{
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if (true == manual) {
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hal_btcoex_SetManualControl(padapter, true);
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} else{
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hal_btcoex_SetManualControl(padapter, false);
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}
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}
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u8 rtw_btcoex_IsBtControlLps(struct adapter *padapter)
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{
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return hal_btcoex_IsBtControlLps(padapter);
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}
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u8 rtw_btcoex_IsLpsOn(struct adapter *padapter)
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{
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return hal_btcoex_IsLpsOn(padapter);
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}
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u8 rtw_btcoex_RpwmVal(struct adapter *padapter)
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{
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return hal_btcoex_RpwmVal(padapter);
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}
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u8 rtw_btcoex_LpsVal(struct adapter *padapter)
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{
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return hal_btcoex_LpsVal(padapter);
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}
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void rtw_btcoex_SetBTCoexist(struct adapter *padapter, u8 bBtExist)
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{
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hal_btcoex_SetBTCoexist(padapter, bBtExist);
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}
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void rtw_btcoex_SetChipType(struct adapter *padapter, u8 chipType)
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{
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hal_btcoex_SetChipType(padapter, chipType);
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}
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void rtw_btcoex_SetPGAntNum(struct adapter *padapter, u8 antNum)
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{
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hal_btcoex_SetPgAntNum(padapter, antNum);
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}
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void rtw_btcoex_SetSingleAntPath(struct adapter *padapter, u8 singleAntPath)
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{
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hal_btcoex_SetSingleAntPath(padapter, singleAntPath);
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}
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u32 rtw_btcoex_GetRaMask(struct adapter *padapter)
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{
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return hal_btcoex_GetRaMask(padapter);
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}
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void rtw_btcoex_RecordPwrMode(struct adapter *padapter, u8 *pCmdBuf, u8 cmdLen)
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{
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hal_btcoex_RecordPwrMode(padapter, pCmdBuf, cmdLen);
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}
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void rtw_btcoex_DisplayBtCoexInfo(struct adapter *padapter, u8 *pbuf, u32 bufsize)
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{
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hal_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize);
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}
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void rtw_btcoex_SetDBG(struct adapter *padapter, u32 *pDbgModule)
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{
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hal_btcoex_SetDBG(padapter, pDbgModule);
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}
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u32 rtw_btcoex_GetDBG(struct adapter *padapter, u8 *pStrBuf, u32 bufSize)
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{
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return hal_btcoex_GetDBG(padapter, pStrBuf, bufSize);
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}
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/* ================================================== */
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/* Below Functions are called by BT-Coex */
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/* ================================================== */
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void rtw_btcoex_RejectApAggregatedPacket(struct adapter *padapter, u8 enable)
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{
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struct mlme_ext_info *pmlmeinfo;
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struct sta_info *psta;
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pmlmeinfo = &padapter->mlmeextpriv.mlmext_info;
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psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
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if (true == enable) {
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pmlmeinfo->bAcceptAddbaReq = false;
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if (psta)
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send_delba(padapter, 0, psta->hwaddr);
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} else{
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pmlmeinfo->bAcceptAddbaReq = true;
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}
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}
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void rtw_btcoex_LPS_Enter(struct adapter *padapter)
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{
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struct pwrctrl_priv *pwrpriv;
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u8 lpsVal;
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pwrpriv = adapter_to_pwrctl(padapter);
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pwrpriv->bpower_saving = true;
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lpsVal = rtw_btcoex_LpsVal(padapter);
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rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, "BTCOEX");
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}
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void rtw_btcoex_LPS_Leave(struct adapter *padapter)
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{
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struct pwrctrl_priv *pwrpriv;
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pwrpriv = adapter_to_pwrctl(padapter);
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if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) {
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rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "BTCOEX");
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LPS_RF_ON_check(padapter, 100);
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pwrpriv->bpower_saving = false;
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}
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}
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,369 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#define _RTW_EEPROM_C_
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#include <drv_conf.h>
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#include <osdep_service.h>
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#include <drv_types.h>
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void up_clk(_adapter *padapter, u16 *x)
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{
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_func_enter_;
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*x = *x | _EESK;
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rtw_write8(padapter, EE_9346CR, (u8)*x);
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udelay(CLOCK_RATE);
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_func_exit_;
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}
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void down_clk(_adapter *padapter, u16 *x)
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{
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_func_enter_;
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*x = *x & ~_EESK;
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rtw_write8(padapter, EE_9346CR, (u8)*x);
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udelay(CLOCK_RATE);
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_func_exit_;
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}
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void shift_out_bits(_adapter *padapter, u16 data, u16 count)
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{
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u16 x, mask;
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_func_enter_;
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if (padapter->bSurpriseRemoved == true) {
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RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
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goto out;
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}
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mask = 0x01 << (count - 1);
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x = rtw_read8(padapter, EE_9346CR);
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x &= ~(_EEDO | _EEDI);
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do {
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x &= ~_EEDI;
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if (data & mask)
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x |= _EEDI;
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if (padapter->bSurpriseRemoved == true) {
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RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
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goto out;
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}
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rtw_write8(padapter, EE_9346CR, (u8)x);
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udelay(CLOCK_RATE);
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up_clk(padapter, &x);
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down_clk(padapter, &x);
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mask = mask >> 1;
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} while (mask);
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if (padapter->bSurpriseRemoved == true) {
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RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
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goto out;
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}
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x &= ~_EEDI;
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rtw_write8(padapter, EE_9346CR, (u8)x);
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out:
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_func_exit_;
|
||||
}
|
||||
|
||||
u16 shift_in_bits(_adapter *padapter)
|
||||
{
|
||||
u16 x, d = 0, i;
|
||||
_func_enter_;
|
||||
if (padapter->bSurpriseRemoved == true) {
|
||||
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
|
||||
goto out;
|
||||
}
|
||||
x = rtw_read8(padapter, EE_9346CR);
|
||||
|
||||
x &= ~(_EEDO | _EEDI);
|
||||
d = 0;
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
d = d << 1;
|
||||
up_clk(padapter, &x);
|
||||
if (padapter->bSurpriseRemoved == true) {
|
||||
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
|
||||
goto out;
|
||||
}
|
||||
x = rtw_read8(padapter, EE_9346CR);
|
||||
|
||||
x &= ~(_EEDI);
|
||||
if (x & _EEDO)
|
||||
d |= 1;
|
||||
|
||||
down_clk(padapter, &x);
|
||||
}
|
||||
out:
|
||||
_func_exit_;
|
||||
|
||||
return d;
|
||||
}
|
||||
|
||||
void standby(_adapter *padapter)
|
||||
{
|
||||
u8 x;
|
||||
_func_enter_;
|
||||
x = rtw_read8(padapter, EE_9346CR);
|
||||
|
||||
x &= ~(_EECS | _EESK);
|
||||
rtw_write8(padapter, EE_9346CR, x);
|
||||
|
||||
udelay(CLOCK_RATE);
|
||||
x |= _EECS;
|
||||
rtw_write8(padapter, EE_9346CR, x);
|
||||
udelay(CLOCK_RATE);
|
||||
_func_exit_;
|
||||
}
|
||||
|
||||
u16 wait_eeprom_cmd_done(_adapter *padapter)
|
||||
{
|
||||
u8 x;
|
||||
u16 i, res = false;
|
||||
_func_enter_;
|
||||
standby(padapter);
|
||||
for (i = 0; i < 200; i++) {
|
||||
x = rtw_read8(padapter, EE_9346CR);
|
||||
if (x & _EEDO) {
|
||||
res = true;
|
||||
goto exit;
|
||||
}
|
||||
udelay(CLOCK_RATE);
|
||||
}
|
||||
exit:
|
||||
_func_exit_;
|
||||
return res;
|
||||
}
|
||||
|
||||
void eeprom_clean(_adapter *padapter)
|
||||
{
|
||||
u16 x;
|
||||
_func_enter_;
|
||||
if (padapter->bSurpriseRemoved == true) {
|
||||
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
|
||||
goto out;
|
||||
}
|
||||
x = rtw_read8(padapter, EE_9346CR);
|
||||
if (padapter->bSurpriseRemoved == true) {
|
||||
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
|
||||
goto out;
|
||||
}
|
||||
x &= ~(_EECS | _EEDI);
|
||||
rtw_write8(padapter, EE_9346CR, (u8)x);
|
||||
if (padapter->bSurpriseRemoved == true) {
|
||||
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
|
||||
goto out;
|
||||
}
|
||||
up_clk(padapter, &x);
|
||||
if (padapter->bSurpriseRemoved == true) {
|
||||
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
|
||||
goto out;
|
||||
}
|
||||
down_clk(padapter, &x);
|
||||
out:
|
||||
_func_exit_;
|
||||
}
|
||||
|
||||
void eeprom_write16(_adapter *padapter, u16 reg, u16 data)
|
||||
{
|
||||
u8 x;
|
||||
|
||||
_func_enter_;
|
||||
|
||||
x = rtw_read8(padapter, EE_9346CR);
|
||||
|
||||
x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
|
||||
x |= _EEM1 | _EECS;
|
||||
rtw_write8(padapter, EE_9346CR, x);
|
||||
|
||||
shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5);
|
||||
|
||||
if (padapter->EepromAddressSize == 8) /*CF+ and SDIO*/
|
||||
shift_out_bits(padapter, 0, 6);
|
||||
else /*USB*/
|
||||
shift_out_bits(padapter, 0, 4);
|
||||
|
||||
standby(padapter);
|
||||
|
||||
/* Commented out by rcnjko, 2004.0
|
||||
* Erase this particular word. Write the erase opcode and register
|
||||
* number in that order. The opcode is 3bits in length; reg is 6 bits long.
|
||||
* shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3);
|
||||
* shift_out_bits(Adapter, reg, Adapter->EepromAddressSize);
|
||||
*
|
||||
* if (wait_eeprom_cmd_done(Adapter ) == false)
|
||||
* {
|
||||
* return;
|
||||
* }
|
||||
*/
|
||||
|
||||
standby(padapter);
|
||||
|
||||
/* write the new word to the EEPROM*/
|
||||
|
||||
/* send the write opcode the EEPORM*/
|
||||
shift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3);
|
||||
|
||||
/* select which word in the EEPROM that we are writing to.*/
|
||||
shift_out_bits(padapter, reg, padapter->EepromAddressSize);
|
||||
|
||||
/* write the data to the selected EEPROM word.*/
|
||||
shift_out_bits(padapter, data, 16);
|
||||
|
||||
if (wait_eeprom_cmd_done(padapter) == false) {
|
||||
|
||||
goto exit;
|
||||
}
|
||||
|
||||
standby(padapter);
|
||||
|
||||
shift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5);
|
||||
shift_out_bits(padapter, reg, 4);
|
||||
|
||||
eeprom_clean(padapter);
|
||||
exit:
|
||||
_func_exit_;
|
||||
return;
|
||||
}
|
||||
|
||||
u16 eeprom_read16(_adapter *padapter, u16 reg) /*ReadEEprom*/
|
||||
{
|
||||
|
||||
u16 x;
|
||||
u16 data = 0;
|
||||
|
||||
_func_enter_;
|
||||
|
||||
if (padapter->bSurpriseRemoved == true) {
|
||||
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
|
||||
goto out;
|
||||
}
|
||||
/* select EEPROM, reset bits, set _EECS*/
|
||||
x = rtw_read8(padapter, EE_9346CR);
|
||||
|
||||
if (padapter->bSurpriseRemoved == true) {
|
||||
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
|
||||
goto out;
|
||||
}
|
||||
|
||||
x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
|
||||
x |= _EEM1 | _EECS;
|
||||
rtw_write8(padapter, EE_9346CR, (unsigned char)x);
|
||||
|
||||
/* write the read opcode and register number in that order*/
|
||||
/* The opcode is 3bits in length, reg is 6 bits long*/
|
||||
shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
|
||||
shift_out_bits(padapter, reg, padapter->EepromAddressSize);
|
||||
|
||||
/* Now read the data (16 bits) in from the selected EEPROM word*/
|
||||
data = shift_in_bits(padapter);
|
||||
|
||||
eeprom_clean(padapter);
|
||||
out:
|
||||
_func_exit_;
|
||||
return data;
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/*From even offset*/
|
||||
void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz)
|
||||
{
|
||||
|
||||
u16 x, data16;
|
||||
u32 i;
|
||||
_func_enter_;
|
||||
if (padapter->bSurpriseRemoved == true) {
|
||||
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
|
||||
goto out;
|
||||
}
|
||||
/* select EEPROM, reset bits, set _EECS*/
|
||||
x = rtw_read8(padapter, EE_9346CR);
|
||||
|
||||
if (padapter->bSurpriseRemoved == true) {
|
||||
RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==true"));
|
||||
goto out;
|
||||
}
|
||||
|
||||
x &= ~(_EEDI | _EEDO | _EESK | _EEM0);
|
||||
x |= _EEM1 | _EECS;
|
||||
rtw_write8(padapter, EE_9346CR, (unsigned char)x);
|
||||
|
||||
/* write the read opcode and register number in that order*/
|
||||
/* The opcode is 3bits in length, reg is 6 bits long*/
|
||||
shift_out_bits(padapter, EEPROM_READ_OPCODE, 3);
|
||||
shift_out_bits(padapter, reg, padapter->EepromAddressSize);
|
||||
|
||||
|
||||
for (i = 0; i < sz; i += 2) {
|
||||
data16 = shift_in_bits(padapter);
|
||||
data[i] = data16 & 0xff;
|
||||
data[i+1] = data16 >> 8;
|
||||
}
|
||||
|
||||
eeprom_clean(padapter);
|
||||
out:
|
||||
_func_exit_;
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg)*/
|
||||
u8 eeprom_read(_adapter *padapter, u32 addr_off, u8 sz, u8 *rbuf)
|
||||
{
|
||||
u8 quotient, remainder, addr_2align_odd;
|
||||
u16 reg, stmp, i = 0, idx = 0;
|
||||
_func_enter_;
|
||||
reg = (u16)(addr_off >> 1);
|
||||
addr_2align_odd = (u8)(addr_off & 0x1);
|
||||
|
||||
/*read that start at high part: e.g 1,3,5,7,9,...*/
|
||||
if (addr_2align_odd) {
|
||||
stmp = eeprom_read16(padapter, reg);
|
||||
rbuf[idx++] = (u8) ((stmp>>8)&0xff); /*return hogh-part of the short*/
|
||||
reg++; sz--;
|
||||
}
|
||||
|
||||
quotient = sz >> 1;
|
||||
remainder = sz & 0x1;
|
||||
|
||||
for (i = 0; i < quotient; i++) {
|
||||
stmp = eeprom_read16(padapter, reg+i);
|
||||
rbuf[idx++] = (u8) (stmp&0xff);
|
||||
rbuf[idx++] = (u8) ((stmp>>8)&0xff);
|
||||
}
|
||||
|
||||
reg = reg+i;
|
||||
if (remainder) { /*end of read at lower part of short : 0,2,4,6,...*/
|
||||
stmp = eeprom_read16(padapter, reg);
|
||||
rbuf[idx] = (u8)(stmp & 0xff);
|
||||
}
|
||||
_func_exit_;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void read_eeprom_content(_adapter *padapter)
|
||||
{
|
||||
|
||||
_func_enter_;
|
||||
|
||||
|
||||
_func_exit_;
|
||||
}
|
||||
|
|
@ -0,0 +1,635 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define _RTW_EFUSE_C_
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <rtw_debug.h>
|
||||
#include <hal_data.h>
|
||||
#include <linux/jiffies.h>
|
||||
|
||||
|
||||
/*------------------------Define local variable------------------------------*/
|
||||
u8 fakeEfuseBank = 0;
|
||||
u32 fakeEfuseUsedBytes = 0;
|
||||
u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE] = {0};
|
||||
u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN] = {0};
|
||||
u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN] = {0};
|
||||
|
||||
u32 BTEfuseUsedBytes = 0;
|
||||
u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
|
||||
u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0};
|
||||
u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0};
|
||||
|
||||
u32 fakeBTEfuseUsedBytes = 0;
|
||||
u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE];
|
||||
u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0};
|
||||
u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0};
|
||||
/*------------------------Define local variable------------------------------*/
|
||||
|
||||
/* */
|
||||
#define REG_EFUSE_CTRL 0x0030
|
||||
#define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */
|
||||
/* */
|
||||
|
||||
bool
|
||||
Efuse_Read1ByteFromFakeContent(
|
||||
struct adapter *padapter,
|
||||
u16 Offset,
|
||||
u8 *Value);
|
||||
bool
|
||||
Efuse_Read1ByteFromFakeContent(
|
||||
struct adapter *padapter,
|
||||
u16 Offset,
|
||||
u8 *Value)
|
||||
{
|
||||
if (Offset >= EFUSE_MAX_HW_SIZE) {
|
||||
return false;
|
||||
}
|
||||
/* DbgPrint("Read fake content, offset = %d\n", Offset); */
|
||||
if (fakeEfuseBank == 0)
|
||||
*Value = fakeEfuseContent[Offset];
|
||||
else
|
||||
*Value = fakeBTEfuseContent[fakeEfuseBank-1][Offset];
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
Efuse_Write1ByteToFakeContent(
|
||||
struct adapter *padapter,
|
||||
u16 Offset,
|
||||
u8 Value);
|
||||
bool
|
||||
Efuse_Write1ByteToFakeContent(
|
||||
struct adapter *padapter,
|
||||
u16 Offset,
|
||||
u8 Value)
|
||||
{
|
||||
if (Offset >= EFUSE_MAX_HW_SIZE) {
|
||||
return false;
|
||||
}
|
||||
if (fakeEfuseBank == 0)
|
||||
fakeEfuseContent[Offset] = Value;
|
||||
else{
|
||||
fakeBTEfuseContent[fakeEfuseBank-1][Offset] = Value;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: Efuse_PowerSwitch
|
||||
*
|
||||
* Overview: When we want to enable write operation, we should change to
|
||||
* pwr on state. When we stop write, we should switch to 500k mode
|
||||
* and disable LDO 2.5V.
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 11/17/2008 MHC Create Version 0.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
void
|
||||
Efuse_PowerSwitch(
|
||||
struct adapter *padapter,
|
||||
u8 bWrite,
|
||||
u8 PwrState)
|
||||
{
|
||||
padapter->HalFunc.EfusePowerSwitch(padapter, bWrite, PwrState);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: Efuse_GetCurrentSize
|
||||
*
|
||||
* Overview: Get current efuse size!!!
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 11/16/2008 MHC Create Version 0.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
u16
|
||||
Efuse_GetCurrentSize(
|
||||
struct adapter *padapter,
|
||||
u8 efuseType,
|
||||
bool bPseudoTest)
|
||||
{
|
||||
u16 ret = 0;
|
||||
|
||||
ret = padapter->HalFunc.EfuseGetCurrentSize(padapter, efuseType, bPseudoTest);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */
|
||||
u8
|
||||
Efuse_CalculateWordCnts(u8 word_en)
|
||||
{
|
||||
u8 word_cnts = 0;
|
||||
if (!(word_en & BIT(0)))
|
||||
word_cnts++; /* 0 : write enable */
|
||||
if (!(word_en & BIT(1)))
|
||||
word_cnts++;
|
||||
if (!(word_en & BIT(2)))
|
||||
word_cnts++;
|
||||
if (!(word_en & BIT(3)))
|
||||
word_cnts++;
|
||||
return word_cnts;
|
||||
}
|
||||
|
||||
/* */
|
||||
/* Description: */
|
||||
/* 1. Execute E-Fuse read byte operation according as map offset and */
|
||||
/* save to E-Fuse table. */
|
||||
/* 2. Refered from SD1 Richard. */
|
||||
/* */
|
||||
/* Assumption: */
|
||||
/* 1. Boot from E-Fuse and successfully auto-load. */
|
||||
/* 2. PASSIVE_LEVEL (USB interface) */
|
||||
/* */
|
||||
/* Created by Roger, 2008.10.21. */
|
||||
/* */
|
||||
/* 2008/12/12 MH 1. Reorganize code flow and reserve bytes. and add description. */
|
||||
/* 2. Add efuse utilization collect. */
|
||||
/* 2008/12/22 MH Read Efuse must check if we write section 1 data again!!! Sec1 */
|
||||
/* write addr must be after sec5. */
|
||||
/* */
|
||||
|
||||
void
|
||||
efuse_ReadEFuse(
|
||||
struct adapter *Adapter,
|
||||
u8 efuseType,
|
||||
u16 _offset,
|
||||
u16 _size_byte,
|
||||
u8 *pbuf,
|
||||
bool bPseudoTest
|
||||
);
|
||||
void
|
||||
efuse_ReadEFuse(
|
||||
struct adapter *Adapter,
|
||||
u8 efuseType,
|
||||
u16 _offset,
|
||||
u16 _size_byte,
|
||||
u8 *pbuf,
|
||||
bool bPseudoTest
|
||||
)
|
||||
{
|
||||
Adapter->HalFunc.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
|
||||
}
|
||||
|
||||
void
|
||||
EFUSE_GetEfuseDefinition(
|
||||
struct adapter *padapter,
|
||||
u8 efuseType,
|
||||
u8 type,
|
||||
void *pOut,
|
||||
bool bPseudoTest
|
||||
)
|
||||
{
|
||||
padapter->HalFunc.EFUSEGetEfuseDefinition(padapter, efuseType, type, pOut, bPseudoTest);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: EFUSE_Read1Byte
|
||||
*
|
||||
* Overview: Copy from WMAC fot EFUSE read 1 byte.
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 09/23/2008 MHC Copy from WMAC.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
u8
|
||||
EFUSE_Read1Byte(
|
||||
struct adapter *Adapter,
|
||||
u16 Address)
|
||||
{
|
||||
u8 data;
|
||||
u8 Bytetemp = {0x00};
|
||||
u8 temp = {0x00};
|
||||
u32 k = 0;
|
||||
u16 contentLen = 0;
|
||||
|
||||
EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (void *)&contentLen, false);
|
||||
|
||||
if (Address < contentLen) {/* E-fuse 512Byte */
|
||||
/* Write E-fuse Register address bit0~7 */
|
||||
temp = Address & 0xFF;
|
||||
rtw_write8(Adapter, EFUSE_CTRL+1, temp);
|
||||
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+2);
|
||||
/* Write E-fuse Register address bit8~9 */
|
||||
temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC);
|
||||
rtw_write8(Adapter, EFUSE_CTRL+2, temp);
|
||||
|
||||
/* Write 0x30[31]= 0 */
|
||||
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
|
||||
temp = Bytetemp & 0x7F;
|
||||
rtw_write8(Adapter, EFUSE_CTRL+3, temp);
|
||||
|
||||
/* Wait Write-ready (0x30[31]= 1) */
|
||||
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
|
||||
while (!(Bytetemp & 0x80)) {
|
||||
Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3);
|
||||
k++;
|
||||
if (k == 1000) {
|
||||
k = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
data = rtw_read8(Adapter, EFUSE_CTRL);
|
||||
return data;
|
||||
} else
|
||||
return 0xFF;
|
||||
|
||||
} /* EFUSE_Read1Byte */
|
||||
|
||||
/* 11/16/2008 MH Read one byte from real Efuse. */
|
||||
u8
|
||||
efuse_OneByteRead(
|
||||
struct adapter *padapter,
|
||||
u16 addr,
|
||||
u8 *data,
|
||||
bool bPseudoTest)
|
||||
{
|
||||
u32 tmpidx = 0;
|
||||
u8 bResult;
|
||||
u8 readbyte;
|
||||
|
||||
/* DBG_871X("===> EFUSE_OneByteRead(), addr = %x\n", addr); */
|
||||
/* DBG_871X("===> EFUSE_OneByteRead() start, 0x34 = 0x%X\n", rtw_read32(padapter, EFUSE_TEST)); */
|
||||
|
||||
if (bPseudoTest) {
|
||||
bResult = Efuse_Read1ByteFromFakeContent(padapter, addr, data);
|
||||
return bResult;
|
||||
}
|
||||
|
||||
/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
|
||||
/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
|
||||
/* PHY_SetMacReg(padapter, 0x34, BIT11, 0); */
|
||||
rtw_write16(padapter, 0x34, rtw_read16(padapter, 0x34) & (~BIT11));
|
||||
|
||||
/* -----------------e-fuse reg ctrl --------------------------------- */
|
||||
/* address */
|
||||
rtw_write8(padapter, EFUSE_CTRL+1, (u8)(addr&0xff));
|
||||
rtw_write8(padapter, EFUSE_CTRL+2, ((u8)((addr>>8) & 0x03)) |
|
||||
(rtw_read8(padapter, EFUSE_CTRL+2)&0xFC));
|
||||
|
||||
/* rtw_write8(padapter, EFUSE_CTRL+3, 0x72); read cmd */
|
||||
/* Write bit 32 0 */
|
||||
readbyte = rtw_read8(padapter, EFUSE_CTRL+3);
|
||||
rtw_write8(padapter, EFUSE_CTRL+3, (readbyte & 0x7f));
|
||||
|
||||
while (!(0x80 & rtw_read8(padapter, EFUSE_CTRL+3)) && (tmpidx < 1000)) {
|
||||
mdelay(1);
|
||||
tmpidx++;
|
||||
}
|
||||
if (tmpidx < 100) {
|
||||
*data = rtw_read8(padapter, EFUSE_CTRL);
|
||||
bResult = true;
|
||||
} else{
|
||||
*data = 0xff;
|
||||
bResult = false;
|
||||
DBG_871X("%s: [ERROR] addr = 0x%x bResult =%d time out 1s !!!\n", __func__, addr, bResult);
|
||||
DBG_871X("%s: [ERROR] EFUSE_CTRL = 0x%08x !!!\n", __func__, rtw_read32(padapter, EFUSE_CTRL));
|
||||
}
|
||||
|
||||
return bResult;
|
||||
}
|
||||
|
||||
/* 11/16/2008 MH Write one byte to reald Efuse. */
|
||||
u8
|
||||
efuse_OneByteWrite(
|
||||
struct adapter *padapter,
|
||||
u16 addr,
|
||||
u8 data,
|
||||
bool bPseudoTest)
|
||||
{
|
||||
u8 tmpidx = 0;
|
||||
u8 bResult = false;
|
||||
u32 efuseValue = 0;
|
||||
|
||||
/* DBG_871X("===> EFUSE_OneByteWrite(), addr = %x data =%x\n", addr, data); */
|
||||
/* DBG_871X("===> EFUSE_OneByteWrite() start, 0x34 = 0x%X\n", rtw_read32(padapter, EFUSE_TEST)); */
|
||||
|
||||
if (bPseudoTest) {
|
||||
bResult = Efuse_Write1ByteToFakeContent(padapter, addr, data);
|
||||
return bResult;
|
||||
}
|
||||
|
||||
|
||||
/* -----------------e-fuse reg ctrl --------------------------------- */
|
||||
/* address */
|
||||
|
||||
|
||||
efuseValue = rtw_read32(padapter, EFUSE_CTRL);
|
||||
efuseValue |= (BIT21|BIT31);
|
||||
efuseValue &= ~(0x3FFFF);
|
||||
efuseValue |= ((addr<<8 | data) & 0x3FFFF);
|
||||
|
||||
|
||||
/* <20130227, Kordan> 8192E MP chip A-cut had better not set 0x34[11] until B-Cut. */
|
||||
|
||||
/* <20130121, Kordan> For SMIC EFUSE specificatoin. */
|
||||
/* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */
|
||||
/* PHY_SetMacReg(padapter, 0x34, BIT11, 1); */
|
||||
rtw_write16(padapter, 0x34, rtw_read16(padapter, 0x34) | (BIT11));
|
||||
rtw_write32(padapter, EFUSE_CTRL, 0x90600000|((addr<<8 | data)));
|
||||
|
||||
while ((0x80 & rtw_read8(padapter, EFUSE_CTRL+3)) && (tmpidx < 100)) {
|
||||
mdelay(1);
|
||||
tmpidx++;
|
||||
}
|
||||
|
||||
if (tmpidx < 100) {
|
||||
bResult = true;
|
||||
} else{
|
||||
bResult = false;
|
||||
DBG_871X("%s: [ERROR] addr = 0x%x , efuseValue = 0x%x , bResult =%d time out 1s !!!\n",
|
||||
__func__, addr, efuseValue, bResult);
|
||||
DBG_871X("%s: [ERROR] EFUSE_CTRL = 0x%08x !!!\n", __func__, rtw_read32(padapter, EFUSE_CTRL));
|
||||
}
|
||||
|
||||
/* disable Efuse program enable */
|
||||
PHY_SetMacReg(padapter, EFUSE_TEST, BIT(11), 0);
|
||||
|
||||
return bResult;
|
||||
}
|
||||
|
||||
int
|
||||
Efuse_PgPacketRead(struct adapter *padapter,
|
||||
u8 offset,
|
||||
u8 *data,
|
||||
bool bPseudoTest)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
ret = padapter->HalFunc.Efuse_PgPacketRead(padapter, offset, data, bPseudoTest);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
Efuse_PgPacketWrite(struct adapter *padapter,
|
||||
u8 offset,
|
||||
u8 word_en,
|
||||
u8 *data,
|
||||
bool bPseudoTest)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = padapter->HalFunc.Efuse_PgPacketWrite(padapter, offset, word_en, data, bPseudoTest);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: efuse_WordEnableDataRead
|
||||
*
|
||||
* Overview: Read allowed word in current efuse section data.
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 11/16/2008 MHC Create Version 0.
|
||||
* 11/21/2008 MHC Fix Write bug when we only enable late word.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
void
|
||||
efuse_WordEnableDataRead(u8 word_en,
|
||||
u8 *sourdata,
|
||||
u8 *targetdata)
|
||||
{
|
||||
if (!(word_en&BIT(0))) {
|
||||
targetdata[0] = sourdata[0];
|
||||
targetdata[1] = sourdata[1];
|
||||
}
|
||||
if (!(word_en&BIT(1))) {
|
||||
targetdata[2] = sourdata[2];
|
||||
targetdata[3] = sourdata[3];
|
||||
}
|
||||
if (!(word_en&BIT(2))) {
|
||||
targetdata[4] = sourdata[4];
|
||||
targetdata[5] = sourdata[5];
|
||||
}
|
||||
if (!(word_en&BIT(3))) {
|
||||
targetdata[6] = sourdata[6];
|
||||
targetdata[7] = sourdata[7];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
u8
|
||||
Efuse_WordEnableDataWrite(struct adapter *padapter,
|
||||
u16 efuse_addr,
|
||||
u8 word_en,
|
||||
u8 *data,
|
||||
bool bPseudoTest)
|
||||
{
|
||||
u8 ret = 0;
|
||||
|
||||
ret = padapter->HalFunc.Efuse_WordEnableDataWrite(padapter, efuse_addr, word_en, data, bPseudoTest);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: Efuse_ReadAllMap
|
||||
*
|
||||
* Overview: Read All Efuse content
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 11/11/2008 MHC Create Version 0.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
void
|
||||
Efuse_ReadAllMap(
|
||||
struct adapter *padapter,
|
||||
u8 efuseType,
|
||||
u8 *Efuse,
|
||||
bool bPseudoTest);
|
||||
void
|
||||
Efuse_ReadAllMap(
|
||||
struct adapter *padapter,
|
||||
u8 efuseType,
|
||||
u8 *Efuse,
|
||||
bool bPseudoTest)
|
||||
{
|
||||
u16 mapLen = 0;
|
||||
|
||||
Efuse_PowerSwitch(padapter, false, true);
|
||||
|
||||
EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);
|
||||
|
||||
efuse_ReadEFuse(padapter, efuseType, 0, mapLen, Efuse, bPseudoTest);
|
||||
|
||||
Efuse_PowerSwitch(padapter, false, false);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: efuse_ShadowRead1Byte
|
||||
* efuse_ShadowRead2Byte
|
||||
* efuse_ShadowRead4Byte
|
||||
*
|
||||
* Overview: Read from efuse init map by one/two/four bytes !!!!!
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 11/12/2008 MHC Create Version 0.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void
|
||||
efuse_ShadowRead1Byte(
|
||||
struct adapter *padapter,
|
||||
u16 Offset,
|
||||
u8 *Value)
|
||||
{
|
||||
struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
|
||||
|
||||
*Value = pEEPROM->efuse_eeprom_data[Offset];
|
||||
|
||||
} /* EFUSE_ShadowRead1Byte */
|
||||
|
||||
/* Read Two Bytes */
|
||||
static void
|
||||
efuse_ShadowRead2Byte(
|
||||
struct adapter *padapter,
|
||||
u16 Offset,
|
||||
u16 *Value)
|
||||
{
|
||||
struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
|
||||
|
||||
*Value = pEEPROM->efuse_eeprom_data[Offset];
|
||||
*Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8;
|
||||
|
||||
} /* EFUSE_ShadowRead2Byte */
|
||||
|
||||
/* Read Four Bytes */
|
||||
static void
|
||||
efuse_ShadowRead4Byte(
|
||||
struct adapter *padapter,
|
||||
u16 Offset,
|
||||
u32 *Value)
|
||||
{
|
||||
struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
|
||||
|
||||
*Value = pEEPROM->efuse_eeprom_data[Offset];
|
||||
*Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8;
|
||||
*Value |= pEEPROM->efuse_eeprom_data[Offset+2]<<16;
|
||||
*Value |= pEEPROM->efuse_eeprom_data[Offset+3]<<24;
|
||||
|
||||
} /* efuse_ShadowRead4Byte */
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: EFUSE_ShadowMapUpdate
|
||||
*
|
||||
* Overview: Transfer current EFUSE content to shadow init and modify map.
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 11/13/2008 MHC Create Version 0.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
void EFUSE_ShadowMapUpdate(
|
||||
struct adapter *padapter,
|
||||
u8 efuseType,
|
||||
bool bPseudoTest)
|
||||
{
|
||||
struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
|
||||
u16 mapLen = 0;
|
||||
|
||||
EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, bPseudoTest);
|
||||
|
||||
if (pEEPROM->bautoload_fail_flag == true) {
|
||||
memset(pEEPROM->efuse_eeprom_data, 0xFF, mapLen);
|
||||
} else{
|
||||
Efuse_ReadAllMap(padapter, efuseType, pEEPROM->efuse_eeprom_data, bPseudoTest);
|
||||
}
|
||||
|
||||
/* PlatformMoveMemory((void *)&pHalData->EfuseMap[EFUSE_MODIFY_MAP][0], */
|
||||
/* void *)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen); */
|
||||
} /* EFUSE_ShadowMapUpdate */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: EFUSE_ShadowRead
|
||||
*
|
||||
* Overview: Read from efuse init map !!!!!
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 11/12/2008 MHC Create Version 0.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
void
|
||||
EFUSE_ShadowRead(
|
||||
struct adapter *padapter,
|
||||
u8 Type,
|
||||
u16 Offset,
|
||||
u32 *Value)
|
||||
{
|
||||
if (Type == 1)
|
||||
efuse_ShadowRead1Byte(padapter, Offset, (u8 *)Value);
|
||||
else if (Type == 2)
|
||||
efuse_ShadowRead2Byte(padapter, Offset, (u16 *)Value);
|
||||
else if (Type == 4)
|
||||
efuse_ShadowRead4Byte(padapter, Offset, (u32 *)Value);
|
||||
|
||||
} /* EFUSE_ShadowRead*/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,203 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
|
||||
The purpose of rtw_io.c
|
||||
|
||||
a. provides the API
|
||||
|
||||
b. provides the protocol engine
|
||||
|
||||
c. provides the software interface between caller and the hardware interface
|
||||
|
||||
|
||||
Compiler Flag Option:
|
||||
|
||||
1. CONFIG_SDIO_HCI:
|
||||
a. USE_SYNC_IRP: Only sync operations are provided.
|
||||
b. USE_ASYNC_IRP:Both sync/async operations are provided.
|
||||
|
||||
jackson@realtek.com.tw
|
||||
|
||||
*/
|
||||
|
||||
#define _RTW_IO_C_
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <rtw_debug.h>
|
||||
|
||||
#define rtw_le16_to_cpu(val) val
|
||||
#define rtw_le32_to_cpu(val) val
|
||||
#define rtw_cpu_to_le16(val) val
|
||||
#define rtw_cpu_to_le32(val) val
|
||||
|
||||
u8 _rtw_read8(struct adapter *adapter, u32 addr)
|
||||
{
|
||||
u8 r_val;
|
||||
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
|
||||
struct io_priv *pio_priv = &adapter->iopriv;
|
||||
struct intf_hdl *pintfhdl = &(pio_priv->intf);
|
||||
u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr);
|
||||
|
||||
_read8 = pintfhdl->io_ops._read8;
|
||||
|
||||
r_val = _read8(pintfhdl, addr);
|
||||
return r_val;
|
||||
}
|
||||
|
||||
u16 _rtw_read16(struct adapter *adapter, u32 addr)
|
||||
{
|
||||
u16 r_val;
|
||||
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
|
||||
struct io_priv *pio_priv = &adapter->iopriv;
|
||||
struct intf_hdl *pintfhdl = &(pio_priv->intf);
|
||||
u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr);
|
||||
|
||||
_read16 = pintfhdl->io_ops._read16;
|
||||
|
||||
r_val = _read16(pintfhdl, addr);
|
||||
return rtw_le16_to_cpu(r_val);
|
||||
}
|
||||
|
||||
u32 _rtw_read32(struct adapter *adapter, u32 addr)
|
||||
{
|
||||
u32 r_val;
|
||||
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
|
||||
struct io_priv *pio_priv = &adapter->iopriv;
|
||||
struct intf_hdl *pintfhdl = &(pio_priv->intf);
|
||||
u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr);
|
||||
|
||||
_read32 = pintfhdl->io_ops._read32;
|
||||
|
||||
r_val = _read32(pintfhdl, addr);
|
||||
return rtw_le32_to_cpu(r_val);
|
||||
|
||||
}
|
||||
|
||||
int _rtw_write8(struct adapter *adapter, u32 addr, u8 val)
|
||||
{
|
||||
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
|
||||
struct io_priv *pio_priv = &adapter->iopriv;
|
||||
struct intf_hdl *pintfhdl = &(pio_priv->intf);
|
||||
int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val);
|
||||
int ret;
|
||||
|
||||
_write8 = pintfhdl->io_ops._write8;
|
||||
|
||||
ret = _write8(pintfhdl, addr, val);
|
||||
|
||||
return RTW_STATUS_CODE(ret);
|
||||
}
|
||||
int _rtw_write16(struct adapter *adapter, u32 addr, u16 val)
|
||||
{
|
||||
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
|
||||
struct io_priv *pio_priv = &adapter->iopriv;
|
||||
struct intf_hdl *pintfhdl = &(pio_priv->intf);
|
||||
int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val);
|
||||
int ret;
|
||||
|
||||
_write16 = pintfhdl->io_ops._write16;
|
||||
|
||||
ret = _write16(pintfhdl, addr, val);
|
||||
return RTW_STATUS_CODE(ret);
|
||||
}
|
||||
int _rtw_write32(struct adapter *adapter, u32 addr, u32 val)
|
||||
{
|
||||
/* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */
|
||||
struct io_priv *pio_priv = &adapter->iopriv;
|
||||
struct intf_hdl *pintfhdl = &(pio_priv->intf);
|
||||
int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val);
|
||||
int ret;
|
||||
|
||||
_write32 = pintfhdl->io_ops._write32;
|
||||
|
||||
ret = _write32(pintfhdl, addr, val);
|
||||
|
||||
return RTW_STATUS_CODE(ret);
|
||||
}
|
||||
|
||||
u8 _rtw_sd_f0_read8(struct adapter *adapter, u32 addr)
|
||||
{
|
||||
u8 r_val = 0x00;
|
||||
struct io_priv *pio_priv = &adapter->iopriv;
|
||||
struct intf_hdl *pintfhdl = &(pio_priv->intf);
|
||||
u8 (*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr);
|
||||
|
||||
_sd_f0_read8 = pintfhdl->io_ops._sd_f0_read8;
|
||||
|
||||
if (_sd_f0_read8)
|
||||
r_val = _sd_f0_read8(pintfhdl, addr);
|
||||
else
|
||||
DBG_871X_LEVEL(_drv_warning_, FUNC_ADPT_FMT" _sd_f0_read8 callback is NULL\n", FUNC_ADPT_ARG(adapter));
|
||||
|
||||
return r_val;
|
||||
}
|
||||
|
||||
u32 _rtw_write_port(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem)
|
||||
{
|
||||
u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
|
||||
struct io_priv *pio_priv = &adapter->iopriv;
|
||||
struct intf_hdl *pintfhdl = &(pio_priv->intf);
|
||||
u32 ret = _SUCCESS;
|
||||
|
||||
_write_port = pintfhdl->io_ops._write_port;
|
||||
|
||||
ret = _write_port(pintfhdl, addr, cnt, pmem);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int rtw_init_io_priv(struct adapter *padapter, void (*set_intf_ops)(struct adapter *padapter, struct _io_ops *pops))
|
||||
{
|
||||
struct io_priv *piopriv = &padapter->iopriv;
|
||||
struct intf_hdl *pintf = &piopriv->intf;
|
||||
|
||||
if (set_intf_ops == NULL)
|
||||
return _FAIL;
|
||||
|
||||
piopriv->padapter = padapter;
|
||||
pintf->padapter = padapter;
|
||||
pintf->pintf_dev = adapter_to_dvobj(padapter);
|
||||
|
||||
set_intf_ops(padapter, &pintf->io_ops);
|
||||
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Increase and check if the continual_io_error of this @param dvobjprive is larger than MAX_CONTINUAL_IO_ERR
|
||||
* @return true:
|
||||
* @return false:
|
||||
*/
|
||||
int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj)
|
||||
{
|
||||
int ret = false;
|
||||
int value = atomic_inc_return(&dvobj->continual_io_error);
|
||||
if (value > MAX_CONTINUAL_IO_ERR) {
|
||||
DBG_871X("[dvobj:%p][ERROR] continual_io_error:%d > %d\n", dvobj, value, MAX_CONTINUAL_IO_ERR);
|
||||
ret = true;
|
||||
} else {
|
||||
/* DBG_871X("[dvobj:%p] continual_io_error:%d\n", dvobj, value); */
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the continual_io_error of this @param dvobjprive to 0
|
||||
*/
|
||||
void rtw_reset_continual_io_error(struct dvobj_priv *dvobj)
|
||||
{
|
||||
atomic_set(&dvobj->continual_io_error, 0);
|
||||
}
|
||||
|
|
@ -0,0 +1,696 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define _RTW_IOCTL_SET_C_
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <rtw_debug.h>
|
||||
|
||||
#define IS_MAC_ADDRESS_BROADCAST(addr) \
|
||||
(\
|
||||
((addr[0] == 0xff) && (addr[1] == 0xff) && \
|
||||
(addr[2] == 0xff) && (addr[3] == 0xff) && \
|
||||
(addr[4] == 0xff) && (addr[5] == 0xff)) ? true : false \
|
||||
)
|
||||
|
||||
u8 rtw_validate_bssid(u8 *bssid)
|
||||
{
|
||||
u8 ret = true;
|
||||
|
||||
if (is_zero_mac_addr(bssid)
|
||||
|| is_broadcast_mac_addr(bssid)
|
||||
|| is_multicast_mac_addr(bssid)
|
||||
) {
|
||||
ret = false;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
u8 rtw_validate_ssid(struct ndis_802_11_ssid *ssid)
|
||||
{
|
||||
u8 ret = true;
|
||||
|
||||
if (ssid->SsidLength > 32) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid length >32\n"));
|
||||
ret = false;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_VALIDATE_SSID
|
||||
for (i = 0; i < ssid->SsidLength; i++) {
|
||||
/* wifi, printable ascii code must be supported */
|
||||
if (!((ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e))) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid has nonprintabl ascii\n"));
|
||||
ret = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_VALIDATE_SSID */
|
||||
|
||||
exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
u8 rtw_do_join(struct adapter *padapter);
|
||||
u8 rtw_do_join(struct adapter *padapter)
|
||||
{
|
||||
struct list_head *plist, *phead;
|
||||
u8 *pibss = NULL;
|
||||
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
|
||||
struct __queue *queue = &(pmlmepriv->scanned_queue);
|
||||
u8 ret = _SUCCESS;
|
||||
|
||||
spin_lock_bh(&(pmlmepriv->scanned_queue.lock));
|
||||
phead = get_list_head(queue);
|
||||
plist = get_next(phead);
|
||||
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("\n rtw_do_join: phead = %p; plist = %p\n\n\n", phead, plist));
|
||||
|
||||
pmlmepriv->cur_network.join_res = -2;
|
||||
|
||||
set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
|
||||
|
||||
pmlmepriv->pscanned = plist;
|
||||
|
||||
pmlmepriv->to_join = true;
|
||||
|
||||
if (list_empty(&queue->queue)) {
|
||||
spin_unlock_bh(&(pmlmepriv->scanned_queue.lock));
|
||||
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
|
||||
|
||||
/* when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty */
|
||||
/* we try to issue sitesurvey firstly */
|
||||
|
||||
if (pmlmepriv->LinkDetectInfo.bBusyTraffic == false
|
||||
|| rtw_to_roam(padapter) > 0
|
||||
) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_do_join(): site survey if scanned_queue is empty\n."));
|
||||
/* submit site_survey_cmd */
|
||||
ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0);
|
||||
if (_SUCCESS != ret) {
|
||||
pmlmepriv->to_join = false;
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_do_join(): site survey return error\n."));
|
||||
}
|
||||
} else{
|
||||
pmlmepriv->to_join = false;
|
||||
ret = _FAIL;
|
||||
}
|
||||
|
||||
goto exit;
|
||||
} else{
|
||||
int select_ret;
|
||||
spin_unlock_bh(&(pmlmepriv->scanned_queue.lock));
|
||||
select_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv);
|
||||
if (select_ret == _SUCCESS) {
|
||||
pmlmepriv->to_join = false;
|
||||
_set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT);
|
||||
} else{
|
||||
if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == true) {
|
||||
/* submit createbss_cmd to change to a ADHOC_MASTER */
|
||||
|
||||
/* pmlmepriv->lock has been acquired by caller... */
|
||||
struct wlan_bssid_ex *pdev_network = &(padapter->registrypriv.dev_network);
|
||||
|
||||
pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;
|
||||
|
||||
pibss = padapter->registrypriv.dev_network.MacAddress;
|
||||
|
||||
memset(&pdev_network->Ssid, 0, sizeof(struct ndis_802_11_ssid));
|
||||
memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(struct ndis_802_11_ssid));
|
||||
|
||||
rtw_update_registrypriv_dev_network(padapter);
|
||||
|
||||
rtw_generate_random_ibss(pibss);
|
||||
|
||||
if (rtw_createbss_cmd(padapter) != _SUCCESS) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("***Error =>do_goin: rtw_createbss_cmd status FAIL***\n "));
|
||||
ret = false;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
pmlmepriv->to_join = false;
|
||||
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("***Error => rtw_select_and_join_from_scanned_queue FAIL under STA_Mode***\n "));
|
||||
|
||||
} else{
|
||||
/* can't associate ; reset under-linking */
|
||||
_clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
|
||||
|
||||
/* when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue */
|
||||
/* we try to issue sitesurvey firstly */
|
||||
if (pmlmepriv->LinkDetectInfo.bBusyTraffic == false
|
||||
|| rtw_to_roam(padapter) > 0
|
||||
) {
|
||||
/* DBG_871X("rtw_do_join() when no desired bss in scanning queue\n"); */
|
||||
ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0);
|
||||
if (_SUCCESS != ret) {
|
||||
pmlmepriv->to_join = false;
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("do_join(): site survey return error\n."));
|
||||
}
|
||||
} else{
|
||||
ret = _FAIL;
|
||||
pmlmepriv->to_join = false;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
u8 rtw_set_802_11_bssid(struct adapter *padapter, u8 *bssid)
|
||||
{
|
||||
u8 status = _SUCCESS;
|
||||
|
||||
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
|
||||
|
||||
DBG_871X_LEVEL(_drv_always_, "set bssid:%pM\n", bssid);
|
||||
|
||||
if ((bssid[0] == 0x00 && bssid[1] == 0x00 && bssid[2] == 0x00 && bssid[3] == 0x00 && bssid[4] == 0x00 && bssid[5] == 0x00) ||
|
||||
(bssid[0] == 0xFF && bssid[1] == 0xFF && bssid[2] == 0xFF && bssid[3] == 0xFF && bssid[4] == 0xFF && bssid[5] == 0xFF)) {
|
||||
status = _FAIL;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
spin_lock_bh(&pmlmepriv->lock);
|
||||
|
||||
|
||||
DBG_871X("Set BSSID under fw_state = 0x%08x\n", get_fwstate(pmlmepriv));
|
||||
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true) {
|
||||
goto handle_tkip_countermeasure;
|
||||
} else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == true) {
|
||||
goto release_mlme_lock;
|
||||
}
|
||||
|
||||
if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == true) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_bssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n"));
|
||||
|
||||
if (!memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN)) {
|
||||
if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == false)
|
||||
goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
|
||||
} else {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("Set BSSID not the same bssid\n"));
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_bssid ="MAC_FMT"\n", MAC_ARG(bssid)));
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("cur_bssid ="MAC_FMT"\n", MAC_ARG(pmlmepriv->cur_network.network.MacAddress)));
|
||||
|
||||
rtw_disassoc_cmd(padapter, 0, true);
|
||||
|
||||
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
|
||||
rtw_indicate_disconnect(padapter);
|
||||
|
||||
rtw_free_assoc_resources(padapter, 1);
|
||||
|
||||
if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true)) {
|
||||
_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
|
||||
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
handle_tkip_countermeasure:
|
||||
if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
|
||||
status = _FAIL;
|
||||
goto release_mlme_lock;
|
||||
}
|
||||
|
||||
memset(&pmlmepriv->assoc_ssid, 0, sizeof(struct ndis_802_11_ssid));
|
||||
memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
|
||||
pmlmepriv->assoc_by_bssid = true;
|
||||
|
||||
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true) {
|
||||
pmlmepriv->to_join = true;
|
||||
} else {
|
||||
status = rtw_do_join(padapter);
|
||||
}
|
||||
|
||||
release_mlme_lock:
|
||||
spin_unlock_bh(&pmlmepriv->lock);
|
||||
|
||||
exit:
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
|
||||
("rtw_set_802_11_bssid: status =%d\n", status));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
u8 rtw_set_802_11_ssid(struct adapter *padapter, struct ndis_802_11_ssid *ssid)
|
||||
{
|
||||
u8 status = _SUCCESS;
|
||||
|
||||
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
|
||||
struct wlan_network *pnetwork = &pmlmepriv->cur_network;
|
||||
|
||||
DBG_871X_LEVEL(_drv_always_, "set ssid [%s] fw_state = 0x%08x\n",
|
||||
ssid->Ssid, get_fwstate(pmlmepriv));
|
||||
|
||||
if (padapter->hw_init_completed == false) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
|
||||
("set_ssid: hw_init_completed ==false =>exit!!!\n"));
|
||||
status = _FAIL;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
spin_lock_bh(&pmlmepriv->lock);
|
||||
|
||||
DBG_871X("Set SSID under fw_state = 0x%08x\n", get_fwstate(pmlmepriv));
|
||||
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true) {
|
||||
goto handle_tkip_countermeasure;
|
||||
} else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == true) {
|
||||
goto release_mlme_lock;
|
||||
}
|
||||
|
||||
if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == true) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_,
|
||||
("set_ssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n"));
|
||||
|
||||
if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) &&
|
||||
(!memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength))) {
|
||||
if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == false)) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
|
||||
("Set SSID is the same ssid, fw_state = 0x%08x\n",
|
||||
get_fwstate(pmlmepriv)));
|
||||
|
||||
if (rtw_is_same_ibss(padapter, pnetwork) == false) {
|
||||
/* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */
|
||||
rtw_disassoc_cmd(padapter, 0, true);
|
||||
|
||||
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
|
||||
rtw_indicate_disconnect(padapter);
|
||||
|
||||
rtw_free_assoc_resources(padapter, 1);
|
||||
|
||||
if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true) {
|
||||
_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
|
||||
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
|
||||
}
|
||||
} else{
|
||||
goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */
|
||||
}
|
||||
} else {
|
||||
rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 1);
|
||||
}
|
||||
} else{
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("Set SSID not the same ssid\n"));
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_ssid =[%s] len = 0x%x\n", ssid->Ssid, (unsigned int)ssid->SsidLength));
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("assoc_ssid =[%s] len = 0x%x\n", pmlmepriv->assoc_ssid.Ssid, (unsigned int)pmlmepriv->assoc_ssid.SsidLength));
|
||||
|
||||
rtw_disassoc_cmd(padapter, 0, true);
|
||||
|
||||
if (check_fwstate(pmlmepriv, _FW_LINKED) == true)
|
||||
rtw_indicate_disconnect(padapter);
|
||||
|
||||
rtw_free_assoc_resources(padapter, 1);
|
||||
|
||||
if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true) {
|
||||
_clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
|
||||
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
handle_tkip_countermeasure:
|
||||
if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
|
||||
status = _FAIL;
|
||||
goto release_mlme_lock;
|
||||
}
|
||||
|
||||
if (rtw_validate_ssid(ssid) == false) {
|
||||
status = _FAIL;
|
||||
goto release_mlme_lock;
|
||||
}
|
||||
|
||||
memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(struct ndis_802_11_ssid));
|
||||
pmlmepriv->assoc_by_bssid = false;
|
||||
|
||||
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true) {
|
||||
pmlmepriv->to_join = true;
|
||||
} else {
|
||||
status = rtw_do_join(padapter);
|
||||
}
|
||||
|
||||
release_mlme_lock:
|
||||
spin_unlock_bh(&pmlmepriv->lock);
|
||||
|
||||
exit:
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
|
||||
("-rtw_set_802_11_ssid: status =%d\n", status));
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
u8 rtw_set_802_11_connect(struct adapter *padapter, u8 *bssid, struct ndis_802_11_ssid *ssid)
|
||||
{
|
||||
u8 status = _SUCCESS;
|
||||
bool bssid_valid = true;
|
||||
bool ssid_valid = true;
|
||||
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
|
||||
|
||||
if (!ssid || rtw_validate_ssid(ssid) == false)
|
||||
ssid_valid = false;
|
||||
|
||||
if (!bssid || rtw_validate_bssid(bssid) == false)
|
||||
bssid_valid = false;
|
||||
|
||||
if (ssid_valid == false && bssid_valid == false) {
|
||||
DBG_871X(FUNC_ADPT_FMT" ssid:%p, ssid_valid:%d, bssid:%p, bssid_valid:%d\n",
|
||||
FUNC_ADPT_ARG(padapter), ssid, ssid_valid, bssid, bssid_valid);
|
||||
status = _FAIL;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (padapter->hw_init_completed == false) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_,
|
||||
("set_ssid: hw_init_completed ==false =>exit!!!\n"));
|
||||
status = _FAIL;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
spin_lock_bh(&pmlmepriv->lock);
|
||||
|
||||
DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" fw_state = 0x%08x\n",
|
||||
FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv));
|
||||
|
||||
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true) {
|
||||
goto handle_tkip_countermeasure;
|
||||
} else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == true) {
|
||||
goto release_mlme_lock;
|
||||
}
|
||||
|
||||
handle_tkip_countermeasure:
|
||||
if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) {
|
||||
status = _FAIL;
|
||||
goto release_mlme_lock;
|
||||
}
|
||||
|
||||
if (ssid && ssid_valid)
|
||||
memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(struct ndis_802_11_ssid));
|
||||
else
|
||||
memset(&pmlmepriv->assoc_ssid, 0, sizeof(struct ndis_802_11_ssid));
|
||||
|
||||
if (bssid && bssid_valid) {
|
||||
memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN);
|
||||
pmlmepriv->assoc_by_bssid = true;
|
||||
} else {
|
||||
pmlmepriv->assoc_by_bssid = false;
|
||||
}
|
||||
|
||||
if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == true) {
|
||||
pmlmepriv->to_join = true;
|
||||
} else {
|
||||
status = rtw_do_join(padapter);
|
||||
}
|
||||
|
||||
release_mlme_lock:
|
||||
spin_unlock_bh(&pmlmepriv->lock);
|
||||
|
||||
exit:
|
||||
return status;
|
||||
}
|
||||
|
||||
u8 rtw_set_802_11_infrastructure_mode(struct adapter *padapter,
|
||||
enum NDIS_802_11_NETWORK_INFRASTRUCTURE networktype)
|
||||
{
|
||||
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
|
||||
struct wlan_network *cur_network = &pmlmepriv->cur_network;
|
||||
enum NDIS_802_11_NETWORK_INFRASTRUCTURE *pold_state = &(cur_network->network.InfrastructureMode);
|
||||
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_notice_,
|
||||
("+rtw_set_802_11_infrastructure_mode: old =%d new =%d fw_state = 0x%08x\n",
|
||||
*pold_state, networktype, get_fwstate(pmlmepriv)));
|
||||
|
||||
if (*pold_state != networktype) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, (" change mode!"));
|
||||
/* DBG_871X("change mode, old_mode =%d, new_mode =%d, fw_state = 0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); */
|
||||
|
||||
if (*pold_state == Ndis802_11APMode) {
|
||||
/* change to other mode from Ndis802_11APMode */
|
||||
cur_network->join_res = -1;
|
||||
|
||||
stop_ap_mode(padapter);
|
||||
}
|
||||
|
||||
spin_lock_bh(&pmlmepriv->lock);
|
||||
|
||||
if ((check_fwstate(pmlmepriv, _FW_LINKED) == true) || (*pold_state == Ndis802_11IBSS))
|
||||
rtw_disassoc_cmd(padapter, 0, true);
|
||||
|
||||
if ((check_fwstate(pmlmepriv, _FW_LINKED) == true) ||
|
||||
(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true))
|
||||
rtw_free_assoc_resources(padapter, 1);
|
||||
|
||||
if ((*pold_state == Ndis802_11Infrastructure) || (*pold_state == Ndis802_11IBSS)) {
|
||||
if (check_fwstate(pmlmepriv, _FW_LINKED) == true) {
|
||||
rtw_indicate_disconnect(padapter); /* will clr Linked_state; before this function, we must have chked whether issue dis-assoc_cmd or not */
|
||||
}
|
||||
}
|
||||
|
||||
*pold_state = networktype;
|
||||
|
||||
_clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE);
|
||||
|
||||
switch (networktype) {
|
||||
case Ndis802_11IBSS:
|
||||
set_fwstate(pmlmepriv, WIFI_ADHOC_STATE);
|
||||
break;
|
||||
|
||||
case Ndis802_11Infrastructure:
|
||||
set_fwstate(pmlmepriv, WIFI_STATION_STATE);
|
||||
break;
|
||||
|
||||
case Ndis802_11APMode:
|
||||
set_fwstate(pmlmepriv, WIFI_AP_STATE);
|
||||
start_ap_mode(padapter);
|
||||
/* rtw_indicate_connect(padapter); */
|
||||
|
||||
break;
|
||||
|
||||
case Ndis802_11AutoUnknown:
|
||||
case Ndis802_11InfrastructureMax:
|
||||
break;
|
||||
}
|
||||
|
||||
/* SecClearAllKeys(adapter); */
|
||||
|
||||
/* RT_TRACE(COMP_OID_SET, DBG_LOUD, ("set_infrastructure: fw_state:%x after changing mode\n", */
|
||||
/* get_fwstate(pmlmepriv))); */
|
||||
|
||||
spin_unlock_bh(&pmlmepriv->lock);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
u8 rtw_set_802_11_disassociate(struct adapter *padapter)
|
||||
{
|
||||
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
|
||||
|
||||
spin_lock_bh(&pmlmepriv->lock);
|
||||
|
||||
if (check_fwstate(pmlmepriv, _FW_LINKED) == true) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_disassociate: rtw_indicate_disconnect\n"));
|
||||
|
||||
rtw_disassoc_cmd(padapter, 0, true);
|
||||
rtw_indicate_disconnect(padapter);
|
||||
/* modify for CONFIG_IEEE80211W, none 11w can use it */
|
||||
rtw_free_assoc_resources_cmd(padapter);
|
||||
if (_FAIL == rtw_pwr_wakeup(padapter))
|
||||
DBG_871X("%s(): rtw_pwr_wakeup fail !!!\n", __func__);
|
||||
}
|
||||
|
||||
spin_unlock_bh(&pmlmepriv->lock);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
u8 rtw_set_802_11_bssid_list_scan(struct adapter *padapter, struct ndis_802_11_ssid *pssid, int ssid_max_num)
|
||||
{
|
||||
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
|
||||
u8 res = true;
|
||||
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("+rtw_set_802_11_bssid_list_scan(), fw_state =%x\n", get_fwstate(pmlmepriv)));
|
||||
|
||||
if (padapter == NULL) {
|
||||
res = false;
|
||||
goto exit;
|
||||
}
|
||||
if (padapter->hw_init_completed == false) {
|
||||
res = false;
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n ===rtw_set_802_11_bssid_list_scan:hw_init_completed ==false ===\n"));
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if ((check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == true) ||
|
||||
(pmlmepriv->LinkDetectInfo.bBusyTraffic == true)) {
|
||||
/* Scan or linking is in progress, do nothing. */
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("rtw_set_802_11_bssid_list_scan fail since fw_state = %x\n", get_fwstate(pmlmepriv)));
|
||||
res = true;
|
||||
|
||||
if (check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING)) == true) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n###_FW_UNDER_SURVEY|_FW_UNDER_LINKING\n\n"));
|
||||
} else {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n###pmlmepriv->sitesurveyctrl.traffic_busy ==true\n\n"));
|
||||
}
|
||||
} else {
|
||||
if (rtw_is_scan_deny(padapter)) {
|
||||
DBG_871X(FUNC_ADPT_FMT": scan deny\n", FUNC_ADPT_ARG(padapter));
|
||||
indicate_wx_scan_complete_event(padapter);
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
spin_lock_bh(&pmlmepriv->lock);
|
||||
|
||||
res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, NULL, 0);
|
||||
|
||||
spin_unlock_bh(&pmlmepriv->lock);
|
||||
}
|
||||
exit:
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
u8 rtw_set_802_11_authentication_mode(struct adapter *padapter, enum NDIS_802_11_AUTHENTICATION_MODE authmode)
|
||||
{
|
||||
struct security_priv *psecuritypriv = &padapter->securitypriv;
|
||||
int res;
|
||||
u8 ret;
|
||||
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_802_11_auth.mode(): mode =%x\n", authmode));
|
||||
|
||||
psecuritypriv->ndisauthtype = authmode;
|
||||
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_authentication_mode:psecuritypriv->ndisauthtype =%d", psecuritypriv->ndisauthtype));
|
||||
|
||||
if (psecuritypriv->ndisauthtype > 3)
|
||||
psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X;
|
||||
|
||||
res = rtw_set_auth(padapter, psecuritypriv);
|
||||
|
||||
if (res == _SUCCESS)
|
||||
ret = true;
|
||||
else
|
||||
ret = false;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
u8 rtw_set_802_11_add_wep(struct adapter *padapter, struct ndis_802_11_wep *wep)
|
||||
{
|
||||
|
||||
u8 bdefaultkey;
|
||||
u8 btransmitkey;
|
||||
sint keyid, res;
|
||||
struct security_priv *psecuritypriv = &(padapter->securitypriv);
|
||||
u8 ret = _SUCCESS;
|
||||
|
||||
bdefaultkey = (wep->KeyIndex & 0x40000000) > 0 ? false : true; /* for ??? */
|
||||
btransmitkey = (wep->KeyIndex & 0x80000000) > 0 ? true : false; /* for ??? */
|
||||
keyid = wep->KeyIndex & 0x3fffffff;
|
||||
|
||||
if (keyid >= 4) {
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("MgntActrtw_set_802_11_add_wep:keyid>4 =>fail\n"));
|
||||
ret = false;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
switch (wep->KeyLength) {
|
||||
case 5:
|
||||
psecuritypriv->dot11PrivacyAlgrthm = _WEP40_;
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_add_wep:wep->KeyLength =5\n"));
|
||||
break;
|
||||
case 13:
|
||||
psecuritypriv->dot11PrivacyAlgrthm = _WEP104_;
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_add_wep:wep->KeyLength = 13\n"));
|
||||
break;
|
||||
default:
|
||||
psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("MgntActrtw_set_802_11_add_wep:wep->KeyLength!=5 or 13\n"));
|
||||
break;
|
||||
}
|
||||
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_wep:befor memcpy, wep->KeyLength = 0x%x wep->KeyIndex = 0x%x keyid =%x\n", wep->KeyLength, wep->KeyIndex, keyid));
|
||||
|
||||
memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]), &(wep->KeyMaterial), wep->KeyLength);
|
||||
|
||||
psecuritypriv->dot11DefKeylen[keyid] = wep->KeyLength;
|
||||
|
||||
psecuritypriv->dot11PrivacyKeyIndex = keyid;
|
||||
|
||||
RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("rtw_set_802_11_add_wep:security key material : %x %x %x %x %x %x %x %x %x %x %x %x %x\n",
|
||||
psecuritypriv->dot11DefKey[keyid].skey[0], psecuritypriv->dot11DefKey[keyid].skey[1], psecuritypriv->dot11DefKey[keyid].skey[2],
|
||||
psecuritypriv->dot11DefKey[keyid].skey[3], psecuritypriv->dot11DefKey[keyid].skey[4], psecuritypriv->dot11DefKey[keyid].skey[5],
|
||||
psecuritypriv->dot11DefKey[keyid].skey[6], psecuritypriv->dot11DefKey[keyid].skey[7], psecuritypriv->dot11DefKey[keyid].skey[8],
|
||||
psecuritypriv->dot11DefKey[keyid].skey[9], psecuritypriv->dot11DefKey[keyid].skey[10], psecuritypriv->dot11DefKey[keyid].skey[11],
|
||||
psecuritypriv->dot11DefKey[keyid].skey[12]));
|
||||
|
||||
res = rtw_set_key(padapter, psecuritypriv, keyid, 1, true);
|
||||
|
||||
if (res == _FAIL)
|
||||
ret = false;
|
||||
exit:
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* rtw_get_cur_max_rate -
|
||||
* @adapter: pointer to struct adapter structure
|
||||
*
|
||||
* Return 0 or 100Kbps
|
||||
*/
|
||||
u16 rtw_get_cur_max_rate(struct adapter *adapter)
|
||||
{
|
||||
int i = 0;
|
||||
u16 rate = 0, max_rate = 0;
|
||||
struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
|
||||
struct wlan_bssid_ex *pcur_bss = &pmlmepriv->cur_network.network;
|
||||
struct sta_info *psta = NULL;
|
||||
u8 short_GI = 0;
|
||||
u8 rf_type = 0;
|
||||
|
||||
if ((check_fwstate(pmlmepriv, _FW_LINKED) != true)
|
||||
&& (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != true))
|
||||
return 0;
|
||||
|
||||
psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv));
|
||||
if (psta == NULL)
|
||||
return 0;
|
||||
|
||||
short_GI = query_ra_short_GI(psta);
|
||||
|
||||
if (IsSupportedHT(psta->wireless_mode)) {
|
||||
rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
|
||||
|
||||
max_rate = rtw_mcs_rate(
|
||||
rf_type,
|
||||
((psta->bw_mode == CHANNEL_WIDTH_40)?1:0),
|
||||
short_GI,
|
||||
psta->htpriv.ht_cap.supp_mcs_set
|
||||
);
|
||||
} else{
|
||||
while ((pcur_bss->SupportedRates[i] != 0) && (pcur_bss->SupportedRates[i] != 0xFF)) {
|
||||
rate = pcur_bss->SupportedRates[i]&0x7F;
|
||||
if (rate > max_rate)
|
||||
max_rate = rate;
|
||||
i++;
|
||||
}
|
||||
|
||||
max_rate = max_rate*10/2;
|
||||
}
|
||||
|
||||
return max_rate;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,195 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2013 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <rtw_debug.h>
|
||||
#include <rtw_odm.h>
|
||||
#include <hal_data.h>
|
||||
|
||||
static const char *odm_comp_str[] = {
|
||||
/* BIT0 */"ODM_COMP_DIG",
|
||||
/* BIT1 */"ODM_COMP_RA_MASK",
|
||||
/* BIT2 */"ODM_COMP_DYNAMIC_TXPWR",
|
||||
/* BIT3 */"ODM_COMP_FA_CNT",
|
||||
/* BIT4 */"ODM_COMP_RSSI_MONITOR",
|
||||
/* BIT5 */"ODM_COMP_CCK_PD",
|
||||
/* BIT6 */"ODM_COMP_ANT_DIV",
|
||||
/* BIT7 */"ODM_COMP_PWR_SAVE",
|
||||
/* BIT8 */"ODM_COMP_PWR_TRAIN",
|
||||
/* BIT9 */"ODM_COMP_RATE_ADAPTIVE",
|
||||
/* BIT10 */"ODM_COMP_PATH_DIV",
|
||||
/* BIT11 */"ODM_COMP_PSD",
|
||||
/* BIT12 */"ODM_COMP_DYNAMIC_PRICCA",
|
||||
/* BIT13 */"ODM_COMP_RXHP",
|
||||
/* BIT14 */"ODM_COMP_MP",
|
||||
/* BIT15 */"ODM_COMP_DYNAMIC_ATC",
|
||||
/* BIT16 */"ODM_COMP_EDCA_TURBO",
|
||||
/* BIT17 */"ODM_COMP_EARLY_MODE",
|
||||
/* BIT18 */NULL,
|
||||
/* BIT19 */NULL,
|
||||
/* BIT20 */NULL,
|
||||
/* BIT21 */NULL,
|
||||
/* BIT22 */NULL,
|
||||
/* BIT23 */NULL,
|
||||
/* BIT24 */"ODM_COMP_TX_PWR_TRACK",
|
||||
/* BIT25 */"ODM_COMP_RX_GAIN_TRACK",
|
||||
/* BIT26 */"ODM_COMP_CALIBRATION",
|
||||
/* BIT27 */NULL,
|
||||
/* BIT28 */NULL,
|
||||
/* BIT29 */NULL,
|
||||
/* BIT30 */"ODM_COMP_COMMON",
|
||||
/* BIT31 */"ODM_COMP_INIT",
|
||||
};
|
||||
|
||||
#define RTW_ODM_COMP_MAX 32
|
||||
|
||||
static const char *odm_ability_str[] = {
|
||||
/* BIT0 */"ODM_BB_DIG",
|
||||
/* BIT1 */"ODM_BB_RA_MASK",
|
||||
/* BIT2 */"ODM_BB_DYNAMIC_TXPWR",
|
||||
/* BIT3 */"ODM_BB_FA_CNT",
|
||||
/* BIT4 */"ODM_BB_RSSI_MONITOR",
|
||||
/* BIT5 */"ODM_BB_CCK_PD",
|
||||
/* BIT6 */"ODM_BB_ANT_DIV",
|
||||
/* BIT7 */"ODM_BB_PWR_SAVE",
|
||||
/* BIT8 */"ODM_BB_PWR_TRAIN",
|
||||
/* BIT9 */"ODM_BB_RATE_ADAPTIVE",
|
||||
/* BIT10 */"ODM_BB_PATH_DIV",
|
||||
/* BIT11 */"ODM_BB_PSD",
|
||||
/* BIT12 */"ODM_BB_RXHP",
|
||||
/* BIT13 */"ODM_BB_ADAPTIVITY",
|
||||
/* BIT14 */"ODM_BB_DYNAMIC_ATC",
|
||||
/* BIT15 */NULL,
|
||||
/* BIT16 */"ODM_MAC_EDCA_TURBO",
|
||||
/* BIT17 */"ODM_MAC_EARLY_MODE",
|
||||
/* BIT18 */NULL,
|
||||
/* BIT19 */NULL,
|
||||
/* BIT20 */NULL,
|
||||
/* BIT21 */NULL,
|
||||
/* BIT22 */NULL,
|
||||
/* BIT23 */NULL,
|
||||
/* BIT24 */"ODM_RF_TX_PWR_TRACK",
|
||||
/* BIT25 */"ODM_RF_RX_GAIN_TRACK",
|
||||
/* BIT26 */"ODM_RF_CALIBRATION",
|
||||
};
|
||||
|
||||
#define RTW_ODM_ABILITY_MAX 27
|
||||
|
||||
static const char *odm_dbg_level_str[] = {
|
||||
NULL,
|
||||
"ODM_DBG_OFF",
|
||||
"ODM_DBG_SERIOUS",
|
||||
"ODM_DBG_WARNING",
|
||||
"ODM_DBG_LOUD",
|
||||
"ODM_DBG_TRACE",
|
||||
};
|
||||
|
||||
#define RTW_ODM_DBG_LEVEL_NUM 6
|
||||
|
||||
void rtw_odm_dbg_comp_msg(void *sel, struct adapter *adapter)
|
||||
{
|
||||
u64 dbg_comp;
|
||||
int i;
|
||||
|
||||
rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &dbg_comp);
|
||||
DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx\n", dbg_comp);
|
||||
for (i = 0; i < RTW_ODM_COMP_MAX; i++) {
|
||||
if (odm_comp_str[i])
|
||||
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
|
||||
(BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
|
||||
}
|
||||
}
|
||||
|
||||
inline void rtw_odm_dbg_comp_set(struct adapter *adapter, u64 comps)
|
||||
{
|
||||
rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &comps);
|
||||
}
|
||||
|
||||
void rtw_odm_dbg_level_msg(void *sel, struct adapter *adapter)
|
||||
{
|
||||
u32 dbg_level;
|
||||
int i;
|
||||
|
||||
rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &dbg_level);
|
||||
DBG_871X_SEL_NL(sel, "odm.DebugLevel = %u\n", dbg_level);
|
||||
for (i = 0; i < RTW_ODM_DBG_LEVEL_NUM; i++) {
|
||||
if (odm_dbg_level_str[i])
|
||||
DBG_871X_SEL_NL(sel, "%u %s\n", i, odm_dbg_level_str[i]);
|
||||
}
|
||||
}
|
||||
|
||||
inline void rtw_odm_dbg_level_set(struct adapter *adapter, u32 level)
|
||||
{
|
||||
rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &level);
|
||||
}
|
||||
|
||||
void rtw_odm_ability_msg(void *sel, struct adapter *adapter)
|
||||
{
|
||||
u32 ability = 0;
|
||||
int i;
|
||||
|
||||
rtw_hal_get_hwreg(adapter, HW_VAR_DM_FLAG, (u8 *)&ability);
|
||||
DBG_871X_SEL_NL(sel, "odm.SupportAbility = 0x%08x\n", ability);
|
||||
for (i = 0; i < RTW_ODM_ABILITY_MAX; i++) {
|
||||
if (odm_ability_str[i])
|
||||
DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
|
||||
(BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
|
||||
}
|
||||
}
|
||||
|
||||
inline void rtw_odm_ability_set(struct adapter *adapter, u32 ability)
|
||||
{
|
||||
rtw_hal_set_hwreg(adapter, HW_VAR_DM_FLAG, (u8 *)&ability);
|
||||
}
|
||||
|
||||
void rtw_odm_adaptivity_parm_msg(void *sel, struct adapter *adapter)
|
||||
{
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(adapter);
|
||||
DM_ODM_T *odm = &pHalData->odmpriv;
|
||||
|
||||
DBG_871X_SEL_NL(sel, "%10s %16s %8s %10s %11s %14s\n"
|
||||
, "TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound");
|
||||
DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n"
|
||||
, (u8)odm->TH_L2H_ini
|
||||
, odm->TH_EDCCA_HL_diff
|
||||
, odm->IGI_Base
|
||||
, odm->ForceEDCCA
|
||||
, odm->AdapEn_RSSI
|
||||
, odm->IGI_LowerBound
|
||||
);
|
||||
}
|
||||
|
||||
void rtw_odm_adaptivity_parm_set(struct adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
|
||||
s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)
|
||||
{
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(adapter);
|
||||
DM_ODM_T *odm = &pHalData->odmpriv;
|
||||
|
||||
odm->TH_L2H_ini = TH_L2H_ini;
|
||||
odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
|
||||
odm->IGI_Base = IGI_Base;
|
||||
odm->ForceEDCCA = ForceEDCCA;
|
||||
odm->AdapEn_RSSI = AdapEn_RSSI;
|
||||
odm->IGI_LowerBound = IGI_LowerBound;
|
||||
}
|
||||
|
||||
void rtw_odm_get_perpkt_rssi(void *sel, struct adapter *adapter)
|
||||
{
|
||||
struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
|
||||
DM_ODM_T *odm = &(hal_data->odmpriv);
|
||||
|
||||
DBG_871X_SEL_NL(sel, "RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
|
||||
HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,64 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define _RTW_RF_C_
|
||||
|
||||
#include <drv_types.h>
|
||||
|
||||
|
||||
struct ch_freq {
|
||||
u32 channel;
|
||||
u32 frequency;
|
||||
};
|
||||
|
||||
static struct ch_freq ch_freq_map[] = {
|
||||
{1, 2412}, {2, 2417}, {3, 2422}, {4, 2427}, {5, 2432},
|
||||
{6, 2437}, {7, 2442}, {8, 2447}, {9, 2452}, {10, 2457},
|
||||
{11, 2462}, {12, 2467}, {13, 2472}, {14, 2484},
|
||||
/* UNII */
|
||||
{36, 5180}, {40, 5200}, {44, 5220}, {48, 5240}, {52, 5260},
|
||||
{56, 5280}, {60, 5300}, {64, 5320}, {149, 5745}, {153, 5765},
|
||||
{157, 5785}, {161, 5805}, {165, 5825}, {167, 5835}, {169, 5845},
|
||||
{171, 5855}, {173, 5865},
|
||||
/* HiperLAN2 */
|
||||
{100, 5500}, {104, 5520}, {108, 5540}, {112, 5560}, {116, 5580},
|
||||
{120, 5600}, {124, 5620}, {128, 5640}, {132, 5660}, {136, 5680},
|
||||
{140, 5700},
|
||||
/* Japan MMAC */
|
||||
{34, 5170}, {38, 5190}, {42, 5210}, {46, 5230},
|
||||
/* Japan */
|
||||
{184, 4920}, {188, 4940}, {192, 4960}, {196, 4980},
|
||||
{208, 5040},/* Japan, means J08 */
|
||||
{212, 5060},/* Japan, means J12 */
|
||||
{216, 5080},/* Japan, means J16 */
|
||||
};
|
||||
|
||||
static int ch_freq_map_num = (sizeof(ch_freq_map) / sizeof(struct ch_freq));
|
||||
|
||||
u32 rtw_ch2freq(u32 channel)
|
||||
{
|
||||
u8 i;
|
||||
u32 freq = 0;
|
||||
|
||||
for (i = 0; i < ch_freq_map_num; i++) {
|
||||
if (channel == ch_freq_map[i].channel) {
|
||||
freq = ch_freq_map[i].frequency;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (i == ch_freq_map_num)
|
||||
freq = 2412;
|
||||
|
||||
return freq;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,641 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define _RTW_STA_MGT_C_
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <rtw_debug.h>
|
||||
|
||||
void _rtw_init_stainfo(struct sta_info *psta);
|
||||
void _rtw_init_stainfo(struct sta_info *psta)
|
||||
{
|
||||
memset((u8 *)psta, 0, sizeof(struct sta_info));
|
||||
|
||||
spin_lock_init(&psta->lock);
|
||||
INIT_LIST_HEAD(&psta->list);
|
||||
INIT_LIST_HEAD(&psta->hash_list);
|
||||
/* INIT_LIST_HEAD(&psta->asoc_list); */
|
||||
/* INIT_LIST_HEAD(&psta->sleep_list); */
|
||||
/* INIT_LIST_HEAD(&psta->wakeup_list); */
|
||||
|
||||
_rtw_init_queue(&psta->sleep_q);
|
||||
psta->sleepq_len = 0;
|
||||
|
||||
_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv);
|
||||
_rtw_init_sta_recv_priv(&psta->sta_recvpriv);
|
||||
|
||||
INIT_LIST_HEAD(&psta->asoc_list);
|
||||
|
||||
INIT_LIST_HEAD(&psta->auth_list);
|
||||
|
||||
psta->expire_to = 0;
|
||||
|
||||
psta->flags = 0;
|
||||
|
||||
psta->capability = 0;
|
||||
|
||||
psta->bpairwise_key_installed = false;
|
||||
|
||||
psta->nonerp_set = 0;
|
||||
psta->no_short_slot_time_set = 0;
|
||||
psta->no_short_preamble_set = 0;
|
||||
psta->no_ht_gf_set = 0;
|
||||
psta->no_ht_set = 0;
|
||||
psta->ht_20mhz_set = 0;
|
||||
|
||||
psta->under_exist_checking = 0;
|
||||
|
||||
psta->keep_alive_trycnt = 0;
|
||||
}
|
||||
|
||||
u32 _rtw_init_sta_priv(struct sta_priv *pstapriv)
|
||||
{
|
||||
struct sta_info *psta;
|
||||
s32 i;
|
||||
|
||||
pstapriv->pallocated_stainfo_buf = vzalloc(sizeof(struct sta_info) * NUM_STA+4);
|
||||
|
||||
if (!pstapriv->pallocated_stainfo_buf)
|
||||
return _FAIL;
|
||||
|
||||
pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 -
|
||||
((SIZE_PTR)(pstapriv->pallocated_stainfo_buf) & 3);
|
||||
|
||||
_rtw_init_queue(&pstapriv->free_sta_queue);
|
||||
|
||||
spin_lock_init(&pstapriv->sta_hash_lock);
|
||||
|
||||
/* _rtw_init_queue(&pstapriv->asoc_q); */
|
||||
pstapriv->asoc_sta_count = 0;
|
||||
_rtw_init_queue(&pstapriv->sleep_q);
|
||||
_rtw_init_queue(&pstapriv->wakeup_q);
|
||||
|
||||
psta = (struct sta_info *)(pstapriv->pstainfo_buf);
|
||||
|
||||
|
||||
for (i = 0; i < NUM_STA; i++) {
|
||||
_rtw_init_stainfo(psta);
|
||||
|
||||
INIT_LIST_HEAD(&(pstapriv->sta_hash[i]));
|
||||
|
||||
list_add_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue));
|
||||
|
||||
psta++;
|
||||
}
|
||||
|
||||
pstapriv->sta_dz_bitmap = 0;
|
||||
pstapriv->tim_bitmap = 0;
|
||||
|
||||
INIT_LIST_HEAD(&pstapriv->asoc_list);
|
||||
INIT_LIST_HEAD(&pstapriv->auth_list);
|
||||
spin_lock_init(&pstapriv->asoc_list_lock);
|
||||
spin_lock_init(&pstapriv->auth_list_lock);
|
||||
pstapriv->asoc_list_cnt = 0;
|
||||
pstapriv->auth_list_cnt = 0;
|
||||
|
||||
pstapriv->auth_to = 3; /* 3*2 = 6 sec */
|
||||
pstapriv->assoc_to = 3;
|
||||
pstapriv->expire_to = 3; /* 3*2 = 6 sec */
|
||||
pstapriv->max_num_sta = NUM_STA;
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta)
|
||||
{
|
||||
int offset = (((u8 *)sta) - stapriv->pstainfo_buf)/sizeof(struct sta_info);
|
||||
|
||||
if (!stainfo_offset_valid(offset))
|
||||
DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset);
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset)
|
||||
{
|
||||
if (!stainfo_offset_valid(offset))
|
||||
DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset);
|
||||
|
||||
return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info));
|
||||
}
|
||||
|
||||
/* this function is used to free the memory of lock || sema for all stainfos */
|
||||
void kfree_all_stainfo(struct sta_priv *pstapriv);
|
||||
void kfree_all_stainfo(struct sta_priv *pstapriv)
|
||||
{
|
||||
struct list_head *plist, *phead;
|
||||
struct sta_info *psta = NULL;
|
||||
|
||||
spin_lock_bh(&pstapriv->sta_hash_lock);
|
||||
|
||||
phead = get_list_head(&pstapriv->free_sta_queue);
|
||||
plist = get_next(phead);
|
||||
|
||||
while (phead != plist) {
|
||||
psta = LIST_CONTAINOR(plist, struct sta_info, list);
|
||||
plist = get_next(plist);
|
||||
}
|
||||
|
||||
spin_unlock_bh(&pstapriv->sta_hash_lock);
|
||||
}
|
||||
|
||||
void kfree_sta_priv_lock(struct sta_priv *pstapriv);
|
||||
void kfree_sta_priv_lock(struct sta_priv *pstapriv)
|
||||
{
|
||||
kfree_all_stainfo(pstapriv); /* be done before free sta_hash_lock */
|
||||
}
|
||||
|
||||
u32 _rtw_free_sta_priv(struct sta_priv *pstapriv)
|
||||
{
|
||||
struct list_head *phead, *plist;
|
||||
struct sta_info *psta = NULL;
|
||||
struct recv_reorder_ctrl *preorder_ctrl;
|
||||
int index;
|
||||
|
||||
if (pstapriv) {
|
||||
|
||||
/*delete all reordering_ctrl_timer */
|
||||
spin_lock_bh(&pstapriv->sta_hash_lock);
|
||||
for (index = 0; index < NUM_STA; index++) {
|
||||
phead = &(pstapriv->sta_hash[index]);
|
||||
plist = get_next(phead);
|
||||
|
||||
while (phead != plist) {
|
||||
int i;
|
||||
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
|
||||
plist = get_next(plist);
|
||||
|
||||
for (i = 0; i < 16 ; i++) {
|
||||
preorder_ctrl = &psta->recvreorder_ctrl[i];
|
||||
del_timer_sync(&preorder_ctrl->reordering_ctrl_timer);
|
||||
}
|
||||
}
|
||||
}
|
||||
spin_unlock_bh(&pstapriv->sta_hash_lock);
|
||||
/*===============================*/
|
||||
|
||||
kfree_sta_priv_lock(pstapriv);
|
||||
|
||||
if (pstapriv->pallocated_stainfo_buf)
|
||||
vfree(pstapriv->pallocated_stainfo_buf);
|
||||
|
||||
}
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
/* struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) */
|
||||
struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
|
||||
{
|
||||
uint tmp_aid;
|
||||
s32 index;
|
||||
struct list_head *phash_list;
|
||||
struct sta_info *psta;
|
||||
struct __queue *pfree_sta_queue;
|
||||
struct recv_reorder_ctrl *preorder_ctrl;
|
||||
int i = 0;
|
||||
u16 wRxSeqInitialValue = 0xffff;
|
||||
|
||||
pfree_sta_queue = &pstapriv->free_sta_queue;
|
||||
|
||||
/* spin_lock_bh(&(pfree_sta_queue->lock)); */
|
||||
spin_lock_bh(&(pstapriv->sta_hash_lock));
|
||||
if (list_empty(&pfree_sta_queue->queue)) {
|
||||
/* spin_unlock_bh(&(pfree_sta_queue->lock)); */
|
||||
spin_unlock_bh(&(pstapriv->sta_hash_lock));
|
||||
psta = NULL;
|
||||
return psta;
|
||||
} else{
|
||||
psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list);
|
||||
|
||||
list_del_init(&(psta->list));
|
||||
|
||||
/* spin_unlock_bh(&(pfree_sta_queue->lock)); */
|
||||
|
||||
tmp_aid = psta->aid;
|
||||
|
||||
_rtw_init_stainfo(psta);
|
||||
|
||||
psta->padapter = pstapriv->padapter;
|
||||
|
||||
memcpy(psta->hwaddr, hwaddr, ETH_ALEN);
|
||||
|
||||
index = wifi_mac_hash(hwaddr);
|
||||
|
||||
RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_info_, ("rtw_alloc_stainfo: index = %x", index));
|
||||
|
||||
if (index >= NUM_STA) {
|
||||
RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_err_, ("ERROR => rtw_alloc_stainfo: index >= NUM_STA"));
|
||||
spin_unlock_bh(&(pstapriv->sta_hash_lock));
|
||||
psta = NULL;
|
||||
goto exit;
|
||||
}
|
||||
phash_list = &(pstapriv->sta_hash[index]);
|
||||
|
||||
/* spin_lock_bh(&(pstapriv->sta_hash_lock)); */
|
||||
|
||||
list_add_tail(&psta->hash_list, phash_list);
|
||||
|
||||
pstapriv->asoc_sta_count++;
|
||||
|
||||
/* spin_unlock_bh(&(pstapriv->sta_hash_lock)); */
|
||||
|
||||
/* Commented by Albert 2009/08/13 */
|
||||
/* For the SMC router, the sequence number of first packet of WPS handshake will be 0. */
|
||||
/* In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable. */
|
||||
/* So, we initialize the tid_rxseq variable as the 0xffff. */
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2);
|
||||
}
|
||||
|
||||
RT_TRACE(
|
||||
_module_rtl871x_sta_mgt_c_,
|
||||
_drv_info_, (
|
||||
"alloc number_%d stainfo with hwaddr = %x %x %x %x %x %x \n",
|
||||
pstapriv->asoc_sta_count,
|
||||
hwaddr[0],
|
||||
hwaddr[1],
|
||||
hwaddr[2],
|
||||
hwaddr[3],
|
||||
hwaddr[4],
|
||||
hwaddr[5]
|
||||
)
|
||||
);
|
||||
|
||||
init_addba_retry_timer(pstapriv->padapter, psta);
|
||||
|
||||
/* for A-MPDU Rx reordering buffer control */
|
||||
for (i = 0; i < 16 ; i++) {
|
||||
preorder_ctrl = &psta->recvreorder_ctrl[i];
|
||||
|
||||
preorder_ctrl->padapter = pstapriv->padapter;
|
||||
|
||||
preorder_ctrl->enable = false;
|
||||
|
||||
preorder_ctrl->indicate_seq = 0xffff;
|
||||
#ifdef DBG_RX_SEQ
|
||||
DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d\n", __func__, __LINE__,
|
||||
preorder_ctrl->indicate_seq);
|
||||
#endif
|
||||
preorder_ctrl->wend_b = 0xffff;
|
||||
/* preorder_ctrl->wsize_b = (NR_RECVBUFF-2); */
|
||||
preorder_ctrl->wsize_b = 64;/* 64; */
|
||||
|
||||
_rtw_init_queue(&preorder_ctrl->pending_recvframe_queue);
|
||||
|
||||
rtw_init_recv_timer(preorder_ctrl);
|
||||
}
|
||||
|
||||
|
||||
/* init for DM */
|
||||
psta->rssi_stat.UndecoratedSmoothedPWDB = (-1);
|
||||
psta->rssi_stat.UndecoratedSmoothedCCK = (-1);
|
||||
|
||||
/* init for the sequence number of received management frame */
|
||||
psta->RxMgmtFrameSeqNum = 0xffff;
|
||||
spin_unlock_bh(&(pstapriv->sta_hash_lock));
|
||||
/* alloc mac id for non-bc/mc station, */
|
||||
rtw_alloc_macid(pstapriv->padapter, psta);
|
||||
|
||||
}
|
||||
|
||||
exit:
|
||||
|
||||
|
||||
return psta;
|
||||
}
|
||||
|
||||
/* using pstapriv->sta_hash_lock to protect */
|
||||
u32 rtw_free_stainfo(struct adapter *padapter, struct sta_info *psta)
|
||||
{
|
||||
int i;
|
||||
struct __queue *pfree_sta_queue;
|
||||
struct recv_reorder_ctrl *preorder_ctrl;
|
||||
struct sta_xmit_priv *pstaxmitpriv;
|
||||
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
|
||||
struct sta_priv *pstapriv = &padapter->stapriv;
|
||||
struct hw_xmit *phwxmit;
|
||||
|
||||
if (psta == NULL)
|
||||
goto exit;
|
||||
|
||||
|
||||
spin_lock_bh(&psta->lock);
|
||||
psta->state &= ~_FW_LINKED;
|
||||
spin_unlock_bh(&psta->lock);
|
||||
|
||||
pfree_sta_queue = &pstapriv->free_sta_queue;
|
||||
|
||||
|
||||
pstaxmitpriv = &psta->sta_xmitpriv;
|
||||
|
||||
/* list_del_init(&psta->sleep_list); */
|
||||
|
||||
/* list_del_init(&psta->wakeup_list); */
|
||||
|
||||
spin_lock_bh(&pxmitpriv->lock);
|
||||
|
||||
rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q);
|
||||
psta->sleepq_len = 0;
|
||||
|
||||
/* vo */
|
||||
/* spin_lock_bh(&(pxmitpriv->vo_pending.lock)); */
|
||||
rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vo_q.sta_pending);
|
||||
list_del_init(&(pstaxmitpriv->vo_q.tx_pending));
|
||||
phwxmit = pxmitpriv->hwxmits;
|
||||
phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt;
|
||||
pstaxmitpriv->vo_q.qcnt = 0;
|
||||
/* spin_unlock_bh(&(pxmitpriv->vo_pending.lock)); */
|
||||
|
||||
/* vi */
|
||||
/* spin_lock_bh(&(pxmitpriv->vi_pending.lock)); */
|
||||
rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vi_q.sta_pending);
|
||||
list_del_init(&(pstaxmitpriv->vi_q.tx_pending));
|
||||
phwxmit = pxmitpriv->hwxmits+1;
|
||||
phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt;
|
||||
pstaxmitpriv->vi_q.qcnt = 0;
|
||||
/* spin_unlock_bh(&(pxmitpriv->vi_pending.lock)); */
|
||||
|
||||
/* be */
|
||||
/* spin_lock_bh(&(pxmitpriv->be_pending.lock)); */
|
||||
rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->be_q.sta_pending);
|
||||
list_del_init(&(pstaxmitpriv->be_q.tx_pending));
|
||||
phwxmit = pxmitpriv->hwxmits+2;
|
||||
phwxmit->accnt -= pstaxmitpriv->be_q.qcnt;
|
||||
pstaxmitpriv->be_q.qcnt = 0;
|
||||
/* spin_unlock_bh(&(pxmitpriv->be_pending.lock)); */
|
||||
|
||||
/* bk */
|
||||
/* spin_lock_bh(&(pxmitpriv->bk_pending.lock)); */
|
||||
rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->bk_q.sta_pending);
|
||||
list_del_init(&(pstaxmitpriv->bk_q.tx_pending));
|
||||
phwxmit = pxmitpriv->hwxmits+3;
|
||||
phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt;
|
||||
pstaxmitpriv->bk_q.qcnt = 0;
|
||||
/* spin_unlock_bh(&(pxmitpriv->bk_pending.lock)); */
|
||||
|
||||
spin_unlock_bh(&pxmitpriv->lock);
|
||||
|
||||
list_del_init(&psta->hash_list);
|
||||
RT_TRACE(
|
||||
_module_rtl871x_sta_mgt_c_,
|
||||
_drv_err_, (
|
||||
"\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",
|
||||
pstapriv->asoc_sta_count,
|
||||
psta->hwaddr[0],
|
||||
psta->hwaddr[1],
|
||||
psta->hwaddr[2],
|
||||
psta->hwaddr[3],
|
||||
psta->hwaddr[4],
|
||||
psta->hwaddr[5]
|
||||
)
|
||||
);
|
||||
pstapriv->asoc_sta_count--;
|
||||
|
||||
|
||||
/* re-init sta_info; 20061114 will be init in alloc_stainfo */
|
||||
/* _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); */
|
||||
/* _rtw_init_sta_recv_priv(&psta->sta_recvpriv); */
|
||||
|
||||
del_timer_sync(&psta->addba_retry_timer);
|
||||
|
||||
/* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */
|
||||
for (i = 0; i < 16 ; i++) {
|
||||
struct list_head *phead, *plist;
|
||||
union recv_frame *prframe;
|
||||
struct __queue *ppending_recvframe_queue;
|
||||
struct __queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue;
|
||||
|
||||
preorder_ctrl = &psta->recvreorder_ctrl[i];
|
||||
|
||||
del_timer_sync(&preorder_ctrl->reordering_ctrl_timer);
|
||||
|
||||
|
||||
ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue;
|
||||
|
||||
spin_lock_bh(&ppending_recvframe_queue->lock);
|
||||
|
||||
phead = get_list_head(ppending_recvframe_queue);
|
||||
plist = get_next(phead);
|
||||
|
||||
while (!list_empty(phead)) {
|
||||
prframe = LIST_CONTAINOR(plist, union recv_frame, u);
|
||||
|
||||
plist = get_next(plist);
|
||||
|
||||
list_del_init(&(prframe->u.hdr.list));
|
||||
|
||||
rtw_free_recvframe(prframe, pfree_recv_queue);
|
||||
}
|
||||
|
||||
spin_unlock_bh(&ppending_recvframe_queue->lock);
|
||||
|
||||
}
|
||||
|
||||
if (!(psta->state & WIFI_AP_STATE))
|
||||
rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, false);
|
||||
|
||||
|
||||
/* release mac id for non-bc/mc station, */
|
||||
rtw_release_macid(pstapriv->padapter, psta);
|
||||
|
||||
/*
|
||||
spin_lock_bh(&pstapriv->asoc_list_lock);
|
||||
list_del_init(&psta->asoc_list);
|
||||
spin_unlock_bh(&pstapriv->asoc_list_lock);
|
||||
*/
|
||||
spin_lock_bh(&pstapriv->auth_list_lock);
|
||||
if (!list_empty(&psta->auth_list)) {
|
||||
list_del_init(&psta->auth_list);
|
||||
pstapriv->auth_list_cnt--;
|
||||
}
|
||||
spin_unlock_bh(&pstapriv->auth_list_lock);
|
||||
|
||||
psta->expire_to = 0;
|
||||
psta->sleepq_ac_len = 0;
|
||||
psta->qos_info = 0;
|
||||
|
||||
psta->max_sp_len = 0;
|
||||
psta->uapsd_bk = 0;
|
||||
psta->uapsd_be = 0;
|
||||
psta->uapsd_vi = 0;
|
||||
psta->uapsd_vo = 0;
|
||||
|
||||
psta->has_legacy_ac = 0;
|
||||
|
||||
pstapriv->sta_dz_bitmap &= ~BIT(psta->aid);
|
||||
pstapriv->tim_bitmap &= ~BIT(psta->aid);
|
||||
|
||||
if ((psta->aid > 0) && (pstapriv->sta_aid[psta->aid - 1] == psta)) {
|
||||
pstapriv->sta_aid[psta->aid - 1] = NULL;
|
||||
psta->aid = 0;
|
||||
}
|
||||
|
||||
psta->under_exist_checking = 0;
|
||||
|
||||
/* spin_lock_bh(&(pfree_sta_queue->lock)); */
|
||||
list_add_tail(&psta->list, get_list_head(pfree_sta_queue));
|
||||
/* spin_unlock_bh(&(pfree_sta_queue->lock)); */
|
||||
|
||||
exit:
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
/* free all stainfo which in sta_hash[all] */
|
||||
void rtw_free_all_stainfo(struct adapter *padapter)
|
||||
{
|
||||
struct list_head *plist, *phead;
|
||||
s32 index;
|
||||
struct sta_info *psta = NULL;
|
||||
struct sta_priv *pstapriv = &padapter->stapriv;
|
||||
struct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(padapter);
|
||||
|
||||
if (pstapriv->asoc_sta_count == 1)
|
||||
return;
|
||||
|
||||
spin_lock_bh(&pstapriv->sta_hash_lock);
|
||||
|
||||
for (index = 0; index < NUM_STA; index++) {
|
||||
phead = &(pstapriv->sta_hash[index]);
|
||||
plist = get_next(phead);
|
||||
|
||||
while (phead != plist) {
|
||||
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
|
||||
|
||||
plist = get_next(plist);
|
||||
|
||||
if (pbcmc_stainfo != psta)
|
||||
rtw_free_stainfo(padapter, psta);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock_bh(&pstapriv->sta_hash_lock);
|
||||
}
|
||||
|
||||
/* any station allocated can be searched by hash list */
|
||||
struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
|
||||
{
|
||||
struct list_head *plist, *phead;
|
||||
struct sta_info *psta = NULL;
|
||||
u32 index;
|
||||
u8 *addr;
|
||||
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
|
||||
|
||||
if (hwaddr == NULL)
|
||||
return NULL;
|
||||
|
||||
if (IS_MCAST(hwaddr))
|
||||
addr = bc_addr;
|
||||
else
|
||||
addr = hwaddr;
|
||||
|
||||
index = wifi_mac_hash(addr);
|
||||
|
||||
spin_lock_bh(&pstapriv->sta_hash_lock);
|
||||
|
||||
phead = &(pstapriv->sta_hash[index]);
|
||||
plist = get_next(phead);
|
||||
|
||||
|
||||
while (phead != plist) {
|
||||
|
||||
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
|
||||
|
||||
if ((!memcmp(psta->hwaddr, addr, ETH_ALEN)))
|
||||
/* if found the matched address */
|
||||
break;
|
||||
|
||||
psta = NULL;
|
||||
plist = get_next(plist);
|
||||
}
|
||||
|
||||
spin_unlock_bh(&pstapriv->sta_hash_lock);
|
||||
return psta;
|
||||
}
|
||||
|
||||
u32 rtw_init_bcmc_stainfo(struct adapter *padapter)
|
||||
{
|
||||
|
||||
struct sta_info *psta;
|
||||
struct tx_servq *ptxservq;
|
||||
u32 res = _SUCCESS;
|
||||
NDIS_802_11_MAC_ADDRESS bcast_addr = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
|
||||
|
||||
struct sta_priv *pstapriv = &padapter->stapriv;
|
||||
/* struct __queue *pstapending = &padapter->xmitpriv.bm_pending; */
|
||||
|
||||
psta = rtw_alloc_stainfo(pstapriv, bcast_addr);
|
||||
|
||||
if (psta == NULL) {
|
||||
res = _FAIL;
|
||||
RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_err_, ("rtw_alloc_stainfo fail"));
|
||||
goto exit;
|
||||
}
|
||||
|
||||
/* default broadcast & multicast use macid 1 */
|
||||
psta->mac_id = 1;
|
||||
|
||||
ptxservq = &(psta->sta_xmitpriv.be_q);
|
||||
exit:
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
struct sta_info *rtw_get_bcmc_stainfo(struct adapter *padapter)
|
||||
{
|
||||
struct sta_info *psta;
|
||||
struct sta_priv *pstapriv = &padapter->stapriv;
|
||||
u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
|
||||
|
||||
psta = rtw_get_stainfo(pstapriv, bc_addr);
|
||||
return psta;
|
||||
}
|
||||
|
||||
u8 rtw_access_ctrl(struct adapter *padapter, u8 *mac_addr)
|
||||
{
|
||||
u8 res = true;
|
||||
struct list_head *plist, *phead;
|
||||
struct rtw_wlan_acl_node *paclnode;
|
||||
u8 match = false;
|
||||
struct sta_priv *pstapriv = &padapter->stapriv;
|
||||
struct wlan_acl_pool *pacl_list = &pstapriv->acl_list;
|
||||
struct __queue *pacl_node_q = &pacl_list->acl_node_q;
|
||||
|
||||
spin_lock_bh(&(pacl_node_q->lock));
|
||||
phead = get_list_head(pacl_node_q);
|
||||
plist = get_next(phead);
|
||||
while (phead != plist) {
|
||||
paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list);
|
||||
plist = get_next(plist);
|
||||
|
||||
if (!memcmp(paclnode->addr, mac_addr, ETH_ALEN))
|
||||
if (paclnode->valid == true) {
|
||||
match = true;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
spin_unlock_bh(&(pacl_node_q->lock));
|
||||
|
||||
|
||||
if (pacl_list->mode == 1) /* accept unless in deny list */
|
||||
res = (match == true) ? false:true;
|
||||
|
||||
else if (pacl_list->mode == 2)/* deny unless in accept list */
|
||||
res = (match == true) ? true:false;
|
||||
else
|
||||
res = true;
|
||||
|
||||
return res;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,138 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
*
|
||||
This file includes all kinds of Power Action event for RTL8723B
|
||||
and corresponding hardware configurtions which are released from HW SD.
|
||||
|
||||
Major Change History:
|
||||
When Who What
|
||||
---------- --------------- -------------------------------
|
||||
2011-08-08 Roger Create.
|
||||
|
||||
*/
|
||||
|
||||
#include "Hal8723BPwrSeq.h"
|
||||
|
||||
/* drivers should parse below arrays and do the corresponding actions */
|
||||
/* 3 Power on Array */
|
||||
WLAN_PWR_CFG rtl8723B_power_on_flow[
|
||||
RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+
|
||||
RTL8723B_TRANS_END_STEPS
|
||||
] = {
|
||||
RTL8723B_TRANS_CARDEMU_TO_ACT
|
||||
RTL8723B_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Radio off GPIO Array */
|
||||
WLAN_PWR_CFG rtl8723B_radio_off_flow[
|
||||
RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+
|
||||
RTL8723B_TRANS_END_STEPS
|
||||
] = {
|
||||
RTL8723B_TRANS_ACT_TO_CARDEMU
|
||||
RTL8723B_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Card Disable Array */
|
||||
WLAN_PWR_CFG rtl8723B_card_disable_flow[
|
||||
RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+
|
||||
RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+
|
||||
RTL8723B_TRANS_END_STEPS
|
||||
] = {
|
||||
RTL8723B_TRANS_ACT_TO_CARDEMU
|
||||
RTL8723B_TRANS_CARDEMU_TO_CARDDIS
|
||||
RTL8723B_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Card Enable Array */
|
||||
WLAN_PWR_CFG rtl8723B_card_enable_flow[
|
||||
RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+
|
||||
RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+
|
||||
RTL8723B_TRANS_END_STEPS
|
||||
] = {
|
||||
RTL8723B_TRANS_CARDDIS_TO_CARDEMU
|
||||
RTL8723B_TRANS_CARDEMU_TO_ACT
|
||||
RTL8723B_TRANS_END
|
||||
};
|
||||
|
||||
/* 3Suspend Array */
|
||||
WLAN_PWR_CFG rtl8723B_suspend_flow[
|
||||
RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+
|
||||
RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS+
|
||||
RTL8723B_TRANS_END_STEPS
|
||||
] = {
|
||||
RTL8723B_TRANS_ACT_TO_CARDEMU
|
||||
RTL8723B_TRANS_CARDEMU_TO_SUS
|
||||
RTL8723B_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Resume Array */
|
||||
WLAN_PWR_CFG rtl8723B_resume_flow[
|
||||
RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+
|
||||
RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS+
|
||||
RTL8723B_TRANS_END_STEPS
|
||||
] = {
|
||||
RTL8723B_TRANS_SUS_TO_CARDEMU
|
||||
RTL8723B_TRANS_CARDEMU_TO_ACT
|
||||
RTL8723B_TRANS_END
|
||||
};
|
||||
|
||||
/* 3HWPDN Array */
|
||||
WLAN_PWR_CFG rtl8723B_hwpdn_flow[
|
||||
RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+
|
||||
RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+
|
||||
RTL8723B_TRANS_END_STEPS
|
||||
] = {
|
||||
RTL8723B_TRANS_ACT_TO_CARDEMU
|
||||
RTL8723B_TRANS_CARDEMU_TO_PDN
|
||||
RTL8723B_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Enter LPS */
|
||||
WLAN_PWR_CFG rtl8723B_enter_lps_flow[
|
||||
RTL8723B_TRANS_ACT_TO_LPS_STEPS+RTL8723B_TRANS_END_STEPS
|
||||
] = {
|
||||
/* FW behavior */
|
||||
RTL8723B_TRANS_ACT_TO_LPS
|
||||
RTL8723B_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Leave LPS */
|
||||
WLAN_PWR_CFG rtl8723B_leave_lps_flow[
|
||||
RTL8723B_TRANS_LPS_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS
|
||||
] = {
|
||||
/* FW behavior */
|
||||
RTL8723B_TRANS_LPS_TO_ACT
|
||||
RTL8723B_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Enter SW LPS */
|
||||
WLAN_PWR_CFG rtl8723B_enter_swlps_flow[
|
||||
RTL8723B_TRANS_ACT_TO_SWLPS_STEPS+RTL8723B_TRANS_END_STEPS
|
||||
] = {
|
||||
/* SW behavior */
|
||||
RTL8723B_TRANS_ACT_TO_SWLPS
|
||||
RTL8723B_TRANS_END
|
||||
};
|
||||
|
||||
/* 3 Leave SW LPS */
|
||||
WLAN_PWR_CFG rtl8723B_leave_swlps_flow[
|
||||
RTL8723B_TRANS_SWLPS_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS
|
||||
] = {
|
||||
/* SW behavior */
|
||||
RTL8723B_TRANS_SWLPS_TO_ACT
|
||||
RTL8723B_TRANS_END
|
||||
};
|
||||
|
|
@ -0,0 +1,442 @@
|
|||
/*****************************************************************************
|
||||
*Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved.
|
||||
*
|
||||
* Module: __INC_HAL8723BREG_H
|
||||
*
|
||||
*
|
||||
* Note: 1. Define Mac register address and corresponding bit mask map
|
||||
*
|
||||
*
|
||||
* Export: Constants, macro, functions(API), global variables(None).
|
||||
*
|
||||
* Abbrev:
|
||||
*
|
||||
* History:
|
||||
* Data Who Remark
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8723BREG_H
|
||||
#define __INC_HAL8723BREG_H
|
||||
|
||||
|
||||
|
||||
/* */
|
||||
/* */
|
||||
/* */
|
||||
|
||||
/* */
|
||||
/* */
|
||||
/* 0x0000h ~ 0x00FFh System Configuration */
|
||||
/* */
|
||||
/* */
|
||||
#define REG_SYS_ISO_CTRL_8723B 0x0000 /* 2 Byte */
|
||||
#define REG_SYS_FUNC_EN_8723B 0x0002 /* 2 Byte */
|
||||
#define REG_APS_FSMCO_8723B 0x0004 /* 4 Byte */
|
||||
#define REG_SYS_CLKR_8723B 0x0008 /* 2 Byte */
|
||||
#define REG_9346CR_8723B 0x000A /* 2 Byte */
|
||||
#define REG_EE_VPD_8723B 0x000C /* 2 Byte */
|
||||
#define REG_AFE_MISC_8723B 0x0010 /* 1 Byte */
|
||||
#define REG_SPS0_CTRL_8723B 0x0011 /* 7 Byte */
|
||||
#define REG_SPS_OCP_CFG_8723B 0x0018 /* 4 Byte */
|
||||
#define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */
|
||||
#define REG_RF_CTRL_8723B 0x001F /* 1 Byte */
|
||||
#define REG_LPLDO_CTRL_8723B 0x0023 /* 1 Byte */
|
||||
#define REG_AFE_XTAL_CTRL_8723B 0x0024 /* 4 Byte */
|
||||
#define REG_AFE_PLL_CTRL_8723B 0x0028 /* 4 Byte */
|
||||
#define REG_MAC_PLL_CTRL_EXT_8723B 0x002c /* 4 Byte */
|
||||
#define REG_EFUSE_CTRL_8723B 0x0030
|
||||
#define REG_EFUSE_TEST_8723B 0x0034
|
||||
#define REG_PWR_DATA_8723B 0x0038
|
||||
#define REG_CAL_TIMER_8723B 0x003C
|
||||
#define REG_ACLK_MON_8723B 0x003E
|
||||
#define REG_GPIO_MUXCFG_8723B 0x0040
|
||||
#define REG_GPIO_IO_SEL_8723B 0x0042
|
||||
#define REG_MAC_PINMUX_CFG_8723B 0x0043
|
||||
#define REG_GPIO_PIN_CTRL_8723B 0x0044
|
||||
#define REG_GPIO_INTM_8723B 0x0048
|
||||
#define REG_LEDCFG0_8723B 0x004C
|
||||
#define REG_LEDCFG1_8723B 0x004D
|
||||
#define REG_LEDCFG2_8723B 0x004E
|
||||
#define REG_LEDCFG3_8723B 0x004F
|
||||
#define REG_FSIMR_8723B 0x0050
|
||||
#define REG_FSISR_8723B 0x0054
|
||||
#define REG_HSIMR_8723B 0x0058
|
||||
#define REG_HSISR_8723B 0x005c
|
||||
#define REG_GPIO_EXT_CTRL 0x0060
|
||||
#define REG_MULTI_FUNC_CTRL_8723B 0x0068
|
||||
#define REG_GPIO_STATUS_8723B 0x006C
|
||||
#define REG_SDIO_CTRL_8723B 0x0070
|
||||
#define REG_OPT_CTRL_8723B 0x0074
|
||||
#define REG_AFE_XTAL_CTRL_EXT_8723B 0x0078
|
||||
#define REG_MCUFWDL_8723B 0x0080
|
||||
#define REG_BT_PATCH_STATUS_8723B 0x0088
|
||||
#define REG_HIMR0_8723B 0x00B0
|
||||
#define REG_HISR0_8723B 0x00B4
|
||||
#define REG_HIMR1_8723B 0x00B8
|
||||
#define REG_HISR1_8723B 0x00BC
|
||||
#define REG_PMC_DBG_CTRL2_8723B 0x00CC
|
||||
#define REG_EFUSE_BURN_GNT_8723B 0x00CF
|
||||
#define REG_HPON_FSM_8723B 0x00EC
|
||||
#define REG_SYS_CFG_8723B 0x00F0
|
||||
#define REG_SYS_CFG1_8723B 0x00FC
|
||||
#define REG_ROM_VERSION 0x00FD
|
||||
|
||||
/* */
|
||||
/* */
|
||||
/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
|
||||
/* */
|
||||
/* */
|
||||
#define REG_CR_8723B 0x0100
|
||||
#define REG_PBP_8723B 0x0104
|
||||
#define REG_PKT_BUFF_ACCESS_CTRL_8723B 0x0106
|
||||
#define REG_TRXDMA_CTRL_8723B 0x010C
|
||||
#define REG_TRXFF_BNDY_8723B 0x0114
|
||||
#define REG_TRXFF_STATUS_8723B 0x0118
|
||||
#define REG_RXFF_PTR_8723B 0x011C
|
||||
#define REG_CPWM_8723B 0x012F
|
||||
#define REG_FWIMR_8723B 0x0130
|
||||
#define REG_FWISR_8723B 0x0134
|
||||
#define REG_FTIMR_8723B 0x0138
|
||||
#define REG_PKTBUF_DBG_CTRL_8723B 0x0140
|
||||
#define REG_RXPKTBUF_CTRL_8723B 0x0142
|
||||
#define REG_PKTBUF_DBG_DATA_L_8723B 0x0144
|
||||
#define REG_PKTBUF_DBG_DATA_H_8723B 0x0148
|
||||
|
||||
#define REG_TC0_CTRL_8723B 0x0150
|
||||
#define REG_TC1_CTRL_8723B 0x0154
|
||||
#define REG_TC2_CTRL_8723B 0x0158
|
||||
#define REG_TC3_CTRL_8723B 0x015C
|
||||
#define REG_TC4_CTRL_8723B 0x0160
|
||||
#define REG_TCUNIT_BASE_8723B 0x0164
|
||||
#define REG_RSVD3_8723B 0x0168
|
||||
#define REG_C2HEVT_MSG_NORMAL_8723B 0x01A0
|
||||
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
|
||||
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
|
||||
#define REG_C2HEVT_CMD_LEN_88XX 0x01AE
|
||||
#define REG_C2HEVT_CLEAR_8723B 0x01AF
|
||||
#define REG_MCUTST_1_8723B 0x01C0
|
||||
#define REG_MCUTST_WOWLAN_8723B 0x01C7
|
||||
#define REG_FMETHR_8723B 0x01C8
|
||||
#define REG_HMETFR_8723B 0x01CC
|
||||
#define REG_HMEBOX_0_8723B 0x01D0
|
||||
#define REG_HMEBOX_1_8723B 0x01D4
|
||||
#define REG_HMEBOX_2_8723B 0x01D8
|
||||
#define REG_HMEBOX_3_8723B 0x01DC
|
||||
#define REG_LLT_INIT_8723B 0x01E0
|
||||
#define REG_HMEBOX_EXT0_8723B 0x01F0
|
||||
#define REG_HMEBOX_EXT1_8723B 0x01F4
|
||||
#define REG_HMEBOX_EXT2_8723B 0x01F8
|
||||
#define REG_HMEBOX_EXT3_8723B 0x01FC
|
||||
|
||||
/* */
|
||||
/* */
|
||||
/* 0x0200h ~ 0x027Fh TXDMA Configuration */
|
||||
/* */
|
||||
/* */
|
||||
#define REG_RQPN_8723B 0x0200
|
||||
#define REG_FIFOPAGE_8723B 0x0204
|
||||
#define REG_DWBCN0_CTRL_8723B REG_TDECTRL
|
||||
#define REG_TXDMA_OFFSET_CHK_8723B 0x020C
|
||||
#define REG_TXDMA_STATUS_8723B 0x0210
|
||||
#define REG_RQPN_NPQ_8723B 0x0214
|
||||
#define REG_DWBCN1_CTRL_8723B 0x0228
|
||||
|
||||
|
||||
/* */
|
||||
/* */
|
||||
/* 0x0280h ~ 0x02FFh RXDMA Configuration */
|
||||
/* */
|
||||
/* */
|
||||
#define REG_RXDMA_AGG_PG_TH_8723B 0x0280
|
||||
#define REG_FW_UPD_RDPTR_8723B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
|
||||
#define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */
|
||||
#define REG_RXPKT_NUM_8723B 0x0287 /* The number of packets in RXPKTBUF. */
|
||||
#define REG_RXDMA_STATUS_8723B 0x0288
|
||||
#define REG_RXDMA_PRO_8723B 0x0290
|
||||
#define REG_EARLY_MODE_CONTROL_8723B 0x02BC
|
||||
#define REG_RSVD5_8723B 0x02F0
|
||||
#define REG_RSVD6_8723B 0x02F4
|
||||
|
||||
|
||||
/* */
|
||||
/* */
|
||||
/* 0x0300h ~ 0x03FFh PCIe */
|
||||
/* */
|
||||
/* */
|
||||
#define REG_PCIE_CTRL_REG_8723B 0x0300
|
||||
#define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */
|
||||
#define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */
|
||||
#define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */
|
||||
#define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */
|
||||
#define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */
|
||||
#define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */
|
||||
#define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */
|
||||
#define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */
|
||||
#define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */
|
||||
#define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */
|
||||
#define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */
|
||||
#define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */
|
||||
#define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */
|
||||
#define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
|
||||
#define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */
|
||||
#define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */
|
||||
#define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */
|
||||
#define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */
|
||||
#define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */
|
||||
#define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
|
||||
|
||||
/* spec version 11 */
|
||||
/* */
|
||||
/* */
|
||||
/* 0x0400h ~ 0x047Fh Protocol Configuration */
|
||||
/* */
|
||||
/* */
|
||||
#define REG_VOQ_INFORMATION_8723B 0x0400
|
||||
#define REG_VIQ_INFORMATION_8723B 0x0404
|
||||
#define REG_BEQ_INFORMATION_8723B 0x0408
|
||||
#define REG_BKQ_INFORMATION_8723B 0x040C
|
||||
#define REG_MGQ_INFORMATION_8723B 0x0410
|
||||
#define REG_HGQ_INFORMATION_8723B 0x0414
|
||||
#define REG_BCNQ_INFORMATION_8723B 0x0418
|
||||
#define REG_TXPKT_EMPTY_8723B 0x041A
|
||||
|
||||
#define REG_FWHW_TXQ_CTRL_8723B 0x0420
|
||||
#define REG_HWSEQ_CTRL_8723B 0x0423
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424
|
||||
#define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425
|
||||
#define REG_LIFECTRL_CTRL_8723B 0x0426
|
||||
#define REG_MULTI_BCNQ_OFFSET_8723B 0x0427
|
||||
#define REG_SPEC_SIFS_8723B 0x0428
|
||||
#define REG_RL_8723B 0x042A
|
||||
#define REG_TXBF_CTRL_8723B 0x042C
|
||||
#define REG_DARFRC_8723B 0x0430
|
||||
#define REG_RARFRC_8723B 0x0438
|
||||
#define REG_RRSR_8723B 0x0440
|
||||
#define REG_ARFR0_8723B 0x0444
|
||||
#define REG_ARFR1_8723B 0x044C
|
||||
#define REG_CCK_CHECK_8723B 0x0454
|
||||
#define REG_AMPDU_MAX_TIME_8723B 0x0456
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY1_8723B 0x0457
|
||||
|
||||
#define REG_AMPDU_MAX_LENGTH_8723B 0x0458
|
||||
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D
|
||||
#define REG_NDPA_OPT_CTRL_8723B 0x045F
|
||||
#define REG_FAST_EDCA_CTRL_8723B 0x0460
|
||||
#define REG_RD_RESP_PKT_TH_8723B 0x0463
|
||||
#define REG_DATA_SC_8723B 0x0483
|
||||
#define REG_TXRPT_START_OFFSET 0x04AC
|
||||
#define REG_POWER_STAGE1_8723B 0x04B4
|
||||
#define REG_POWER_STAGE2_8723B 0x04B8
|
||||
#define REG_AMPDU_BURST_MODE_8723B 0x04BC
|
||||
#define REG_PKT_VO_VI_LIFE_TIME_8723B 0x04C0
|
||||
#define REG_PKT_BE_BK_LIFE_TIME_8723B 0x04C2
|
||||
#define REG_STBC_SETTING_8723B 0x04C4
|
||||
#define REG_HT_SINGLE_AMPDU_8723B 0x04C7
|
||||
#define REG_PROT_MODE_CTRL_8723B 0x04C8
|
||||
#define REG_MAX_AGGR_NUM_8723B 0x04CA
|
||||
#define REG_RTS_MAX_AGGR_NUM_8723B 0x04CB
|
||||
#define REG_BAR_MODE_CTRL_8723B 0x04CC
|
||||
#define REG_RA_TRY_RATE_AGG_LMT_8723B 0x04CF
|
||||
#define REG_MACID_PKT_DROP0_8723B 0x04D0
|
||||
#define REG_MACID_PKT_SLEEP_8723B 0x04D4
|
||||
|
||||
/* */
|
||||
/* */
|
||||
/* 0x0500h ~ 0x05FFh EDCA Configuration */
|
||||
/* */
|
||||
/* */
|
||||
#define REG_EDCA_VO_PARAM_8723B 0x0500
|
||||
#define REG_EDCA_VI_PARAM_8723B 0x0504
|
||||
#define REG_EDCA_BE_PARAM_8723B 0x0508
|
||||
#define REG_EDCA_BK_PARAM_8723B 0x050C
|
||||
#define REG_BCNTCFG_8723B 0x0510
|
||||
#define REG_PIFS_8723B 0x0512
|
||||
#define REG_RDG_PIFS_8723B 0x0513
|
||||
#define REG_SIFS_CTX_8723B 0x0514
|
||||
#define REG_SIFS_TRX_8723B 0x0516
|
||||
#define REG_AGGR_BREAK_TIME_8723B 0x051A
|
||||
#define REG_SLOT_8723B 0x051B
|
||||
#define REG_TX_PTCL_CTRL_8723B 0x0520
|
||||
#define REG_TXPAUSE_8723B 0x0522
|
||||
#define REG_DIS_TXREQ_CLR_8723B 0x0523
|
||||
#define REG_RD_CTRL_8723B 0x0524
|
||||
/* */
|
||||
/* Format for offset 540h-542h: */
|
||||
/* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */
|
||||
/* [7:4]: Reserved. */
|
||||
/* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. */
|
||||
/* [23:20]: Reserved */
|
||||
/* Description: */
|
||||
/* | */
|
||||
/* |<--Setup--|--Hold------------>| */
|
||||
/* --------------|---------------------- */
|
||||
/* | */
|
||||
/* TBTT */
|
||||
/* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */
|
||||
/* Described by Designer Tim and Bruce, 2011-01-14. */
|
||||
/* */
|
||||
#define REG_TBTT_PROHIBIT_8723B 0x0540
|
||||
#define REG_RD_NAV_NXT_8723B 0x0544
|
||||
#define REG_NAV_PROT_LEN_8723B 0x0546
|
||||
#define REG_BCN_CTRL_8723B 0x0550
|
||||
#define REG_BCN_CTRL_1_8723B 0x0551
|
||||
#define REG_MBID_NUM_8723B 0x0552
|
||||
#define REG_DUAL_TSF_RST_8723B 0x0553
|
||||
#define REG_BCN_INTERVAL_8723B 0x0554
|
||||
#define REG_DRVERLYINT_8723B 0x0558
|
||||
#define REG_BCNDMATIM_8723B 0x0559
|
||||
#define REG_ATIMWND_8723B 0x055A
|
||||
#define REG_USTIME_TSF_8723B 0x055C
|
||||
#define REG_BCN_MAX_ERR_8723B 0x055D
|
||||
#define REG_RXTSF_OFFSET_CCK_8723B 0x055E
|
||||
#define REG_RXTSF_OFFSET_OFDM_8723B 0x055F
|
||||
#define REG_TSFTR_8723B 0x0560
|
||||
#define REG_CTWND_8723B 0x0572
|
||||
#define REG_SECONDARY_CCA_CTRL_8723B 0x0577
|
||||
#define REG_PSTIMER_8723B 0x0580
|
||||
#define REG_TIMER0_8723B 0x0584
|
||||
#define REG_TIMER1_8723B 0x0588
|
||||
#define REG_ACMHWCTRL_8723B 0x05C0
|
||||
#define REG_SCH_TXCMD_8723B 0x05F8
|
||||
|
||||
/* 0x0600h ~ 0x07FFh WMAC Configuration */
|
||||
#define REG_MAC_CR_8723B 0x0600
|
||||
#define REG_TCR_8723B 0x0604
|
||||
#define REG_RCR_8723B 0x0608
|
||||
#define REG_RX_PKT_LIMIT_8723B 0x060C
|
||||
#define REG_RX_DLK_TIME_8723B 0x060D
|
||||
#define REG_RX_DRVINFO_SZ_8723B 0x060F
|
||||
|
||||
#define REG_MACID_8723B 0x0610
|
||||
#define REG_BSSID_8723B 0x0618
|
||||
#define REG_MAR_8723B 0x0620
|
||||
#define REG_MBIDCAMCFG_8723B 0x0628
|
||||
|
||||
#define REG_USTIME_EDCA_8723B 0x0638
|
||||
#define REG_MAC_SPEC_SIFS_8723B 0x063A
|
||||
#define REG_RESP_SIFP_CCK_8723B 0x063C
|
||||
#define REG_RESP_SIFS_OFDM_8723B 0x063E
|
||||
#define REG_ACKTO_8723B 0x0640
|
||||
#define REG_CTS2TO_8723B 0x0641
|
||||
#define REG_EIFS_8723B 0x0642
|
||||
|
||||
#define REG_NAV_UPPER_8723B 0x0652 /* unit of 128 */
|
||||
#define REG_TRXPTCL_CTL_8723B 0x0668
|
||||
|
||||
/* Security */
|
||||
#define REG_CAMCMD_8723B 0x0670
|
||||
#define REG_CAMWRITE_8723B 0x0674
|
||||
#define REG_CAMREAD_8723B 0x0678
|
||||
#define REG_CAMDBG_8723B 0x067C
|
||||
#define REG_SECCFG_8723B 0x0680
|
||||
|
||||
/* Power */
|
||||
#define REG_WOW_CTRL_8723B 0x0690
|
||||
#define REG_PS_RX_INFO_8723B 0x0692
|
||||
#define REG_UAPSD_TID_8723B 0x0693
|
||||
#define REG_WKFMCAM_CMD_8723B 0x0698
|
||||
#define REG_WKFMCAM_NUM_8723B 0x0698
|
||||
#define REG_WKFMCAM_RWD_8723B 0x069C
|
||||
#define REG_RXFLTMAP0_8723B 0x06A0
|
||||
#define REG_RXFLTMAP1_8723B 0x06A2
|
||||
#define REG_RXFLTMAP2_8723B 0x06A4
|
||||
#define REG_BCN_PSR_RPT_8723B 0x06A8
|
||||
#define REG_BT_COEX_TABLE_8723B 0x06C0
|
||||
#define REG_BFMER0_INFO_8723B 0x06E4
|
||||
#define REG_BFMER1_INFO_8723B 0x06EC
|
||||
#define REG_CSI_RPT_PARAM_BW20_8723B 0x06F4
|
||||
#define REG_CSI_RPT_PARAM_BW40_8723B 0x06F8
|
||||
#define REG_CSI_RPT_PARAM_BW80_8723B 0x06FC
|
||||
|
||||
/* Hardware Port 2 */
|
||||
#define REG_MACID1_8723B 0x0700
|
||||
#define REG_BSSID1_8723B 0x0708
|
||||
#define REG_BFMEE_SEL_8723B 0x0714
|
||||
#define REG_SND_PTCL_CTRL_8723B 0x0718
|
||||
|
||||
|
||||
/* Redifine 8192C register definition for compatibility */
|
||||
|
||||
/* TODO: use these definition when using REG_xxx naming rule. */
|
||||
/* NOTE: DO NOT Remove these definition. Use later. */
|
||||
#define EFUSE_CTRL_8723B REG_EFUSE_CTRL_8723B /* E-Fuse Control. */
|
||||
#define EFUSE_TEST_8723B REG_EFUSE_TEST_8723B /* E-Fuse Test. */
|
||||
#define MSR_8723B (REG_CR_8723B + 2) /* Media Status register */
|
||||
#define ISR_8723B REG_HISR0_8723B
|
||||
#define TSFR_8723B REG_TSFTR_8723B /* Timing Sync Function Timer Register. */
|
||||
|
||||
#define PBP_8723B REG_PBP_8723B
|
||||
|
||||
/* Redifine MACID register, to compatible prior ICs. */
|
||||
#define IDR0_8723B REG_MACID_8723B /* MAC ID Register, Offset 0x0050-0x0053 */
|
||||
#define IDR4_8723B (REG_MACID_8723B + 4) /* MAC ID Register, Offset 0x0054-0x0055 */
|
||||
|
||||
/* 9. Security Control Registers (Offset:) */
|
||||
#define RWCAM_8723B REG_CAMCMD_8723B /* IN 8190 Data Sheet is called CAMcmd */
|
||||
#define WCAMI_8723B REG_CAMWRITE_8723B /* Software write CAM input content */
|
||||
#define RCAMO_8723B REG_CAMREAD_8723B /* Software read/write CAM config */
|
||||
#define CAMDBG_8723B REG_CAMDBG_8723B
|
||||
#define SECR_8723B REG_SECCFG_8723B /* Security Configuration Register */
|
||||
|
||||
/* 8195 IMR/ISR bits (offset 0xB0, 8bits) */
|
||||
#define IMR_DISABLED_8723B 0
|
||||
/* IMR DW0(0x00B0-00B3) Bit 0-31 */
|
||||
#define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */
|
||||
#define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */
|
||||
#define IMR_PSTIMEOUT_8723B BIT29 /* Power Save Time Out Interrupt */
|
||||
#define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */
|
||||
#define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */
|
||||
#define IMR_TXBCN0ERR_8723B BIT26 /* Transmit Beacon0 Error */
|
||||
#define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */
|
||||
#define IMR_TSF_BIT32_TOGGLE_8723B BIT24 /* TSF Timer BIT32 toggle indication interrupt */
|
||||
#define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */
|
||||
#define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */
|
||||
#define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
|
||||
#define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */
|
||||
#define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */
|
||||
#define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */
|
||||
#define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */
|
||||
#define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */
|
||||
#define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */
|
||||
#define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */
|
||||
#define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */
|
||||
#define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */
|
||||
#define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */
|
||||
#define IMR_ROK_8723B BIT0 /* Receive DMA OK */
|
||||
|
||||
/* IMR DW1(0x00B4-00B7) Bit 0-31 */
|
||||
#define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */
|
||||
#define IMR_BCNDMAINT6_8723B BIT26 /* Beacon DMA Interrupt 6 */
|
||||
#define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */
|
||||
#define IMR_BCNDMAINT4_8723B BIT24 /* Beacon DMA Interrupt 4 */
|
||||
#define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */
|
||||
#define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */
|
||||
#define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */
|
||||
#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrup 7 */
|
||||
#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrup 6 */
|
||||
#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrup 5 */
|
||||
#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrup 4 */
|
||||
#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrup 3 */
|
||||
#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrup 2 */
|
||||
#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrup 1 */
|
||||
#define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension for Win7 */
|
||||
#define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */
|
||||
#define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */
|
||||
#define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */
|
||||
#define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */
|
||||
|
||||
/* 2 ACMHWCTRL 0x05C0 */
|
||||
#define AcmHw_HwEn_8723B BIT(0)
|
||||
#define AcmHw_VoqEn_8723B BIT(1)
|
||||
#define AcmHw_ViqEn_8723B BIT(2)
|
||||
#define AcmHw_BeqEn_8723B BIT(3)
|
||||
#define AcmHw_VoqStatus_8723B BIT(5)
|
||||
#define AcmHw_ViqStatus_8723B BIT(6)
|
||||
#define AcmHw_BeqStatus_8723B BIT(7)
|
||||
|
||||
/* 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */
|
||||
#define RCR_TCPOFLD_EN BIT25 /* Enable TCP checksum offload */
|
||||
|
||||
#endif /* #ifndef __INC_HAL8723BREG_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,193 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
/* The following is for 8723B 1ANT BT Co-exist definition */
|
||||
#define BT_INFO_8723B_1ANT_B_FTP BIT7
|
||||
#define BT_INFO_8723B_1ANT_B_A2DP BIT6
|
||||
#define BT_INFO_8723B_1ANT_B_HID BIT5
|
||||
#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
|
||||
#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
|
||||
#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
|
||||
#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
|
||||
#define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
|
||||
|
||||
#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
|
||||
(((_BT_INFO_EXT_&BIT0)) ? true : false)
|
||||
|
||||
#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2
|
||||
|
||||
#define BT_8723B_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */
|
||||
|
||||
typedef enum _BT_INFO_SRC_8723B_1ANT {
|
||||
BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0,
|
||||
BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1,
|
||||
BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2,
|
||||
BT_INFO_SRC_8723B_1ANT_MAX
|
||||
} BT_INFO_SRC_8723B_1ANT, *PBT_INFO_SRC_8723B_1ANT;
|
||||
|
||||
typedef enum _BT_8723B_1ANT_BT_STATUS {
|
||||
BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
|
||||
BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
|
||||
BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
|
||||
BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
|
||||
BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
|
||||
BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
|
||||
BT_8723B_1ANT_BT_STATUS_MAX
|
||||
} BT_8723B_1ANT_BT_STATUS, *PBT_8723B_1ANT_BT_STATUS;
|
||||
|
||||
typedef enum _BT_8723B_1ANT_WIFI_STATUS {
|
||||
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
|
||||
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
|
||||
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
|
||||
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
|
||||
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
|
||||
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
|
||||
BT_8723B_1ANT_WIFI_STATUS_MAX
|
||||
} BT_8723B_1ANT_WIFI_STATUS, *PBT_8723B_1ANT_WIFI_STATUS;
|
||||
|
||||
typedef enum _BT_8723B_1ANT_COEX_ALGO {
|
||||
BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
|
||||
BT_8723B_1ANT_COEX_ALGO_SCO = 0x1,
|
||||
BT_8723B_1ANT_COEX_ALGO_HID = 0x2,
|
||||
BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3,
|
||||
BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
|
||||
BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5,
|
||||
BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6,
|
||||
BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
|
||||
BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
|
||||
BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
|
||||
BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
|
||||
BT_8723B_1ANT_COEX_ALGO_MAX = 0xb,
|
||||
} BT_8723B_1ANT_COEX_ALGO, *PBT_8723B_1ANT_COEX_ALGO;
|
||||
|
||||
typedef struct _COEX_DM_8723B_1ANT {
|
||||
/* fw mechanism */
|
||||
bool bCurIgnoreWlanAct;
|
||||
bool bPreIgnoreWlanAct;
|
||||
u8 prePsTdma;
|
||||
u8 curPsTdma;
|
||||
u8 psTdmaPara[5];
|
||||
u8 psTdmaDuAdjType;
|
||||
bool bAutoTdmaAdjust;
|
||||
bool bPrePsTdmaOn;
|
||||
bool bCurPsTdmaOn;
|
||||
bool bPreBtAutoReport;
|
||||
bool bCurBtAutoReport;
|
||||
u8 preLps;
|
||||
u8 curLps;
|
||||
u8 preRpwm;
|
||||
u8 curRpwm;
|
||||
|
||||
/* sw mechanism */
|
||||
bool bPreLowPenaltyRa;
|
||||
bool bCurLowPenaltyRa;
|
||||
u32 preVal0x6c0;
|
||||
u32 curVal0x6c0;
|
||||
u32 preVal0x6c4;
|
||||
u32 curVal0x6c4;
|
||||
u32 preVal0x6c8;
|
||||
u32 curVal0x6c8;
|
||||
u8 preVal0x6cc;
|
||||
u8 curVal0x6cc;
|
||||
bool bLimitedDig;
|
||||
|
||||
u32 backupArfrCnt1; /* Auto Rate Fallback Retry cnt */
|
||||
u32 backupArfrCnt2; /* Auto Rate Fallback Retry cnt */
|
||||
u16 backupRetryLimit;
|
||||
u8 backupAmpduMaxTime;
|
||||
|
||||
/* algorithm related */
|
||||
u8 preAlgorithm;
|
||||
u8 curAlgorithm;
|
||||
u8 btStatus;
|
||||
u8 wifiChnlInfo[3];
|
||||
|
||||
u32 preRaMask;
|
||||
u32 curRaMask;
|
||||
u8 preArfrType;
|
||||
u8 curArfrType;
|
||||
u8 preRetryLimitType;
|
||||
u8 curRetryLimitType;
|
||||
u8 preAmpduTimeType;
|
||||
u8 curAmpduTimeType;
|
||||
u32 nArpCnt;
|
||||
|
||||
u8 errorCondition;
|
||||
} COEX_DM_8723B_1ANT, *PCOEX_DM_8723B_1ANT;
|
||||
|
||||
typedef struct _COEX_STA_8723B_1ANT {
|
||||
bool bBtLinkExist;
|
||||
bool bScoExist;
|
||||
bool bA2dpExist;
|
||||
bool bHidExist;
|
||||
bool bPanExist;
|
||||
|
||||
bool bUnderLps;
|
||||
bool bUnderIps;
|
||||
u32 specialPktPeriodCnt;
|
||||
u32 highPriorityTx;
|
||||
u32 highPriorityRx;
|
||||
u32 lowPriorityTx;
|
||||
u32 lowPriorityRx;
|
||||
s8 btRssi;
|
||||
bool bBtTxRxMask;
|
||||
u8 preBtRssiState;
|
||||
u8 preWifiRssiState[4];
|
||||
bool bC2hBtInfoReqSent;
|
||||
u8 btInfoC2h[BT_INFO_SRC_8723B_1ANT_MAX][10];
|
||||
u32 btInfoC2hCnt[BT_INFO_SRC_8723B_1ANT_MAX];
|
||||
bool bC2hBtInquiryPage;
|
||||
bool bC2hBtPage; /* Add for win8.1 page out issue */
|
||||
bool bWiFiIsHighPriTask; /* Add for win8.1 page out issue */
|
||||
u8 btRetryCnt;
|
||||
u8 btInfoExt;
|
||||
u32 popEventCnt;
|
||||
u8 nScanAPNum;
|
||||
|
||||
u32 nCRCOK_CCK;
|
||||
u32 nCRCOK_11g;
|
||||
u32 nCRCOK_11n;
|
||||
u32 nCRCOK_11nAgg;
|
||||
|
||||
u32 nCRCErr_CCK;
|
||||
u32 nCRCErr_11g;
|
||||
u32 nCRCErr_11n;
|
||||
u32 nCRCErr_11nAgg;
|
||||
|
||||
bool bCCKLock;
|
||||
bool bPreCCKLock;
|
||||
u8 nCoexTableType;
|
||||
|
||||
bool bForceLpsOn;
|
||||
} COEX_STA_8723B_1ANT, *PCOEX_STA_8723B_1ANT;
|
||||
|
||||
/* */
|
||||
/* The following is interface which will notify coex module. */
|
||||
/* */
|
||||
void EXhalbtc8723b1ant_PowerOnSetting(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtc8723b1ant_InitHwConfig(PBTC_COEXIST pBtCoexist, bool bWifiOnly);
|
||||
void EXhalbtc8723b1ant_InitCoexDm(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtc8723b1ant_IpsNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b1ant_LpsNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b1ant_ScanNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b1ant_ConnectNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b1ant_MediaStatusNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b1ant_SpecialPacketNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b1ant_BtInfoNotify(
|
||||
PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length
|
||||
);
|
||||
void EXhalbtc8723b1ant_HaltNotify(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtc8723b1ant_PnpNotify(PBTC_COEXIST pBtCoexist, u8 pnpState);
|
||||
void EXhalbtc8723b1ant_Periodical(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtc8723b1ant_DisplayCoexInfo(PBTC_COEXIST pBtCoexist);
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,155 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
/* The following is for 8723B 2Ant BT Co-exist definition */
|
||||
#define BT_INFO_8723B_2ANT_B_FTP BIT7
|
||||
#define BT_INFO_8723B_2ANT_B_A2DP BIT6
|
||||
#define BT_INFO_8723B_2ANT_B_HID BIT5
|
||||
#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
|
||||
#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
|
||||
#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
|
||||
#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
|
||||
#define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
|
||||
|
||||
#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2
|
||||
|
||||
typedef enum _BT_INFO_SRC_8723B_2ANT {
|
||||
BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0,
|
||||
BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1,
|
||||
BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2,
|
||||
BT_INFO_SRC_8723B_2ANT_MAX
|
||||
} BT_INFO_SRC_8723B_2ANT, *PBT_INFO_SRC_8723B_2ANT;
|
||||
|
||||
typedef enum _BT_8723B_2ANT_BT_STATUS {
|
||||
BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
|
||||
BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
|
||||
BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
|
||||
BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
|
||||
BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
|
||||
BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
|
||||
BT_8723B_2ANT_BT_STATUS_MAX
|
||||
} BT_8723B_2ANT_BT_STATUS, *PBT_8723B_2ANT_BT_STATUS;
|
||||
|
||||
typedef enum _BT_8723B_2ANT_COEX_ALGO {
|
||||
BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
|
||||
BT_8723B_2ANT_COEX_ALGO_SCO = 0x1,
|
||||
BT_8723B_2ANT_COEX_ALGO_HID = 0x2,
|
||||
BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3,
|
||||
BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
|
||||
BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5,
|
||||
BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6,
|
||||
BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
|
||||
BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
|
||||
BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
|
||||
BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
|
||||
BT_8723B_2ANT_COEX_ALGO_MAX = 0xb,
|
||||
} BT_8723B_2ANT_COEX_ALGO, *PBT_8723B_2ANT_COEX_ALGO;
|
||||
|
||||
typedef struct _COEX_DM_8723B_2ANT {
|
||||
/* fw mechanism */
|
||||
u8 preBtDecPwrLvl;
|
||||
u8 curBtDecPwrLvl;
|
||||
u8 preFwDacSwingLvl;
|
||||
u8 curFwDacSwingLvl;
|
||||
bool bCurIgnoreWlanAct;
|
||||
bool bPreIgnoreWlanAct;
|
||||
u8 prePsTdma;
|
||||
u8 curPsTdma;
|
||||
u8 psTdmaPara[5];
|
||||
u8 psTdmaDuAdjType;
|
||||
bool bResetTdmaAdjust;
|
||||
bool bAutoTdmaAdjust;
|
||||
bool bPrePsTdmaOn;
|
||||
bool bCurPsTdmaOn;
|
||||
bool bPreBtAutoReport;
|
||||
bool bCurBtAutoReport;
|
||||
|
||||
/* sw mechanism */
|
||||
bool bPreRfRxLpfShrink;
|
||||
bool bCurRfRxLpfShrink;
|
||||
u32 btRf0x1eBackup;
|
||||
bool bPreLowPenaltyRa;
|
||||
bool bCurLowPenaltyRa;
|
||||
bool bPreDacSwingOn;
|
||||
u32 preDacSwingLvl;
|
||||
bool bCurDacSwingOn;
|
||||
u32 curDacSwingLvl;
|
||||
bool bPreAdcBackOff;
|
||||
bool bCurAdcBackOff;
|
||||
bool bPreAgcTableEn;
|
||||
bool bCurAgcTableEn;
|
||||
u32 preVal0x6c0;
|
||||
u32 curVal0x6c0;
|
||||
u32 preVal0x6c4;
|
||||
u32 curVal0x6c4;
|
||||
u32 preVal0x6c8;
|
||||
u32 curVal0x6c8;
|
||||
u8 preVal0x6cc;
|
||||
u8 curVal0x6cc;
|
||||
bool bLimitedDig;
|
||||
|
||||
/* algorithm related */
|
||||
u8 preAlgorithm;
|
||||
u8 curAlgorithm;
|
||||
u8 btStatus;
|
||||
u8 wifiChnlInfo[3];
|
||||
|
||||
bool bNeedRecover0x948;
|
||||
u32 backup0x948;
|
||||
} COEX_DM_8723B_2ANT, *PCOEX_DM_8723B_2ANT;
|
||||
|
||||
typedef struct _COEX_STA_8723B_2ANT {
|
||||
bool bBtLinkExist;
|
||||
bool bScoExist;
|
||||
bool bA2dpExist;
|
||||
bool bHidExist;
|
||||
bool bPanExist;
|
||||
|
||||
bool bUnderLps;
|
||||
bool bUnderIps;
|
||||
u32 highPriorityTx;
|
||||
u32 highPriorityRx;
|
||||
u32 lowPriorityTx;
|
||||
u32 lowPriorityRx;
|
||||
u8 btRssi;
|
||||
bool bBtTxRxMask;
|
||||
u8 preBtRssiState;
|
||||
u8 preWifiRssiState[4];
|
||||
bool bC2hBtInfoReqSent;
|
||||
u8 btInfoC2h[BT_INFO_SRC_8723B_2ANT_MAX][10];
|
||||
u32 btInfoC2hCnt[BT_INFO_SRC_8723B_2ANT_MAX];
|
||||
bool bC2hBtInquiryPage;
|
||||
u8 btRetryCnt;
|
||||
u8 btInfoExt;
|
||||
} COEX_STA_8723B_2ANT, *PCOEX_STA_8723B_2ANT;
|
||||
|
||||
/* */
|
||||
/* The following is interface which will notify coex module. */
|
||||
/* */
|
||||
void EXhalbtc8723b2ant_PowerOnSetting(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtc8723b2ant_InitHwConfig(PBTC_COEXIST pBtCoexist, bool bWifiOnly);
|
||||
void EXhalbtc8723b2ant_InitCoexDm(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtc8723b2ant_IpsNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b2ant_LpsNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b2ant_ScanNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b2ant_ConnectNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b2ant_MediaStatusNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b2ant_SpecialPacketNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtc8723b2ant_BtInfoNotify(
|
||||
PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length
|
||||
);
|
||||
void EXhalbtc8723b2ant_HaltNotify(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtc8723b2ant_PnpNotify(PBTC_COEXIST pBtCoexist, u8 pnpState);
|
||||
void EXhalbtc8723b2ant_Periodical(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtc8723b2ant_DisplayCoexInfo(PBTC_COEXIST pBtCoexist);
|
||||
|
|
@ -0,0 +1,565 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __HALBTC_OUT_SRC_H__
|
||||
#define __HALBTC_OUT_SRC_H__
|
||||
|
||||
#define NORMAL_EXEC false
|
||||
#define FORCE_EXEC true
|
||||
|
||||
#define BTC_RF_OFF 0x0
|
||||
#define BTC_RF_ON 0x1
|
||||
|
||||
#define BTC_RF_A 0x0
|
||||
#define BTC_RF_B 0x1
|
||||
#define BTC_RF_C 0x2
|
||||
#define BTC_RF_D 0x3
|
||||
|
||||
#define BTC_SMSP SINGLEMAC_SINGLEPHY
|
||||
#define BTC_DMDP DUALMAC_DUALPHY
|
||||
#define BTC_DMSP DUALMAC_SINGLEPHY
|
||||
#define BTC_MP_UNKNOWN 0xff
|
||||
|
||||
#define BT_COEX_ANT_TYPE_PG 0
|
||||
#define BT_COEX_ANT_TYPE_ANTDIV 1
|
||||
#define BT_COEX_ANT_TYPE_DETECTED 2
|
||||
|
||||
#define BTC_MIMO_PS_STATIC 0 /* 1ss */
|
||||
#define BTC_MIMO_PS_DYNAMIC 1 /* 2ss */
|
||||
|
||||
#define BTC_RATE_DISABLE 0
|
||||
#define BTC_RATE_ENABLE 1
|
||||
|
||||
/* single Antenna definition */
|
||||
#define BTC_ANT_PATH_WIFI 0
|
||||
#define BTC_ANT_PATH_BT 1
|
||||
#define BTC_ANT_PATH_PTA 2
|
||||
/* dual Antenna definition */
|
||||
#define BTC_ANT_WIFI_AT_MAIN 0
|
||||
#define BTC_ANT_WIFI_AT_AUX 1
|
||||
/* coupler Antenna definition */
|
||||
#define BTC_ANT_WIFI_AT_CPL_MAIN 0
|
||||
#define BTC_ANT_WIFI_AT_CPL_AUX 1
|
||||
|
||||
typedef enum _BTC_POWERSAVE_TYPE{
|
||||
BTC_PS_WIFI_NATIVE = 0, /* wifi original power save behavior */
|
||||
BTC_PS_LPS_ON = 1,
|
||||
BTC_PS_LPS_OFF = 2,
|
||||
BTC_PS_MAX
|
||||
} BTC_POWERSAVE_TYPE, *PBTC_POWERSAVE_TYPE;
|
||||
|
||||
typedef enum _BTC_BT_REG_TYPE{
|
||||
BTC_BT_REG_RF = 0,
|
||||
BTC_BT_REG_MODEM = 1,
|
||||
BTC_BT_REG_BLUEWIZE = 2,
|
||||
BTC_BT_REG_VENDOR = 3,
|
||||
BTC_BT_REG_LE = 4,
|
||||
BTC_BT_REG_MAX
|
||||
} BTC_BT_REG_TYPE, *PBTC_BT_REG_TYPE;
|
||||
|
||||
typedef enum _BTC_CHIP_INTERFACE{
|
||||
BTC_INTF_UNKNOWN = 0,
|
||||
BTC_INTF_PCI = 1,
|
||||
BTC_INTF_USB = 2,
|
||||
BTC_INTF_SDIO = 3,
|
||||
BTC_INTF_MAX
|
||||
} BTC_CHIP_INTERFACE, *PBTC_CHIP_INTERFACE;
|
||||
|
||||
typedef enum _BTC_CHIP_TYPE {
|
||||
BTC_CHIP_UNDEF = 0,
|
||||
BTC_CHIP_CSR_BC4 = 1,
|
||||
BTC_CHIP_CSR_BC8 = 2,
|
||||
BTC_CHIP_RTL8723A = 3,
|
||||
BTC_CHIP_RTL8821 = 4,
|
||||
BTC_CHIP_RTL8723B = 5,
|
||||
BTC_CHIP_MAX
|
||||
} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE;
|
||||
|
||||
typedef enum _BTC_MSG_TYPE {
|
||||
BTC_MSG_INTERFACE = 0x0,
|
||||
BTC_MSG_ALGORITHM = 0x1,
|
||||
BTC_MSG_MAX
|
||||
} BTC_MSG_TYPE;
|
||||
extern u32 GLBtcDbgType[];
|
||||
|
||||
/* following is for BTC_MSG_INTERFACE */
|
||||
#define INTF_INIT BIT0
|
||||
#define INTF_NOTIFY BIT2
|
||||
|
||||
/* following is for BTC_ALGORITHM */
|
||||
#define ALGO_BT_RSSI_STATE BIT0
|
||||
#define ALGO_WIFI_RSSI_STATE BIT1
|
||||
#define ALGO_BT_MONITOR BIT2
|
||||
#define ALGO_TRACE BIT3
|
||||
#define ALGO_TRACE_FW BIT4
|
||||
#define ALGO_TRACE_FW_DETAIL BIT5
|
||||
#define ALGO_TRACE_FW_EXEC BIT6
|
||||
#define ALGO_TRACE_SW BIT7
|
||||
#define ALGO_TRACE_SW_DETAIL BIT8
|
||||
#define ALGO_TRACE_SW_EXEC BIT9
|
||||
|
||||
/* following is for wifi link status */
|
||||
#define WIFI_STA_CONNECTED BIT0
|
||||
#define WIFI_AP_CONNECTED BIT1
|
||||
#define WIFI_HS_CONNECTED BIT2
|
||||
#define WIFI_P2P_GO_CONNECTED BIT3
|
||||
#define WIFI_P2P_GC_CONNECTED BIT4
|
||||
|
||||
/* following is for command line utility */
|
||||
#define CL_SPRINTF snprintf
|
||||
#define CL_PRINTF DCMD_Printf
|
||||
|
||||
/* The following is for dbgview print */
|
||||
#if DBG
|
||||
#define BTC_PRINT(dbgtype, dbgflag, printstr)\
|
||||
{\
|
||||
if (GLBtcDbgType[dbgtype] & dbgflag)\
|
||||
DbgPrint printstr;\
|
||||
}
|
||||
|
||||
#define BTC_PRINT_F(dbgtype, dbgflag, printstr)\
|
||||
{\
|
||||
if (GLBtcDbgType[dbgtype] & dbgflag) {\
|
||||
DbgPrint("%s(): ", __func__);\
|
||||
DbgPrint printstr;\
|
||||
} \
|
||||
}
|
||||
|
||||
#define BTC_PRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)\
|
||||
{\
|
||||
if (GLBtcDbgType[dbgtype] & dbgflag) {\
|
||||
int __i;\
|
||||
u8 *ptr = (u8 *)_Ptr;\
|
||||
DbgPrint printstr;\
|
||||
DbgPrint(" ");\
|
||||
for (__i = 0; __i < 6; __i++)\
|
||||
DbgPrint("%02X%s", ptr[__i], (__i == 5) ? "" : "-");\
|
||||
DbgPrint("\n");\
|
||||
} \
|
||||
}
|
||||
|
||||
#define BTC_PRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\
|
||||
{\
|
||||
if (GLBtcDbgType[dbgtype] & dbgflag) {\
|
||||
int __i;\
|
||||
u8 *ptr = (u8 *)_HexData;\
|
||||
DbgPrint(_TitleString);\
|
||||
for (__i = 0; __i < (int)_HexDataLen; __i++) {\
|
||||
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " ");\
|
||||
if (((__i + 1) % 16) == 0)\
|
||||
DbgPrint("\n");\
|
||||
} \
|
||||
DbgPrint("\n");\
|
||||
} \
|
||||
}
|
||||
|
||||
#else
|
||||
#define BTC_PRINT(dbgtype, dbgflag, printstr)
|
||||
#define BTC_PRINT_F(dbgtype, dbgflag, printstr)
|
||||
#define BTC_PRINT_ADDR(dbgtype, dbgflag, printstr, _Ptr)
|
||||
#define BTC_PRINT_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)
|
||||
#endif
|
||||
|
||||
typedef struct _BTC_BOARD_INFO {
|
||||
/* The following is some board information */
|
||||
u8 btChipType;
|
||||
u8 pgAntNum; /* pg ant number */
|
||||
u8 btdmAntNum; /* ant number for btdm */
|
||||
u8 btdmAntPos; /* Bryant Add to indicate Antenna Position for (pgAntNum = 2) && (btdmAntNum = 1) (DPDT+1Ant case) */
|
||||
u8 singleAntPath; /* current used for 8723b only, 1 =>s0, 0 =>s1 */
|
||||
/* bool bBtExist; */
|
||||
} BTC_BOARD_INFO, *PBTC_BOARD_INFO;
|
||||
|
||||
typedef enum _BTC_DBG_OPCODE {
|
||||
BTC_DBG_SET_COEX_NORMAL = 0x0,
|
||||
BTC_DBG_SET_COEX_WIFI_ONLY = 0x1,
|
||||
BTC_DBG_SET_COEX_BT_ONLY = 0x2,
|
||||
BTC_DBG_SET_COEX_DEC_BT_PWR = 0x3,
|
||||
BTC_DBG_SET_COEX_BT_AFH_MAP = 0x4,
|
||||
BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT = 0x5,
|
||||
BTC_DBG_MAX
|
||||
} BTC_DBG_OPCODE, *PBTC_DBG_OPCODE;
|
||||
|
||||
typedef enum _BTC_RSSI_STATE {
|
||||
BTC_RSSI_STATE_HIGH = 0x0,
|
||||
BTC_RSSI_STATE_MEDIUM = 0x1,
|
||||
BTC_RSSI_STATE_LOW = 0x2,
|
||||
BTC_RSSI_STATE_STAY_HIGH = 0x3,
|
||||
BTC_RSSI_STATE_STAY_MEDIUM = 0x4,
|
||||
BTC_RSSI_STATE_STAY_LOW = 0x5,
|
||||
BTC_RSSI_MAX
|
||||
} BTC_RSSI_STATE, *PBTC_RSSI_STATE;
|
||||
#define BTC_RSSI_HIGH(_rssi_) ((_rssi_ == BTC_RSSI_STATE_HIGH || _rssi_ == BTC_RSSI_STATE_STAY_HIGH) ? true : false)
|
||||
#define BTC_RSSI_MEDIUM(_rssi_) ((_rssi_ == BTC_RSSI_STATE_MEDIUM || _rssi_ == BTC_RSSI_STATE_STAY_MEDIUM) ? true : false)
|
||||
#define BTC_RSSI_LOW(_rssi_) ((_rssi_ == BTC_RSSI_STATE_LOW || _rssi_ == BTC_RSSI_STATE_STAY_LOW) ? true : false)
|
||||
|
||||
typedef enum _BTC_WIFI_ROLE {
|
||||
BTC_ROLE_STATION = 0x0,
|
||||
BTC_ROLE_AP = 0x1,
|
||||
BTC_ROLE_IBSS = 0x2,
|
||||
BTC_ROLE_HS_MODE = 0x3,
|
||||
BTC_ROLE_MAX
|
||||
} BTC_WIFI_ROLE, *PBTC_WIFI_ROLE;
|
||||
|
||||
typedef enum _BTC_WIFI_BW_MODE {
|
||||
BTC_WIFI_BW_LEGACY = 0x0,
|
||||
BTC_WIFI_BW_HT20 = 0x1,
|
||||
BTC_WIFI_BW_HT40 = 0x2,
|
||||
BTC_WIFI_BW_MAX
|
||||
} BTC_WIFI_BW_MODE, *PBTC_WIFI_BW_MODE;
|
||||
|
||||
typedef enum _BTC_WIFI_TRAFFIC_DIR {
|
||||
BTC_WIFI_TRAFFIC_TX = 0x0,
|
||||
BTC_WIFI_TRAFFIC_RX = 0x1,
|
||||
BTC_WIFI_TRAFFIC_MAX
|
||||
} BTC_WIFI_TRAFFIC_DIR, *PBTC_WIFI_TRAFFIC_DIR;
|
||||
|
||||
typedef enum _BTC_WIFI_PNP {
|
||||
BTC_WIFI_PNP_WAKE_UP = 0x0,
|
||||
BTC_WIFI_PNP_SLEEP = 0x1,
|
||||
BTC_WIFI_PNP_MAX
|
||||
} BTC_WIFI_PNP, *PBTC_WIFI_PNP;
|
||||
|
||||
/* for 8723b-d cut large current issue */
|
||||
typedef enum _BT_WIFI_COEX_STATE {
|
||||
BTC_WIFI_STAT_INIT,
|
||||
BTC_WIFI_STAT_IQK,
|
||||
BTC_WIFI_STAT_NORMAL_OFF,
|
||||
BTC_WIFI_STAT_MP_OFF,
|
||||
BTC_WIFI_STAT_NORMAL,
|
||||
BTC_WIFI_STAT_ANT_DIV,
|
||||
BTC_WIFI_STAT_MAX
|
||||
} BT_WIFI_COEX_STATE, *PBT_WIFI_COEX_STATE;
|
||||
|
||||
/* defined for BFP_BTC_GET */
|
||||
typedef enum _BTC_GET_TYPE {
|
||||
/* type bool */
|
||||
BTC_GET_BL_HS_OPERATION,
|
||||
BTC_GET_BL_HS_CONNECTING,
|
||||
BTC_GET_BL_WIFI_CONNECTED,
|
||||
BTC_GET_BL_WIFI_BUSY,
|
||||
BTC_GET_BL_WIFI_SCAN,
|
||||
BTC_GET_BL_WIFI_LINK,
|
||||
BTC_GET_BL_WIFI_ROAM,
|
||||
BTC_GET_BL_WIFI_4_WAY_PROGRESS,
|
||||
BTC_GET_BL_WIFI_UNDER_5G,
|
||||
BTC_GET_BL_WIFI_AP_MODE_ENABLE,
|
||||
BTC_GET_BL_WIFI_ENABLE_ENCRYPTION,
|
||||
BTC_GET_BL_WIFI_UNDER_B_MODE,
|
||||
BTC_GET_BL_EXT_SWITCH,
|
||||
BTC_GET_BL_WIFI_IS_IN_MP_MODE,
|
||||
|
||||
/* type s32 */
|
||||
BTC_GET_S4_WIFI_RSSI,
|
||||
BTC_GET_S4_HS_RSSI,
|
||||
|
||||
/* type u32 */
|
||||
BTC_GET_U4_WIFI_BW,
|
||||
BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
|
||||
BTC_GET_U4_WIFI_FW_VER,
|
||||
BTC_GET_U4_WIFI_LINK_STATUS,
|
||||
BTC_GET_U4_BT_PATCH_VER,
|
||||
|
||||
/* type u8 */
|
||||
BTC_GET_U1_WIFI_DOT11_CHNL,
|
||||
BTC_GET_U1_WIFI_CENTRAL_CHNL,
|
||||
BTC_GET_U1_WIFI_HS_CHNL,
|
||||
BTC_GET_U1_MAC_PHY_MODE,
|
||||
BTC_GET_U1_AP_NUM,
|
||||
|
||||
/* for 1Ant ====== */
|
||||
BTC_GET_U1_LPS_MODE,
|
||||
|
||||
BTC_GET_MAX
|
||||
} BTC_GET_TYPE, *PBTC_GET_TYPE;
|
||||
|
||||
/* defined for BFP_BTC_SET */
|
||||
typedef enum _BTC_SET_TYPE {
|
||||
/* type bool */
|
||||
BTC_SET_BL_BT_DISABLE,
|
||||
BTC_SET_BL_BT_TRAFFIC_BUSY,
|
||||
BTC_SET_BL_BT_LIMITED_DIG,
|
||||
BTC_SET_BL_FORCE_TO_ROAM,
|
||||
BTC_SET_BL_TO_REJ_AP_AGG_PKT,
|
||||
BTC_SET_BL_BT_CTRL_AGG_SIZE,
|
||||
BTC_SET_BL_INC_SCAN_DEV_NUM,
|
||||
BTC_SET_BL_BT_TX_RX_MASK,
|
||||
|
||||
/* type u8 */
|
||||
BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
|
||||
BTC_SET_U1_AGG_BUF_SIZE,
|
||||
|
||||
/* type trigger some action */
|
||||
BTC_SET_ACT_GET_BT_RSSI,
|
||||
BTC_SET_ACT_AGGREGATE_CTRL,
|
||||
/* for 1Ant ====== */
|
||||
/* type bool */
|
||||
|
||||
/* type u8 */
|
||||
BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
|
||||
BTC_SET_U1_LPS_VAL,
|
||||
BTC_SET_U1_RPWM_VAL,
|
||||
/* type trigger some action */
|
||||
BTC_SET_ACT_LEAVE_LPS,
|
||||
BTC_SET_ACT_ENTER_LPS,
|
||||
BTC_SET_ACT_NORMAL_LPS,
|
||||
BTC_SET_ACT_DISABLE_LOW_POWER,
|
||||
BTC_SET_ACT_UPDATE_RAMASK,
|
||||
BTC_SET_ACT_SEND_MIMO_PS,
|
||||
/* BT Coex related */
|
||||
BTC_SET_ACT_CTRL_BT_INFO,
|
||||
BTC_SET_ACT_CTRL_BT_COEX,
|
||||
BTC_SET_ACT_CTRL_8723B_ANT,
|
||||
/* */
|
||||
BTC_SET_MAX
|
||||
} BTC_SET_TYPE, *PBTC_SET_TYPE;
|
||||
|
||||
typedef enum _BTC_DBG_DISP_TYPE {
|
||||
BTC_DBG_DISP_COEX_STATISTICS = 0x0,
|
||||
BTC_DBG_DISP_BT_LINK_INFO = 0x1,
|
||||
BTC_DBG_DISP_FW_PWR_MODE_CMD = 0x2,
|
||||
BTC_DBG_DISP_MAX
|
||||
} BTC_DBG_DISP_TYPE, *PBTC_DBG_DISP_TYPE;
|
||||
|
||||
typedef enum _BTC_NOTIFY_TYPE_IPS {
|
||||
BTC_IPS_LEAVE = 0x0,
|
||||
BTC_IPS_ENTER = 0x1,
|
||||
BTC_IPS_MAX
|
||||
} BTC_NOTIFY_TYPE_IPS, *PBTC_NOTIFY_TYPE_IPS;
|
||||
|
||||
typedef enum _BTC_NOTIFY_TYPE_LPS {
|
||||
BTC_LPS_DISABLE = 0x0,
|
||||
BTC_LPS_ENABLE = 0x1,
|
||||
BTC_LPS_MAX
|
||||
} BTC_NOTIFY_TYPE_LPS, *PBTC_NOTIFY_TYPE_LPS;
|
||||
|
||||
typedef enum _BTC_NOTIFY_TYPE_SCAN {
|
||||
BTC_SCAN_FINISH = 0x0,
|
||||
BTC_SCAN_START = 0x1,
|
||||
BTC_SCAN_MAX
|
||||
} BTC_NOTIFY_TYPE_SCAN, *PBTC_NOTIFY_TYPE_SCAN;
|
||||
|
||||
typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE {
|
||||
BTC_ASSOCIATE_FINISH = 0x0,
|
||||
BTC_ASSOCIATE_START = 0x1,
|
||||
BTC_ASSOCIATE_MAX
|
||||
} BTC_NOTIFY_TYPE_ASSOCIATE, *PBTC_NOTIFY_TYPE_ASSOCIATE;
|
||||
|
||||
typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS {
|
||||
BTC_MEDIA_DISCONNECT = 0x0,
|
||||
BTC_MEDIA_CONNECT = 0x1,
|
||||
BTC_MEDIA_MAX
|
||||
} BTC_NOTIFY_TYPE_MEDIA_STATUS, *PBTC_NOTIFY_TYPE_MEDIA_STATUS;
|
||||
|
||||
typedef enum _BTC_NOTIFY_TYPE_SPECIAL_PACKET {
|
||||
BTC_PACKET_UNKNOWN = 0x0,
|
||||
BTC_PACKET_DHCP = 0x1,
|
||||
BTC_PACKET_ARP = 0x2,
|
||||
BTC_PACKET_EAPOL = 0x3,
|
||||
BTC_PACKET_MAX
|
||||
} BTC_NOTIFY_TYPE_SPECIAL_PACKET, *PBTC_NOTIFY_TYPE_SPECIAL_PACKET;
|
||||
|
||||
typedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION {
|
||||
BTC_STACK_OP_NONE = 0x0,
|
||||
BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1,
|
||||
BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2,
|
||||
BTC_STACK_OP_MAX
|
||||
} BTC_NOTIFY_TYPE_STACK_OPERATION, *PBTC_NOTIFY_TYPE_STACK_OPERATION;
|
||||
|
||||
/* Bryant Add */
|
||||
typedef enum _BTC_ANTENNA_POS {
|
||||
BTC_ANTENNA_AT_MAIN_PORT = 0x1,
|
||||
BTC_ANTENNA_AT_AUX_PORT = 0x2,
|
||||
} BTC_ANTENNA_POS, *PBTC_ANTENNA_POS;
|
||||
|
||||
typedef u8 (*BFP_BTC_R1)(void *pBtcContext, u32 RegAddr);
|
||||
typedef u16(*BFP_BTC_R2)(void *pBtcContext, u32 RegAddr);
|
||||
typedef u32 (*BFP_BTC_R4)(void *pBtcContext, u32 RegAddr);
|
||||
typedef void (*BFP_BTC_W1)(void *pBtcContext, u32 RegAddr, u8 Data);
|
||||
typedef void(*BFP_BTC_W1_BIT_MASK)(
|
||||
void *pBtcContext, u32 regAddr, u8 bitMask, u8 data1b
|
||||
);
|
||||
typedef void (*BFP_BTC_W2)(void *pBtcContext, u32 RegAddr, u16 Data);
|
||||
typedef void (*BFP_BTC_W4)(void *pBtcContext, u32 RegAddr, u32 Data);
|
||||
typedef void (*BFP_BTC_LOCAL_REG_W1)(void *pBtcContext, u32 RegAddr, u8 Data);
|
||||
typedef void (*BFP_BTC_SET_BB_REG)(
|
||||
void *pBtcContext, u32 RegAddr, u32 BitMask, u32 Data
|
||||
);
|
||||
typedef u32 (*BFP_BTC_GET_BB_REG)(void *pBtcContext, u32 RegAddr, u32 BitMask);
|
||||
typedef void (*BFP_BTC_SET_RF_REG)(
|
||||
void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data
|
||||
);
|
||||
typedef u32 (*BFP_BTC_GET_RF_REG)(
|
||||
void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask
|
||||
);
|
||||
typedef void (*BFP_BTC_FILL_H2C)(
|
||||
void *pBtcContext, u8 elementId, u32 cmdLen, u8 *pCmdBuffer
|
||||
);
|
||||
|
||||
typedef u8 (*BFP_BTC_GET)(void *pBtCoexist, u8 getType, void *pOutBuf);
|
||||
|
||||
typedef u8 (*BFP_BTC_SET)(void *pBtCoexist, u8 setType, void *pInBuf);
|
||||
typedef void (*BFP_BTC_SET_BT_REG)(
|
||||
void *pBtcContext, u8 regType, u32 offset, u32 value
|
||||
);
|
||||
typedef u32 (*BFP_BTC_GET_BT_REG)(void *pBtcContext, u8 regType, u32 offset);
|
||||
typedef void (*BFP_BTC_DISP_DBG_MSG)(void *pBtCoexist, u8 dispType);
|
||||
|
||||
typedef struct _BTC_BT_INFO {
|
||||
bool bBtDisabled;
|
||||
u8 rssiAdjustForAgcTableOn;
|
||||
u8 rssiAdjustFor1AntCoexType;
|
||||
bool bPreBtCtrlAggBufSize;
|
||||
bool bBtCtrlAggBufSize;
|
||||
bool bRejectAggPkt;
|
||||
bool bIncreaseScanDevNum;
|
||||
bool bBtTxRxMask;
|
||||
u8 preAggBufSize;
|
||||
u8 aggBufSize;
|
||||
bool bBtBusy;
|
||||
bool bLimitedDig;
|
||||
u16 btHciVer;
|
||||
u16 btRealFwVer;
|
||||
u8 btFwVer;
|
||||
u32 getBtFwVerCnt;
|
||||
|
||||
bool bBtDisableLowPwr;
|
||||
|
||||
bool bBtCtrlLps;
|
||||
bool bBtLpsOn;
|
||||
bool bForceToRoam; /* for 1Ant solution */
|
||||
u8 lpsVal;
|
||||
u8 rpwmVal;
|
||||
u32 raMask;
|
||||
} BTC_BT_INFO, *PBTC_BT_INFO;
|
||||
|
||||
typedef struct _BTC_STACK_INFO {
|
||||
bool bProfileNotified;
|
||||
u16 hciVersion; /* stack hci version */
|
||||
u8 numOfLink;
|
||||
bool bBtLinkExist;
|
||||
bool bScoExist;
|
||||
bool bAclExist;
|
||||
bool bA2dpExist;
|
||||
bool bHidExist;
|
||||
u8 numOfHid;
|
||||
bool bPanExist;
|
||||
bool bUnknownAclExist;
|
||||
s8 minBtRssi;
|
||||
} BTC_STACK_INFO, *PBTC_STACK_INFO;
|
||||
|
||||
typedef struct _BTC_BT_LINK_INFO {
|
||||
bool bBtLinkExist;
|
||||
bool bScoExist;
|
||||
bool bScoOnly;
|
||||
bool bA2dpExist;
|
||||
bool bA2dpOnly;
|
||||
bool bHidExist;
|
||||
bool bHidOnly;
|
||||
bool bPanExist;
|
||||
bool bPanOnly;
|
||||
bool bSlaveRole;
|
||||
} BTC_BT_LINK_INFO, *PBTC_BT_LINK_INFO;
|
||||
|
||||
typedef struct _BTC_STATISTICS {
|
||||
u32 cntBind;
|
||||
u32 cntPowerOn;
|
||||
u32 cntInitHwConfig;
|
||||
u32 cntInitCoexDm;
|
||||
u32 cntIpsNotify;
|
||||
u32 cntLpsNotify;
|
||||
u32 cntScanNotify;
|
||||
u32 cntConnectNotify;
|
||||
u32 cntMediaStatusNotify;
|
||||
u32 cntSpecialPacketNotify;
|
||||
u32 cntBtInfoNotify;
|
||||
u32 cntRfStatusNotify;
|
||||
u32 cntPeriodical;
|
||||
u32 cntCoexDmSwitch;
|
||||
u32 cntStackOperationNotify;
|
||||
u32 cntDbgCtrl;
|
||||
} BTC_STATISTICS, *PBTC_STATISTICS;
|
||||
|
||||
typedef struct _BTC_COEXIST {
|
||||
bool bBinded; /* make sure only one adapter can bind the data context */
|
||||
void *Adapter; /* default adapter */
|
||||
BTC_BOARD_INFO boardInfo;
|
||||
BTC_BT_INFO btInfo; /* some bt info referenced by non-bt module */
|
||||
BTC_STACK_INFO stackInfo;
|
||||
BTC_BT_LINK_INFO btLinkInfo;
|
||||
BTC_CHIP_INTERFACE chipInterface;
|
||||
|
||||
bool bInitilized;
|
||||
bool bStopCoexDm;
|
||||
bool bManualControl;
|
||||
u8 *cliBuf;
|
||||
BTC_STATISTICS statistics;
|
||||
u8 pwrModeVal[10];
|
||||
|
||||
/* function pointers */
|
||||
/* io related */
|
||||
BFP_BTC_R1 fBtcRead1Byte;
|
||||
BFP_BTC_W1 fBtcWrite1Byte;
|
||||
BFP_BTC_W1_BIT_MASK fBtcWrite1ByteBitMask;
|
||||
BFP_BTC_R2 fBtcRead2Byte;
|
||||
BFP_BTC_W2 fBtcWrite2Byte;
|
||||
BFP_BTC_R4 fBtcRead4Byte;
|
||||
BFP_BTC_W4 fBtcWrite4Byte;
|
||||
BFP_BTC_LOCAL_REG_W1 fBtcWriteLocalReg1Byte;
|
||||
/* read/write bb related */
|
||||
BFP_BTC_SET_BB_REG fBtcSetBbReg;
|
||||
BFP_BTC_GET_BB_REG fBtcGetBbReg;
|
||||
|
||||
/* read/write rf related */
|
||||
BFP_BTC_SET_RF_REG fBtcSetRfReg;
|
||||
BFP_BTC_GET_RF_REG fBtcGetRfReg;
|
||||
|
||||
/* fill h2c related */
|
||||
BFP_BTC_FILL_H2C fBtcFillH2c;
|
||||
/* other */
|
||||
BFP_BTC_DISP_DBG_MSG fBtcDispDbgMsg;
|
||||
/* normal get/set related */
|
||||
BFP_BTC_GET fBtcGet;
|
||||
BFP_BTC_SET fBtcSet;
|
||||
|
||||
BFP_BTC_GET_BT_REG fBtcGetBtReg;
|
||||
BFP_BTC_SET_BT_REG fBtcSetBtReg;
|
||||
} BTC_COEXIST, *PBTC_COEXIST;
|
||||
|
||||
extern BTC_COEXIST GLBtCoexist;
|
||||
|
||||
u8 EXhalbtcoutsrc_InitlizeVariables(void *Adapter);
|
||||
void EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtcoutsrc_InitHwConfig(PBTC_COEXIST pBtCoexist, u8 bWifiOnly);
|
||||
void EXhalbtcoutsrc_InitCoexDm(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtcoutsrc_IpsNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtcoutsrc_LpsNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtcoutsrc_ScanNotify(PBTC_COEXIST pBtCoexist, u8 type);
|
||||
void EXhalbtcoutsrc_ConnectNotify(PBTC_COEXIST pBtCoexist, u8 action);
|
||||
void EXhalbtcoutsrc_MediaStatusNotify(
|
||||
PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS mediaStatus
|
||||
);
|
||||
void EXhalbtcoutsrc_SpecialPacketNotify(PBTC_COEXIST pBtCoexist, u8 pktType);
|
||||
void EXhalbtcoutsrc_BtInfoNotify(
|
||||
PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length
|
||||
);
|
||||
void EXhalbtcoutsrc_HaltNotify(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtcoutsrc_PnpNotify(PBTC_COEXIST pBtCoexist, u8 pnpState);
|
||||
void EXhalbtcoutsrc_Periodical(PBTC_COEXIST pBtCoexist);
|
||||
void EXhalbtcoutsrc_SetChipType(u8 chipType);
|
||||
void EXhalbtcoutsrc_SetAntNum(u8 type, u8 antNum);
|
||||
void EXhalbtcoutsrc_SetSingleAntPath(u8 singleAntPath);
|
||||
void EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,643 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
static bool CheckPositive(
|
||||
PDM_ODM_T pDM_Odm, const u32 Condition1, const u32 Condition2
|
||||
)
|
||||
{
|
||||
u8 _BoardType =
|
||||
((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */
|
||||
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */
|
||||
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */
|
||||
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
|
||||
((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */
|
||||
|
||||
u32 cond1 = Condition1, cond2 = Condition2;
|
||||
u32 driver1 =
|
||||
pDM_Odm->CutVersion << 24 |
|
||||
pDM_Odm->SupportPlatform << 16 |
|
||||
pDM_Odm->PackageType << 12 |
|
||||
pDM_Odm->SupportInterface << 8 |
|
||||
_BoardType;
|
||||
|
||||
u32 driver2 =
|
||||
pDM_Odm->TypeGLNA << 0 |
|
||||
pDM_Odm->TypeGPA << 8 |
|
||||
pDM_Odm->TypeALNA << 16 |
|
||||
pDM_Odm->TypeAPA << 24;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
"===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n",
|
||||
cond1,
|
||||
cond2
|
||||
)
|
||||
);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
"===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n",
|
||||
driver1,
|
||||
driver2
|
||||
)
|
||||
);
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(" (Platform, Interface) = (0x%X, 0x%X)\n",
|
||||
pDM_Odm->SupportPlatform,
|
||||
pDM_Odm->SupportInterface
|
||||
)
|
||||
);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
" (Board, Package) = (0x%X, 0x%X)\n",
|
||||
pDM_Odm->BoardType,
|
||||
pDM_Odm->PackageType
|
||||
)
|
||||
);
|
||||
|
||||
|
||||
/* Value Defined Check =============== */
|
||||
/* QFN Type [15:12] and Cut Version [27:24] need to do value check */
|
||||
|
||||
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
|
||||
return false;
|
||||
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
|
||||
return false;
|
||||
|
||||
/* Bit Defined Check ================ */
|
||||
/* We don't care [31:28] and [23:20] */
|
||||
/* */
|
||||
cond1 &= 0x000F0FFF;
|
||||
driver1 &= 0x000F0FFF;
|
||||
|
||||
if ((cond1 & driver1) == cond1) {
|
||||
u32 bitMask = 0;
|
||||
|
||||
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE */
|
||||
return true;
|
||||
|
||||
if ((cond1 & BIT0) != 0) /* GLNA */
|
||||
bitMask |= 0x000000FF;
|
||||
if ((cond1 & BIT1) != 0) /* GPA */
|
||||
bitMask |= 0x0000FF00;
|
||||
if ((cond1 & BIT2) != 0) /* ALNA */
|
||||
bitMask |= 0x00FF0000;
|
||||
if ((cond1 & BIT3) != 0) /* APA */
|
||||
bitMask |= 0xFF000000;
|
||||
|
||||
/* BoardType of each RF path is matched */
|
||||
if ((cond2 & bitMask) == (driver2 & bitMask))
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool CheckNegative(
|
||||
PDM_ODM_T pDM_Odm, const u32 Condition1, const u32 Condition2
|
||||
)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* AGC_TAB.TXT
|
||||
******************************************************************************/
|
||||
|
||||
static u32 Array_MP_8723B_AGC_TAB[] = {
|
||||
0xC78, 0xFD000001,
|
||||
0xC78, 0xFC010001,
|
||||
0xC78, 0xFB020001,
|
||||
0xC78, 0xFA030001,
|
||||
0xC78, 0xF9040001,
|
||||
0xC78, 0xF8050001,
|
||||
0xC78, 0xF7060001,
|
||||
0xC78, 0xF6070001,
|
||||
0xC78, 0xF5080001,
|
||||
0xC78, 0xF4090001,
|
||||
0xC78, 0xF30A0001,
|
||||
0xC78, 0xF20B0001,
|
||||
0xC78, 0xF10C0001,
|
||||
0xC78, 0xF00D0001,
|
||||
0xC78, 0xEF0E0001,
|
||||
0xC78, 0xEE0F0001,
|
||||
0xC78, 0xED100001,
|
||||
0xC78, 0xEC110001,
|
||||
0xC78, 0xEB120001,
|
||||
0xC78, 0xEA130001,
|
||||
0xC78, 0xE9140001,
|
||||
0xC78, 0xE8150001,
|
||||
0xC78, 0xE7160001,
|
||||
0xC78, 0xE6170001,
|
||||
0xC78, 0xE5180001,
|
||||
0xC78, 0xE4190001,
|
||||
0xC78, 0xE31A0001,
|
||||
0xC78, 0xA51B0001,
|
||||
0xC78, 0xA41C0001,
|
||||
0xC78, 0xA31D0001,
|
||||
0xC78, 0x671E0001,
|
||||
0xC78, 0x661F0001,
|
||||
0xC78, 0x65200001,
|
||||
0xC78, 0x64210001,
|
||||
0xC78, 0x63220001,
|
||||
0xC78, 0x4A230001,
|
||||
0xC78, 0x49240001,
|
||||
0xC78, 0x48250001,
|
||||
0xC78, 0x47260001,
|
||||
0xC78, 0x46270001,
|
||||
0xC78, 0x45280001,
|
||||
0xC78, 0x44290001,
|
||||
0xC78, 0x432A0001,
|
||||
0xC78, 0x422B0001,
|
||||
0xC78, 0x292C0001,
|
||||
0xC78, 0x282D0001,
|
||||
0xC78, 0x272E0001,
|
||||
0xC78, 0x262F0001,
|
||||
0xC78, 0x0A300001,
|
||||
0xC78, 0x09310001,
|
||||
0xC78, 0x08320001,
|
||||
0xC78, 0x07330001,
|
||||
0xC78, 0x06340001,
|
||||
0xC78, 0x05350001,
|
||||
0xC78, 0x04360001,
|
||||
0xC78, 0x03370001,
|
||||
0xC78, 0x02380001,
|
||||
0xC78, 0x01390001,
|
||||
0xC78, 0x013A0001,
|
||||
0xC78, 0x013B0001,
|
||||
0xC78, 0x013C0001,
|
||||
0xC78, 0x013D0001,
|
||||
0xC78, 0x013E0001,
|
||||
0xC78, 0x013F0001,
|
||||
0xC78, 0xFC400001,
|
||||
0xC78, 0xFB410001,
|
||||
0xC78, 0xFA420001,
|
||||
0xC78, 0xF9430001,
|
||||
0xC78, 0xF8440001,
|
||||
0xC78, 0xF7450001,
|
||||
0xC78, 0xF6460001,
|
||||
0xC78, 0xF5470001,
|
||||
0xC78, 0xF4480001,
|
||||
0xC78, 0xF3490001,
|
||||
0xC78, 0xF24A0001,
|
||||
0xC78, 0xF14B0001,
|
||||
0xC78, 0xF04C0001,
|
||||
0xC78, 0xEF4D0001,
|
||||
0xC78, 0xEE4E0001,
|
||||
0xC78, 0xED4F0001,
|
||||
0xC78, 0xEC500001,
|
||||
0xC78, 0xEB510001,
|
||||
0xC78, 0xEA520001,
|
||||
0xC78, 0xE9530001,
|
||||
0xC78, 0xE8540001,
|
||||
0xC78, 0xE7550001,
|
||||
0xC78, 0xE6560001,
|
||||
0xC78, 0xE5570001,
|
||||
0xC78, 0xE4580001,
|
||||
0xC78, 0xE3590001,
|
||||
0xC78, 0xA65A0001,
|
||||
0xC78, 0xA55B0001,
|
||||
0xC78, 0xA45C0001,
|
||||
0xC78, 0xA35D0001,
|
||||
0xC78, 0x675E0001,
|
||||
0xC78, 0x665F0001,
|
||||
0xC78, 0x65600001,
|
||||
0xC78, 0x64610001,
|
||||
0xC78, 0x63620001,
|
||||
0xC78, 0x62630001,
|
||||
0xC78, 0x61640001,
|
||||
0xC78, 0x48650001,
|
||||
0xC78, 0x47660001,
|
||||
0xC78, 0x46670001,
|
||||
0xC78, 0x45680001,
|
||||
0xC78, 0x44690001,
|
||||
0xC78, 0x436A0001,
|
||||
0xC78, 0x426B0001,
|
||||
0xC78, 0x286C0001,
|
||||
0xC78, 0x276D0001,
|
||||
0xC78, 0x266E0001,
|
||||
0xC78, 0x256F0001,
|
||||
0xC78, 0x24700001,
|
||||
0xC78, 0x09710001,
|
||||
0xC78, 0x08720001,
|
||||
0xC78, 0x07730001,
|
||||
0xC78, 0x06740001,
|
||||
0xC78, 0x05750001,
|
||||
0xC78, 0x04760001,
|
||||
0xC78, 0x03770001,
|
||||
0xC78, 0x02780001,
|
||||
0xC78, 0x01790001,
|
||||
0xC78, 0x017A0001,
|
||||
0xC78, 0x017B0001,
|
||||
0xC78, 0x017C0001,
|
||||
0xC78, 0x017D0001,
|
||||
0xC78, 0x017E0001,
|
||||
0xC78, 0x017F0001,
|
||||
0xC50, 0x69553422,
|
||||
0xC50, 0x69553420,
|
||||
0x824, 0x00390204,
|
||||
|
||||
};
|
||||
|
||||
void ODM_ReadAndConfig_MP_8723B_AGC_TAB(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
u32 i = 0;
|
||||
u32 ArrayLen = sizeof(Array_MP_8723B_AGC_TAB)/sizeof(u32);
|
||||
u32 *Array = Array_MP_8723B_AGC_TAB;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_LOUD,
|
||||
("===> ODM_ReadAndConfig_MP_8723B_AGC_TAB\n")
|
||||
);
|
||||
|
||||
for (i = 0; i < ArrayLen; i += 2) {
|
||||
u32 v1 = Array[i];
|
||||
u32 v2 = Array[i+1];
|
||||
|
||||
/* This (offset, data) pair doesn't care the condition. */
|
||||
if (v1 < 0x40000000) {
|
||||
odm_ConfigBB_AGC_8723B(pDM_Odm, v1, bMaskDWord, v2);
|
||||
continue;
|
||||
} else {
|
||||
/* This line is the beginning of branch. */
|
||||
bool bMatched = true;
|
||||
u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
|
||||
if (cCond == COND_ELSE) { /* ELSE, ENDIF */
|
||||
bMatched = true;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
} else if (!CheckPositive(pDM_Odm, v1, v2)) {
|
||||
bMatched = false;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
} else {
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
if (!CheckNegative(pDM_Odm, v1, v2))
|
||||
bMatched = false;
|
||||
else
|
||||
bMatched = true;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
}
|
||||
|
||||
if (bMatched == false) {
|
||||
/* Condition isn't matched.
|
||||
* Discard the following (offset, data) pairs.
|
||||
*/
|
||||
while (v1 < 0x40000000 && i < ArrayLen-2)
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
|
||||
i -= 2; /* prevent from for-loop += 2 */
|
||||
} else {
|
||||
/* Configure matched pairs and skip to end of if-else. */
|
||||
while (v1 < 0x40000000 && i < ArrayLen-2) {
|
||||
odm_ConfigBB_AGC_8723B(pDM_Odm, v1, bMaskDWord, v2);
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
}
|
||||
|
||||
/* Keeps reading until ENDIF. */
|
||||
cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
while (cCond != COND_ENDIF && i < ArrayLen-2) {
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
static u32 Array_MP_8723B_PHY_REG[] = {
|
||||
0x800, 0x80040000,
|
||||
0x804, 0x00000003,
|
||||
0x808, 0x0000FC00,
|
||||
0x80C, 0x0000000A,
|
||||
0x810, 0x10001331,
|
||||
0x814, 0x020C3D10,
|
||||
0x818, 0x02200385,
|
||||
0x81C, 0x00000000,
|
||||
0x820, 0x01000100,
|
||||
0x824, 0x00190204,
|
||||
0x828, 0x00000000,
|
||||
0x82C, 0x00000000,
|
||||
0x830, 0x00000000,
|
||||
0x834, 0x00000000,
|
||||
0x838, 0x00000000,
|
||||
0x83C, 0x00000000,
|
||||
0x840, 0x00010000,
|
||||
0x844, 0x00000000,
|
||||
0x848, 0x00000000,
|
||||
0x84C, 0x00000000,
|
||||
0x850, 0x00000000,
|
||||
0x854, 0x00000000,
|
||||
0x858, 0x569A11A9,
|
||||
0x85C, 0x01000014,
|
||||
0x860, 0x66F60110,
|
||||
0x864, 0x061F0649,
|
||||
0x868, 0x00000000,
|
||||
0x86C, 0x27272700,
|
||||
0x870, 0x07000760,
|
||||
0x874, 0x25004000,
|
||||
0x878, 0x00000808,
|
||||
0x87C, 0x00000000,
|
||||
0x880, 0xB0000C1C,
|
||||
0x884, 0x00000001,
|
||||
0x888, 0x00000000,
|
||||
0x88C, 0xCCC000C0,
|
||||
0x890, 0x00000800,
|
||||
0x894, 0xFFFFFFFE,
|
||||
0x898, 0x40302010,
|
||||
0x89C, 0x00706050,
|
||||
0x900, 0x00000000,
|
||||
0x904, 0x00000023,
|
||||
0x908, 0x00000000,
|
||||
0x90C, 0x81121111,
|
||||
0x910, 0x00000002,
|
||||
0x914, 0x00000201,
|
||||
0xA00, 0x00D047C8,
|
||||
0xA04, 0x80FF800C,
|
||||
0xA08, 0x8C838300,
|
||||
0xA0C, 0x2E7F120F,
|
||||
0xA10, 0x9500BB78,
|
||||
0xA14, 0x1114D028,
|
||||
0xA18, 0x00881117,
|
||||
0xA1C, 0x89140F00,
|
||||
0xA20, 0x1A1B0000,
|
||||
0xA24, 0x090E1317,
|
||||
0xA28, 0x00000204,
|
||||
0xA2C, 0x00D30000,
|
||||
0xA70, 0x101FBF00,
|
||||
0xA74, 0x00000007,
|
||||
0xA78, 0x00000900,
|
||||
0xA7C, 0x225B0606,
|
||||
0xA80, 0x21806490,
|
||||
0xB2C, 0x00000000,
|
||||
0xC00, 0x48071D40,
|
||||
0xC04, 0x03A05611,
|
||||
0xC08, 0x000000E4,
|
||||
0xC0C, 0x6C6C6C6C,
|
||||
0xC10, 0x08800000,
|
||||
0xC14, 0x40000100,
|
||||
0xC18, 0x08800000,
|
||||
0xC1C, 0x40000100,
|
||||
0xC20, 0x00000000,
|
||||
0xC24, 0x00000000,
|
||||
0xC28, 0x00000000,
|
||||
0xC2C, 0x00000000,
|
||||
0xC30, 0x69E9AC44,
|
||||
0xC34, 0x469652AF,
|
||||
0xC38, 0x49795994,
|
||||
0xC3C, 0x0A97971C,
|
||||
0xC40, 0x1F7C403F,
|
||||
0xC44, 0x000100B7,
|
||||
0xC48, 0xEC020107,
|
||||
0xC4C, 0x007F037F,
|
||||
0xC50, 0x69553420,
|
||||
0xC54, 0x43BC0094,
|
||||
0xC58, 0x00013149,
|
||||
0xC5C, 0x00250492,
|
||||
0xC60, 0x00000000,
|
||||
0xC64, 0x7112848B,
|
||||
0xC68, 0x47C00BFF,
|
||||
0xC6C, 0x00000036,
|
||||
0xC70, 0x2C7F000D,
|
||||
0xC74, 0x020610DB,
|
||||
0xC78, 0x0000001F,
|
||||
0xC7C, 0x00B91612,
|
||||
0xC80, 0x390000E4,
|
||||
0xC84, 0x20F60000,
|
||||
0xC88, 0x40000100,
|
||||
0xC8C, 0x20200000,
|
||||
0xC90, 0x00020E1A,
|
||||
0xC94, 0x00000000,
|
||||
0xC98, 0x00020E1A,
|
||||
0xC9C, 0x00007F7F,
|
||||
0xCA0, 0x00000000,
|
||||
0xCA4, 0x000300A0,
|
||||
0xCA8, 0x00000000,
|
||||
0xCAC, 0x00000000,
|
||||
0xCB0, 0x00000000,
|
||||
0xCB4, 0x00000000,
|
||||
0xCB8, 0x00000000,
|
||||
0xCBC, 0x28000000,
|
||||
0xCC0, 0x00000000,
|
||||
0xCC4, 0x00000000,
|
||||
0xCC8, 0x00000000,
|
||||
0xCCC, 0x00000000,
|
||||
0xCD0, 0x00000000,
|
||||
0xCD4, 0x00000000,
|
||||
0xCD8, 0x64B22427,
|
||||
0xCDC, 0x00766932,
|
||||
0xCE0, 0x00222222,
|
||||
0xCE4, 0x00000000,
|
||||
0xCE8, 0x37644302,
|
||||
0xCEC, 0x2F97D40C,
|
||||
0xD00, 0x00000740,
|
||||
0xD04, 0x40020401,
|
||||
0xD08, 0x0000907F,
|
||||
0xD0C, 0x20010201,
|
||||
0xD10, 0xA0633333,
|
||||
0xD14, 0x3333BC53,
|
||||
0xD18, 0x7A8F5B6F,
|
||||
0xD2C, 0xCC979975,
|
||||
0xD30, 0x00000000,
|
||||
0xD34, 0x80608000,
|
||||
0xD38, 0x00000000,
|
||||
0xD3C, 0x00127353,
|
||||
0xD40, 0x00000000,
|
||||
0xD44, 0x00000000,
|
||||
0xD48, 0x00000000,
|
||||
0xD4C, 0x00000000,
|
||||
0xD50, 0x6437140A,
|
||||
0xD54, 0x00000000,
|
||||
0xD58, 0x00000282,
|
||||
0xD5C, 0x30032064,
|
||||
0xD60, 0x4653DE68,
|
||||
0xD64, 0x04518A3C,
|
||||
0xD68, 0x00002101,
|
||||
0xD6C, 0x2A201C16,
|
||||
0xD70, 0x1812362E,
|
||||
0xD74, 0x322C2220,
|
||||
0xD78, 0x000E3C24,
|
||||
0xE00, 0x2D2D2D2D,
|
||||
0xE04, 0x2D2D2D2D,
|
||||
0xE08, 0x0390272D,
|
||||
0xE10, 0x2D2D2D2D,
|
||||
0xE14, 0x2D2D2D2D,
|
||||
0xE18, 0x2D2D2D2D,
|
||||
0xE1C, 0x2D2D2D2D,
|
||||
0xE28, 0x00000000,
|
||||
0xE30, 0x1000DC1F,
|
||||
0xE34, 0x10008C1F,
|
||||
0xE38, 0x02140102,
|
||||
0xE3C, 0x681604C2,
|
||||
0xE40, 0x01007C00,
|
||||
0xE44, 0x01004800,
|
||||
0xE48, 0xFB000000,
|
||||
0xE4C, 0x000028D1,
|
||||
0xE50, 0x1000DC1F,
|
||||
0xE54, 0x10008C1F,
|
||||
0xE58, 0x02140102,
|
||||
0xE5C, 0x28160D05,
|
||||
0xE60, 0x00000008,
|
||||
0xE68, 0x001B2556,
|
||||
0xE6C, 0x00C00096,
|
||||
0xE70, 0x00C00096,
|
||||
0xE74, 0x01000056,
|
||||
0xE78, 0x01000014,
|
||||
0xE7C, 0x01000056,
|
||||
0xE80, 0x01000014,
|
||||
0xE84, 0x00C00096,
|
||||
0xE88, 0x01000056,
|
||||
0xE8C, 0x00C00096,
|
||||
0xED0, 0x00C00096,
|
||||
0xED4, 0x00C00096,
|
||||
0xED8, 0x00C00096,
|
||||
0xEDC, 0x000000D6,
|
||||
0xEE0, 0x000000D6,
|
||||
0xEEC, 0x01C00016,
|
||||
0xF14, 0x00000003,
|
||||
0xF4C, 0x00000000,
|
||||
0xF00, 0x00000300,
|
||||
0x820, 0x01000100,
|
||||
0x800, 0x83040000,
|
||||
|
||||
};
|
||||
|
||||
void ODM_ReadAndConfig_MP_8723B_PHY_REG(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
u32 i = 0;
|
||||
u32 ArrayLen = sizeof(Array_MP_8723B_PHY_REG)/sizeof(u32);
|
||||
u32 *Array = Array_MP_8723B_PHY_REG;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_LOUD,
|
||||
("===> ODM_ReadAndConfig_MP_8723B_PHY_REG\n")
|
||||
);
|
||||
|
||||
for (i = 0; i < ArrayLen; i += 2) {
|
||||
u32 v1 = Array[i];
|
||||
u32 v2 = Array[i+1];
|
||||
|
||||
/* This (offset, data) pair doesn't care the condition. */
|
||||
if (v1 < 0x40000000) {
|
||||
odm_ConfigBB_PHY_8723B(pDM_Odm, v1, bMaskDWord, v2);
|
||||
continue;
|
||||
} else {
|
||||
/* This line is the beginning of branch. */
|
||||
bool bMatched = true;
|
||||
u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
|
||||
if (cCond == COND_ELSE) { /* ELSE, ENDIF */
|
||||
bMatched = true;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
} else if (!CheckPositive(pDM_Odm, v1, v2)) {
|
||||
bMatched = false;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
} else {
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
if (!CheckNegative(pDM_Odm, v1, v2))
|
||||
bMatched = false;
|
||||
else
|
||||
bMatched = true;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
}
|
||||
|
||||
if (bMatched == false) {
|
||||
/* Condition isn't matched.
|
||||
* Discard the following (offset, data) pairs.
|
||||
*/
|
||||
while (v1 < 0x40000000 && i < ArrayLen-2)
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
|
||||
i -= 2; /* prevent from for-loop += 2 */
|
||||
} else { /* Configure matched pairs and skip to end of if-else. */
|
||||
while (v1 < 0x40000000 && i < ArrayLen-2) {
|
||||
odm_ConfigBB_PHY_8723B(pDM_Odm, v1, bMaskDWord, v2);
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
}
|
||||
|
||||
/* Keeps reading until ENDIF. */
|
||||
cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
while (cCond != COND_ENDIF && i < ArrayLen-2) {
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG_PG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
static u32 Array_MP_8723B_PHY_REG_PG[] = {
|
||||
0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003800,
|
||||
0, 0, 0, 0x0000086c, 0xffffff00, 0x32343600,
|
||||
0, 0, 0, 0x00000e00, 0xffffffff, 0x40424444,
|
||||
0, 0, 0, 0x00000e04, 0xffffffff, 0x28323638,
|
||||
0, 0, 0, 0x00000e10, 0xffffffff, 0x38404244,
|
||||
0, 0, 0, 0x00000e14, 0xffffffff, 0x26303436
|
||||
};
|
||||
|
||||
void ODM_ReadAndConfig_MP_8723B_PHY_REG_PG(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
u32 i = 0;
|
||||
u32 ArrayLen = sizeof(Array_MP_8723B_PHY_REG_PG)/sizeof(u32);
|
||||
u32 *Array = Array_MP_8723B_PHY_REG_PG;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_LOUD,
|
||||
("===> ODM_ReadAndConfig_MP_8723B_PHY_REG_PG\n")
|
||||
);
|
||||
|
||||
pDM_Odm->PhyRegPgVersion = 1;
|
||||
pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE;
|
||||
|
||||
for (i = 0; i < ArrayLen; i += 6) {
|
||||
u32 v1 = Array[i];
|
||||
u32 v2 = Array[i+1];
|
||||
u32 v3 = Array[i+2];
|
||||
u32 v4 = Array[i+3];
|
||||
u32 v5 = Array[i+4];
|
||||
u32 v6 = Array[i+5];
|
||||
|
||||
odm_ConfigBB_PHY_REG_PG_8723B(pDM_Odm, v1, v2, v3, v4, v5, v6);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_MP_BB_HW_IMG_8723B_H
|
||||
#define __INC_MP_BB_HW_IMG_8723B_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* AGC_TAB.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723B_AGC_TAB(/* TC: Test Chip, MP: MP Chip */
|
||||
PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723B_PHY_REG(/* TC: Test Chip, MP: MP Chip */
|
||||
PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG_PG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723B_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip */
|
||||
PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u32 ODM_GetVersion_MP_8723B_PHY_REG_PG(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,302 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
static bool CheckPositive(
|
||||
PDM_ODM_T pDM_Odm, const u32 Condition1, const u32 Condition2
|
||||
)
|
||||
{
|
||||
u8 _BoardType =
|
||||
((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */
|
||||
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */
|
||||
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */
|
||||
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
|
||||
((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */
|
||||
|
||||
u32 cond1 = Condition1, cond2 = Condition2;
|
||||
u32 driver1 =
|
||||
pDM_Odm->CutVersion << 24 |
|
||||
pDM_Odm->SupportPlatform << 16 |
|
||||
pDM_Odm->PackageType << 12 |
|
||||
pDM_Odm->SupportInterface << 8 |
|
||||
_BoardType;
|
||||
|
||||
u32 driver2 =
|
||||
pDM_Odm->TypeGLNA << 0 |
|
||||
pDM_Odm->TypeGPA << 8 |
|
||||
pDM_Odm->TypeALNA << 16 |
|
||||
pDM_Odm->TypeAPA << 24;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
"===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n",
|
||||
cond1,
|
||||
cond2
|
||||
)
|
||||
);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
"===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n",
|
||||
driver1,
|
||||
driver2
|
||||
)
|
||||
);
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
" (Platform, Interface) = (0x%X, 0x%X)\n",
|
||||
pDM_Odm->SupportPlatform,
|
||||
pDM_Odm->SupportInterface
|
||||
)
|
||||
);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
" (Board, Package) = (0x%X, 0x%X)\n",
|
||||
pDM_Odm->BoardType,
|
||||
pDM_Odm->PackageType
|
||||
)
|
||||
);
|
||||
|
||||
|
||||
/* Value Defined Check =============== */
|
||||
/* QFN Type [15:12] and Cut Version [27:24] need to do value check */
|
||||
|
||||
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
|
||||
return false;
|
||||
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
|
||||
return false;
|
||||
|
||||
/* Bit Defined Check ================ */
|
||||
/* We don't care [31:28] and [23:20] */
|
||||
/* */
|
||||
cond1 &= 0x000F0FFF;
|
||||
driver1 &= 0x000F0FFF;
|
||||
|
||||
if ((cond1 & driver1) == cond1) {
|
||||
u32 bitMask = 0;
|
||||
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE */
|
||||
return true;
|
||||
|
||||
if ((cond1 & BIT0) != 0) /* GLNA */
|
||||
bitMask |= 0x000000FF;
|
||||
if ((cond1 & BIT1) != 0) /* GPA */
|
||||
bitMask |= 0x0000FF00;
|
||||
if ((cond1 & BIT2) != 0) /* ALNA */
|
||||
bitMask |= 0x00FF0000;
|
||||
if ((cond1 & BIT3) != 0) /* APA */
|
||||
bitMask |= 0xFF000000;
|
||||
|
||||
if ((cond2 & bitMask) == (driver2 & bitMask)) /* BoardType of each RF path is matched */
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool CheckNegative(
|
||||
PDM_ODM_T pDM_Odm, const u32 Condition1, const u32 Condition2
|
||||
)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* MAC_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
static u32 Array_MP_8723B_MAC_REG[] = {
|
||||
0x02F, 0x00000030,
|
||||
0x035, 0x00000000,
|
||||
0x039, 0x00000008,
|
||||
0x04E, 0x000000E0,
|
||||
0x064, 0x00000000,
|
||||
0x067, 0x00000020,
|
||||
0x428, 0x0000000A,
|
||||
0x429, 0x00000010,
|
||||
0x430, 0x00000000,
|
||||
0x431, 0x00000000,
|
||||
0x432, 0x00000000,
|
||||
0x433, 0x00000001,
|
||||
0x434, 0x00000004,
|
||||
0x435, 0x00000005,
|
||||
0x436, 0x00000007,
|
||||
0x437, 0x00000008,
|
||||
0x43C, 0x00000004,
|
||||
0x43D, 0x00000005,
|
||||
0x43E, 0x00000007,
|
||||
0x43F, 0x00000008,
|
||||
0x440, 0x0000005D,
|
||||
0x441, 0x00000001,
|
||||
0x442, 0x00000000,
|
||||
0x444, 0x00000010,
|
||||
0x445, 0x00000000,
|
||||
0x446, 0x00000000,
|
||||
0x447, 0x00000000,
|
||||
0x448, 0x00000000,
|
||||
0x449, 0x000000F0,
|
||||
0x44A, 0x0000000F,
|
||||
0x44B, 0x0000003E,
|
||||
0x44C, 0x00000010,
|
||||
0x44D, 0x00000000,
|
||||
0x44E, 0x00000000,
|
||||
0x44F, 0x00000000,
|
||||
0x450, 0x00000000,
|
||||
0x451, 0x000000F0,
|
||||
0x452, 0x0000000F,
|
||||
0x453, 0x00000000,
|
||||
0x456, 0x0000005E,
|
||||
0x460, 0x00000066,
|
||||
0x461, 0x00000066,
|
||||
0x4C8, 0x000000FF,
|
||||
0x4C9, 0x00000008,
|
||||
0x4CC, 0x000000FF,
|
||||
0x4CD, 0x000000FF,
|
||||
0x4CE, 0x00000001,
|
||||
0x500, 0x00000026,
|
||||
0x501, 0x000000A2,
|
||||
0x502, 0x0000002F,
|
||||
0x503, 0x00000000,
|
||||
0x504, 0x00000028,
|
||||
0x505, 0x000000A3,
|
||||
0x506, 0x0000005E,
|
||||
0x507, 0x00000000,
|
||||
0x508, 0x0000002B,
|
||||
0x509, 0x000000A4,
|
||||
0x50A, 0x0000005E,
|
||||
0x50B, 0x00000000,
|
||||
0x50C, 0x0000004F,
|
||||
0x50D, 0x000000A4,
|
||||
0x50E, 0x00000000,
|
||||
0x50F, 0x00000000,
|
||||
0x512, 0x0000001C,
|
||||
0x514, 0x0000000A,
|
||||
0x516, 0x0000000A,
|
||||
0x525, 0x0000004F,
|
||||
0x550, 0x00000010,
|
||||
0x551, 0x00000010,
|
||||
0x559, 0x00000002,
|
||||
0x55C, 0x00000050,
|
||||
0x55D, 0x000000FF,
|
||||
0x605, 0x00000030,
|
||||
0x608, 0x0000000E,
|
||||
0x609, 0x0000002A,
|
||||
0x620, 0x000000FF,
|
||||
0x621, 0x000000FF,
|
||||
0x622, 0x000000FF,
|
||||
0x623, 0x000000FF,
|
||||
0x624, 0x000000FF,
|
||||
0x625, 0x000000FF,
|
||||
0x626, 0x000000FF,
|
||||
0x627, 0x000000FF,
|
||||
0x638, 0x00000050,
|
||||
0x63C, 0x0000000A,
|
||||
0x63D, 0x0000000A,
|
||||
0x63E, 0x0000000E,
|
||||
0x63F, 0x0000000E,
|
||||
0x640, 0x00000040,
|
||||
0x642, 0x00000040,
|
||||
0x643, 0x00000000,
|
||||
0x652, 0x000000C8,
|
||||
0x66E, 0x00000005,
|
||||
0x700, 0x00000021,
|
||||
0x701, 0x00000043,
|
||||
0x702, 0x00000065,
|
||||
0x703, 0x00000087,
|
||||
0x708, 0x00000021,
|
||||
0x709, 0x00000043,
|
||||
0x70A, 0x00000065,
|
||||
0x70B, 0x00000087,
|
||||
0x765, 0x00000018,
|
||||
0x76E, 0x00000004,
|
||||
|
||||
};
|
||||
|
||||
void ODM_ReadAndConfig_MP_8723B_MAC_REG(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
u32 i = 0;
|
||||
u32 ArrayLen = sizeof(Array_MP_8723B_MAC_REG)/sizeof(u32);
|
||||
u32 *Array = Array_MP_8723B_MAC_REG;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_LOUD,
|
||||
("===> ODM_ReadAndConfig_MP_8723B_MAC_REG\n")
|
||||
);
|
||||
|
||||
for (i = 0; i < ArrayLen; i += 2) {
|
||||
u32 v1 = Array[i];
|
||||
u32 v2 = Array[i+1];
|
||||
|
||||
/* This (offset, data) pair doesn't care the condition. */
|
||||
if (v1 < 0x40000000) {
|
||||
odm_ConfigMAC_8723B(pDM_Odm, v1, (u8)v2);
|
||||
continue;
|
||||
} else {
|
||||
/* This line is the beginning of branch. */
|
||||
bool bMatched = true;
|
||||
u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
|
||||
if (cCond == COND_ELSE) { /* ELSE, ENDIF */
|
||||
bMatched = true;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
} else if (!CheckPositive(pDM_Odm, v1, v2)) {
|
||||
bMatched = false;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
} else {
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
if (!CheckNegative(pDM_Odm, v1, v2))
|
||||
bMatched = false;
|
||||
else
|
||||
bMatched = true;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
}
|
||||
|
||||
if (bMatched == false) {
|
||||
/* Condition isn't matched. Discard the following (offset, data) pairs. */
|
||||
while (v1 < 0x40000000 && i < ArrayLen-2)
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
|
||||
i -= 2; /* prevent from for-loop += 2 */
|
||||
} else { /* Configure matched pairs and skip to end of if-else. */
|
||||
while (v1 < 0x40000000 && i < ArrayLen-2) {
|
||||
odm_ConfigMAC_8723B(pDM_Odm, v1, (u8)v2);
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
}
|
||||
|
||||
/* Keeps reading until ENDIF. */
|
||||
cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
while (cCond != COND_ENDIF && i < ArrayLen-2) {
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_MP_MAC_HW_IMG_8723B_H
|
||||
#define __INC_MP_MAC_HW_IMG_8723B_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* MAC_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723B_MAC_REG(/* TC: Test Chip, MP: MP Chip */
|
||||
PDM_ODM_T pDM_Odm
|
||||
);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,799 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
static bool CheckPositive(
|
||||
PDM_ODM_T pDM_Odm, const u32 Condition1, const u32 Condition2
|
||||
)
|
||||
{
|
||||
u8 _BoardType =
|
||||
((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */
|
||||
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */
|
||||
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */
|
||||
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
|
||||
((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */
|
||||
|
||||
u32 cond1 = Condition1, cond2 = Condition2;
|
||||
u32 driver1 =
|
||||
pDM_Odm->CutVersion << 24 |
|
||||
pDM_Odm->SupportPlatform << 16 |
|
||||
pDM_Odm->PackageType << 12 |
|
||||
pDM_Odm->SupportInterface << 8 |
|
||||
_BoardType;
|
||||
|
||||
u32 driver2 =
|
||||
pDM_Odm->TypeGLNA << 0 |
|
||||
pDM_Odm->TypeGPA << 8 |
|
||||
pDM_Odm->TypeALNA << 16 |
|
||||
pDM_Odm->TypeAPA << 24;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
"===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n",
|
||||
cond1,
|
||||
cond2
|
||||
)
|
||||
);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
"===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n",
|
||||
driver1,
|
||||
driver2
|
||||
)
|
||||
);
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
" (Platform, Interface) = (0x%X, 0x%X)\n",
|
||||
pDM_Odm->SupportPlatform,
|
||||
pDM_Odm->SupportInterface
|
||||
)
|
||||
);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
" (Board, Package) = (0x%X, 0x%X)\n",
|
||||
pDM_Odm->BoardType,
|
||||
pDM_Odm->PackageType
|
||||
)
|
||||
);
|
||||
|
||||
/* Value Defined Check =============== */
|
||||
/* QFN Type [15:12] and Cut Version [27:24] need to do value check */
|
||||
|
||||
if (
|
||||
((cond1 & 0x0000F000) != 0) &&
|
||||
((cond1 & 0x0000F000) != (driver1 & 0x0000F000))
|
||||
)
|
||||
return false;
|
||||
|
||||
if (
|
||||
((cond1 & 0x0F000000) != 0) &&
|
||||
((cond1 & 0x0F000000) != (driver1 & 0x0F000000))
|
||||
)
|
||||
return false;
|
||||
|
||||
/* Bit Defined Check ================ */
|
||||
/* We don't care [31:28] and [23:20] */
|
||||
cond1 &= 0x000F0FFF;
|
||||
driver1 &= 0x000F0FFF;
|
||||
|
||||
if ((cond1 & driver1) == cond1) {
|
||||
u32 bitMask = 0;
|
||||
|
||||
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE */
|
||||
return true;
|
||||
|
||||
if ((cond1 & BIT0) != 0) /* GLNA */
|
||||
bitMask |= 0x000000FF;
|
||||
if ((cond1 & BIT1) != 0) /* GPA */
|
||||
bitMask |= 0x0000FF00;
|
||||
if ((cond1 & BIT2) != 0) /* ALNA */
|
||||
bitMask |= 0x00FF0000;
|
||||
if ((cond1 & BIT3) != 0) /* APA */
|
||||
bitMask |= 0xFF000000;
|
||||
|
||||
/* BoardType of each RF path is matched */
|
||||
if ((cond2 & bitMask) == (driver2 & bitMask))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool CheckNegative(
|
||||
PDM_ODM_T pDM_Odm, const u32 Condition1, const u32 Condition2
|
||||
)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* RadioA.TXT
|
||||
******************************************************************************/
|
||||
|
||||
static u32 Array_MP_8723B_RadioA[] = {
|
||||
0x000, 0x00010000,
|
||||
0x0B0, 0x000DFFE0,
|
||||
0x0FE, 0x00000000,
|
||||
0x0FE, 0x00000000,
|
||||
0x0FE, 0x00000000,
|
||||
0x0B1, 0x00000018,
|
||||
0x0FE, 0x00000000,
|
||||
0x0FE, 0x00000000,
|
||||
0x0FE, 0x00000000,
|
||||
0x0B2, 0x00084C00,
|
||||
0x0B5, 0x0000D2CC,
|
||||
0x0B6, 0x000925AA,
|
||||
0x0B7, 0x00000010,
|
||||
0x0B8, 0x0000907F,
|
||||
0x05C, 0x00000002,
|
||||
0x07C, 0x00000002,
|
||||
0x07E, 0x00000005,
|
||||
0x08B, 0x0006FC00,
|
||||
0x0B0, 0x000FF9F0,
|
||||
0x01C, 0x000739D2,
|
||||
0x01E, 0x00000000,
|
||||
0x0DF, 0x00000780,
|
||||
0x050, 0x00067435,
|
||||
0x80002000, 0x00000000, 0x40000000, 0x00000000,
|
||||
0x051, 0x0006B10E,
|
||||
0x90003000, 0x00000000, 0x40000000, 0x00000000,
|
||||
0x051, 0x0006B10E,
|
||||
0x90004000, 0x00000000, 0x40000000, 0x00000000,
|
||||
0x051, 0x0006B10E,
|
||||
0xA0000000, 0x00000000,
|
||||
0x051, 0x0006B04E,
|
||||
0xB0000000, 0x00000000,
|
||||
0x052, 0x000007D2,
|
||||
0x053, 0x00000000,
|
||||
0x054, 0x00050400,
|
||||
0x055, 0x0004026E,
|
||||
0x0DD, 0x0000004C,
|
||||
0x070, 0x00067435,
|
||||
0x80002000, 0x00000000, 0x40000000, 0x00000000,
|
||||
0x071, 0x0006B10E,
|
||||
0x90003000, 0x00000000, 0x40000000, 0x00000000,
|
||||
0x071, 0x0006B10E,
|
||||
0x90004000, 0x00000000, 0x40000000, 0x00000000,
|
||||
0x071, 0x0006B10E,
|
||||
0xA0000000, 0x00000000,
|
||||
0x071, 0x0006B04E,
|
||||
0xB0000000, 0x00000000,
|
||||
0x072, 0x000007D2,
|
||||
0x073, 0x00000000,
|
||||
0x074, 0x00050400,
|
||||
0x075, 0x0004026E,
|
||||
0x0EF, 0x00000100,
|
||||
0x034, 0x0000ADD7,
|
||||
0x035, 0x00005C00,
|
||||
0x034, 0x00009DD4,
|
||||
0x035, 0x00005000,
|
||||
0x034, 0x00008DD1,
|
||||
0x035, 0x00004400,
|
||||
0x034, 0x00007DCE,
|
||||
0x035, 0x00003800,
|
||||
0x034, 0x00006CD1,
|
||||
0x035, 0x00004400,
|
||||
0x034, 0x00005CCE,
|
||||
0x035, 0x00003800,
|
||||
0x034, 0x000048CE,
|
||||
0x035, 0x00004400,
|
||||
0x034, 0x000034CE,
|
||||
0x035, 0x00003800,
|
||||
0x034, 0x00002451,
|
||||
0x035, 0x00004400,
|
||||
0x034, 0x0000144E,
|
||||
0x035, 0x00003800,
|
||||
0x034, 0x00000051,
|
||||
0x035, 0x00004400,
|
||||
0x0EF, 0x00000000,
|
||||
0x0EF, 0x00000100,
|
||||
0x0ED, 0x00000010,
|
||||
0x044, 0x0000ADD7,
|
||||
0x044, 0x00009DD4,
|
||||
0x044, 0x00008DD1,
|
||||
0x044, 0x00007DCE,
|
||||
0x044, 0x00006CC1,
|
||||
0x044, 0x00005CCE,
|
||||
0x044, 0x000044D1,
|
||||
0x044, 0x000034CE,
|
||||
0x044, 0x00002451,
|
||||
0x044, 0x0000144E,
|
||||
0x044, 0x00000051,
|
||||
0x0EF, 0x00000000,
|
||||
0x0ED, 0x00000000,
|
||||
0x07F, 0x00020080,
|
||||
0x0EF, 0x00002000,
|
||||
0x03B, 0x000380EF,
|
||||
0x03B, 0x000302FE,
|
||||
0x03B, 0x00028CE6,
|
||||
0x03B, 0x000200BC,
|
||||
0x03B, 0x000188A5,
|
||||
0x03B, 0x00010FBC,
|
||||
0x03B, 0x00008F71,
|
||||
0x03B, 0x00000900,
|
||||
0x0EF, 0x00000000,
|
||||
0x0ED, 0x00000001,
|
||||
0x040, 0x000380EF,
|
||||
0x040, 0x000302FE,
|
||||
0x040, 0x00028CE6,
|
||||
0x040, 0x000200BC,
|
||||
0x040, 0x000188A5,
|
||||
0x040, 0x00010FBC,
|
||||
0x040, 0x00008F71,
|
||||
0x040, 0x00000900,
|
||||
0x0ED, 0x00000000,
|
||||
0x082, 0x00080000,
|
||||
0x083, 0x00008000,
|
||||
0x084, 0x00048D80,
|
||||
0x085, 0x00068000,
|
||||
0x0A2, 0x00080000,
|
||||
0x0A3, 0x00008000,
|
||||
0x0A4, 0x00048D80,
|
||||
0x0A5, 0x00068000,
|
||||
0x0ED, 0x00000002,
|
||||
0x0EF, 0x00000002,
|
||||
0x056, 0x00000032,
|
||||
0x076, 0x00000032,
|
||||
0x001, 0x00000780,
|
||||
|
||||
};
|
||||
|
||||
void ODM_ReadAndConfig_MP_8723B_RadioA(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
u32 i = 0;
|
||||
u32 ArrayLen = sizeof(Array_MP_8723B_RadioA)/sizeof(u32);
|
||||
u32 *Array = Array_MP_8723B_RadioA;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_LOUD,
|
||||
("===> ODM_ReadAndConfig_MP_8723B_RadioA\n")
|
||||
);
|
||||
|
||||
for (i = 0; i < ArrayLen; i += 2) {
|
||||
u32 v1 = Array[i];
|
||||
u32 v2 = Array[i+1];
|
||||
|
||||
/* This (offset, data) pair doesn't care the condition. */
|
||||
if (v1 < 0x40000000) {
|
||||
odm_ConfigRF_RadioA_8723B(pDM_Odm, v1, v2);
|
||||
continue;
|
||||
} else {
|
||||
/* This line is the beginning of branch. */
|
||||
bool bMatched = true;
|
||||
u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
|
||||
if (cCond == COND_ELSE) { /* ELSE, ENDIF */
|
||||
bMatched = true;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
} else if (!CheckPositive(pDM_Odm, v1, v2)) {
|
||||
bMatched = false;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
} else {
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
if (!CheckNegative(pDM_Odm, v1, v2))
|
||||
bMatched = false;
|
||||
else
|
||||
bMatched = true;
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
}
|
||||
|
||||
if (bMatched == false) {
|
||||
/* Condition isn't matched.
|
||||
* Discard the following (offset, data) pairs.
|
||||
*/
|
||||
while (v1 < 0x40000000 && i < ArrayLen-2)
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
|
||||
i -= 2; /* prevent from for-loop += 2 */
|
||||
} else {
|
||||
/* Configure matched pairs and skip to end of if-else. */
|
||||
while (v1 < 0x40000000 && i < ArrayLen-2) {
|
||||
odm_ConfigRF_RadioA_8723B(pDM_Odm, v1, v2);
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
}
|
||||
|
||||
/* Keeps reading until ENDIF. */
|
||||
cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
while (cCond != COND_ENDIF && i < ArrayLen-2) {
|
||||
READ_NEXT_PAIR(v1, v2, i);
|
||||
cCond = (u8)((v1 & (BIT29|BIT28)) >> 28);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_SDIO.TXT
|
||||
******************************************************************************/
|
||||
|
||||
static u8 gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = {
|
||||
{
|
||||
0, 1, 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9,
|
||||
9, 10, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14
|
||||
},
|
||||
{
|
||||
0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10,
|
||||
10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14
|
||||
},
|
||||
{
|
||||
0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10,
|
||||
10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14
|
||||
},
|
||||
};
|
||||
static u8 gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = {
|
||||
{
|
||||
0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
|
||||
12, 13, 14, 15, 15, 16, 16, 17, 17, 18, 19, 20, 20, 20
|
||||
},
|
||||
{
|
||||
0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
|
||||
12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 19, 20, 20, 20
|
||||
},
|
||||
{
|
||||
0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
|
||||
12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21
|
||||
},
|
||||
};
|
||||
static u8 gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = {
|
||||
{
|
||||
0, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 8, 8, 9, 9, 10,
|
||||
10, 11, 11, 12, 12, 13, 13, 14, 14, 14, 14, 14, 14, 14
|
||||
},
|
||||
{
|
||||
0, 1, 2, 3, 3, 4, 5, 6, 6, 6, 7, 7, 8, 8, 9, 10,
|
||||
11, 11, 12, 13, 13, 14, 15, 16, 16, 16, 16, 16, 16, 16
|
||||
},
|
||||
{
|
||||
0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11,
|
||||
11, 12, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16
|
||||
},
|
||||
};
|
||||
static u8 gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8723B[][DELTA_SWINGIDX_SIZE] = {
|
||||
{
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
},
|
||||
{
|
||||
0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
|
||||
12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21
|
||||
},
|
||||
{
|
||||
0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
|
||||
12, 13, 14, 15, 15, 16, 17, 18, 18, 19, 20, 21, 21, 21
|
||||
},
|
||||
};
|
||||
static u8 gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8723B[] = {
|
||||
0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6,
|
||||
7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15
|
||||
};
|
||||
static u8 gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8723B[] = {
|
||||
0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8,
|
||||
9, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15
|
||||
};
|
||||
static u8 gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8723B[] = {
|
||||
0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 6, 6,
|
||||
7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 12, 13, 14, 15
|
||||
};
|
||||
static u8 gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8723B[] = {
|
||||
0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8,
|
||||
9, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13, 14, 15, 15
|
||||
};
|
||||
static u8 gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8723B[] = {
|
||||
0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8,
|
||||
8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15
|
||||
};
|
||||
static u8 gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8723B[] = {
|
||||
0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7,
|
||||
8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15
|
||||
};
|
||||
static u8 gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8723B[] = {
|
||||
0, 0, 1, 2, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 7, 8,
|
||||
8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15
|
||||
};
|
||||
static u8 gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8723B[] = {
|
||||
0, 0, 1, 2, 2, 2, 3, 3, 3, 4, 5, 5, 6, 6, 7, 7,
|
||||
8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13, 14, 15
|
||||
};
|
||||
|
||||
void ODM_ReadAndConfig_MP_8723B_TxPowerTrack_SDIO(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_LOUD,
|
||||
("===> ODM_ReadAndConfig_MP_MP_8723B\n")
|
||||
);
|
||||
|
||||
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P,
|
||||
gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE
|
||||
);
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N,
|
||||
gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE
|
||||
);
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P,
|
||||
gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE
|
||||
);
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N,
|
||||
gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE
|
||||
);
|
||||
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P,
|
||||
gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE
|
||||
);
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N,
|
||||
gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE
|
||||
);
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P,
|
||||
gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE
|
||||
);
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N,
|
||||
gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE
|
||||
);
|
||||
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P,
|
||||
gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE*3
|
||||
);
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N,
|
||||
gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE*3
|
||||
);
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P,
|
||||
gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE*3
|
||||
);
|
||||
memcpy(
|
||||
pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N,
|
||||
gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8723B,
|
||||
DELTA_SWINGIDX_SIZE*3
|
||||
);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* TXPWR_LMT.TXT
|
||||
******************************************************************************/
|
||||
|
||||
static u8 *Array_MP_8723B_TXPWR_LMT[] = {
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "01", "32",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "01", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "02", "32",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "02", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "02", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "03", "32",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "03", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "03", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "04", "32",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "04", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "04", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "05", "32",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "05", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "05", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "06", "32",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "06", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "06", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "07", "32",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "07", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "07", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "08", "32",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "08", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "08", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "09", "32",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "09", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "09", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "10", "32",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "10", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "10", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "11", "32",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "11", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "11", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "12", "63",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "12", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "12", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "13", "63",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "13", "32",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "13", "32",
|
||||
"FCC", "2.4G", "20M", "CCK", "1T", "14", "63",
|
||||
"ETSI", "2.4G", "20M", "CCK", "1T", "14", "63",
|
||||
"MKK", "2.4G", "20M", "CCK", "1T", "14", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "01", "28",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "01", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "02", "28",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "02", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "03", "32",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "03", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "04", "32",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "04", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "05", "32",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "05", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "06", "32",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "06", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "07", "32",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "07", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "08", "32",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "08", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "09", "32",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "09", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "10", "28",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "10", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "11", "28",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "11", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "12", "63",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "12", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "13", "63",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "13", "32",
|
||||
"FCC", "2.4G", "20M", "OFDM", "1T", "14", "63",
|
||||
"ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63",
|
||||
"MKK", "2.4G", "20M", "OFDM", "1T", "14", "63",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "01", "26",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "01", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "01", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "02", "26",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "02", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "02", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "03", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "03", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "03", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "04", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "04", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "04", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "05", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "05", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "05", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "06", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "06", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "06", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "07", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "07", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "07", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "08", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "08", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "08", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "09", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "09", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "09", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "10", "26",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "10", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "10", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "11", "26",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "11", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "11", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "12", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "12", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "12", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "13", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "13", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "13", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "1T", "14", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "1T", "14", "63",
|
||||
"MKK", "2.4G", "20M", "HT", "1T", "14", "63",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "01", "30",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "01", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "01", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "02", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "02", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "02", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "03", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "03", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "03", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "04", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "04", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "04", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "05", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "05", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "05", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "06", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "06", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "06", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "07", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "07", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "07", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "08", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "08", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "08", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "09", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "09", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "09", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "10", "32",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "10", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "10", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "11", "30",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "11", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "11", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "12", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "12", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "12", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "13", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "13", "32",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "13", "32",
|
||||
"FCC", "2.4G", "20M", "HT", "2T", "14", "63",
|
||||
"ETSI", "2.4G", "20M", "HT", "2T", "14", "63",
|
||||
"MKK", "2.4G", "20M", "HT", "2T", "14", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "01", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "01", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "01", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "02", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "02", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "02", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "03", "26",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "03", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "03", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "04", "26",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "04", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "04", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "05", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "05", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "05", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "06", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "06", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "06", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "07", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "07", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "07", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "08", "26",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "08", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "08", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "09", "26",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "09", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "09", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "10", "26",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "10", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "10", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "11", "26",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "11", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "11", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "12", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "12", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "12", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "13", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "13", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "13", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "1T", "14", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "1T", "14", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "1T", "14", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "01", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "01", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "01", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "02", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "02", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "02", "63",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "03", "30",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "03", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "03", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "04", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "04", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "04", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "05", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "05", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "05", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "06", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "06", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "06", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "07", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "07", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "07", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "08", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "08", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "08", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "09", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "09", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "09", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "10", "32",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "10", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "10", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "11", "30",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "11", "30",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "11", "30",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "12", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "12", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "12", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "13", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "13", "32",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "13", "32",
|
||||
"FCC", "2.4G", "40M", "HT", "2T", "14", "63",
|
||||
"ETSI", "2.4G", "40M", "HT", "2T", "14", "63",
|
||||
"MKK", "2.4G", "40M", "HT", "2T", "14", "63"
|
||||
};
|
||||
|
||||
void ODM_ReadAndConfig_MP_8723B_TXPWR_LMT(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
u32 i = 0;
|
||||
u32 ArrayLen = sizeof(Array_MP_8723B_TXPWR_LMT)/sizeof(u8 *);
|
||||
u8 **Array = Array_MP_8723B_TXPWR_LMT;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_LOUD,
|
||||
("===> ODM_ReadAndConfig_MP_8723B_TXPWR_LMT\n")
|
||||
);
|
||||
|
||||
for (i = 0; i < ArrayLen; i += 7) {
|
||||
u8 *regulation = Array[i];
|
||||
u8 *band = Array[i+1];
|
||||
u8 *bandwidth = Array[i+2];
|
||||
u8 *rate = Array[i+3];
|
||||
u8 *rfPath = Array[i+4];
|
||||
u8 *chnl = Array[i+5];
|
||||
u8 *val = Array[i+6];
|
||||
|
||||
odm_ConfigBB_TXPWR_LMT_8723B(
|
||||
pDM_Odm,
|
||||
regulation,
|
||||
band,
|
||||
bandwidth,
|
||||
rate,
|
||||
rfPath,
|
||||
chnl,
|
||||
val
|
||||
);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_MP_RF_HW_IMG_8723B_H
|
||||
#define __INC_MP_RF_HW_IMG_8723B_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* RadioA.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723B_RadioA(/* TC: Test Chip, MP: MP Chip */
|
||||
PDM_ODM_T pDM_Odm
|
||||
);
|
||||
|
||||
/******************************************************************************
|
||||
* TxPowerTrack_SDIO.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723B_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip */
|
||||
PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u32 ODM_GetVersion_MP_8723B_TxPowerTrack_SDIO(void);
|
||||
|
||||
/******************************************************************************
|
||||
* TXPWR_LMT.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
ODM_ReadAndConfig_MP_8723B_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip */
|
||||
PDM_ODM_T pDM_Odm
|
||||
);
|
||||
u32 ODM_GetVersion_MP_8723B_TXPWR_LMT(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,662 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* include "Mp_Precomp.h" */
|
||||
#include "odm_precomp.h"
|
||||
|
||||
|
||||
#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \
|
||||
do {\
|
||||
for (_offset = 0; _offset < _size; _offset++) {\
|
||||
if (_deltaThermal < thermalThreshold[_direction][_offset]) {\
|
||||
if (_offset != 0)\
|
||||
_offset--;\
|
||||
break;\
|
||||
} \
|
||||
} \
|
||||
if (_offset >= _size)\
|
||||
_offset = _size-1;\
|
||||
} while (0)
|
||||
|
||||
|
||||
void ConfigureTxpowerTrack(PDM_ODM_T pDM_Odm, PTXPWRTRACK_CFG pConfig)
|
||||
{
|
||||
ConfigureTxpowerTrack_8723B(pConfig);
|
||||
}
|
||||
|
||||
/* */
|
||||
/* <20121113, Kordan> This function should be called when TxAGC changed. */
|
||||
/* Otherwise the previous compensation is gone, because we record the */
|
||||
/* delta of temperature between two TxPowerTracking watch dogs. */
|
||||
/* */
|
||||
/* NOTE: If Tx BB swing or Tx scaling is varified during run-time, still */
|
||||
/* need to call this function. */
|
||||
/* */
|
||||
void ODM_ClearTxPowerTrackingState(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
|
||||
u8 p = 0;
|
||||
|
||||
pDM_Odm->BbSwingIdxCckBase = pDM_Odm->DefaultCckIndex;
|
||||
pDM_Odm->BbSwingIdxCck = pDM_Odm->DefaultCckIndex;
|
||||
pDM_Odm->RFCalibrateInfo.CCK_index = 0;
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) {
|
||||
pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->DefaultOfdmIndex;
|
||||
pDM_Odm->BbSwingIdxOfdm[p] = pDM_Odm->DefaultOfdmIndex;
|
||||
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->DefaultOfdmIndex;
|
||||
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = 0;
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p] = 0;
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
|
||||
|
||||
/* Initial Mix mode power tracking */
|
||||
pDM_Odm->Absolute_OFDMSwingIdx[p] = 0;
|
||||
pDM_Odm->Remnant_OFDMSwingIdx[p] = 0;
|
||||
}
|
||||
|
||||
/* Initial at Modify Tx Scaling Mode */
|
||||
pDM_Odm->Modify_TxAGC_Flag_PathA = false;
|
||||
/* Initial at Modify Tx Scaling Mode */
|
||||
pDM_Odm->Modify_TxAGC_Flag_PathB = false;
|
||||
pDM_Odm->Remnant_CCKSwingIdx = 0;
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter;
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = pHalData->EEPROMThermalMeter;
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = pHalData->EEPROMThermalMeter;
|
||||
}
|
||||
|
||||
void ODM_TXPowerTrackingCallback_ThermalMeter(struct adapter *Adapter)
|
||||
{
|
||||
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
|
||||
|
||||
u8 ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0;
|
||||
u8 ThermalValue_AVG_count = 0;
|
||||
u32 ThermalValue_AVG = 0;
|
||||
|
||||
u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */
|
||||
u8 Indexforchannel = 0; /* GetRightChnlPlaceforIQK(pHalData->CurrentChannel) */
|
||||
|
||||
TXPWRTRACK_CFG c;
|
||||
|
||||
|
||||
/* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */
|
||||
u8 *deltaSwingTableIdx_TUP_A;
|
||||
u8 *deltaSwingTableIdx_TDOWN_A;
|
||||
u8 *deltaSwingTableIdx_TUP_B;
|
||||
u8 *deltaSwingTableIdx_TDOWN_B;
|
||||
|
||||
/* 4 2. Initilization (7 steps in total) */
|
||||
|
||||
ConfigureTxpowerTrack(pDM_Odm, &c);
|
||||
|
||||
(*c.GetDeltaSwingTable)(
|
||||
pDM_Odm,
|
||||
(u8 **)&deltaSwingTableIdx_TUP_A,
|
||||
(u8 **)&deltaSwingTableIdx_TDOWN_A,
|
||||
(u8 **)&deltaSwingTableIdx_TUP_B,
|
||||
(u8 **)&deltaSwingTableIdx_TDOWN_B
|
||||
);
|
||||
|
||||
/* cosa add for debug */
|
||||
pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++;
|
||||
pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = true;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"===>ODM_TXPowerTrackingCallback_ThermalMeter,\npDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase[A]: %d, pDM_Odm->DefaultOfdmIndex: %d\n",
|
||||
pDM_Odm->BbSwingIdxCckBase,
|
||||
pDM_Odm->BbSwingIdxOfdmBase[ODM_RF_PATH_A],
|
||||
pDM_Odm->DefaultOfdmIndex
|
||||
)
|
||||
);
|
||||
|
||||
ThermalValue = (u8)PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */
|
||||
if (
|
||||
!pDM_Odm->RFCalibrateInfo.TxPowerTrackControl ||
|
||||
pHalData->EEPROMThermalMeter == 0 ||
|
||||
pHalData->EEPROMThermalMeter == 0xFF
|
||||
)
|
||||
return;
|
||||
|
||||
/* 4 3. Initialize ThermalValues of RFCalibrateInfo */
|
||||
|
||||
if (pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex)
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
("reload ofdm index for band switch\n")
|
||||
);
|
||||
|
||||
/* 4 4. Calculate average thermal meter */
|
||||
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue;
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++;
|
||||
if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) /* Average times = c.AverageThermalNum */
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0;
|
||||
|
||||
for (i = 0; i < c.AverageThermalNum; i++) {
|
||||
if (pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) {
|
||||
ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i];
|
||||
ThermalValue_AVG_count++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Calculate Average ThermalValue after average enough times */
|
||||
if (ThermalValue_AVG_count) {
|
||||
ThermalValue = (u8)(ThermalValue_AVG / ThermalValue_AVG_count);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n",
|
||||
ThermalValue,
|
||||
pHalData->EEPROMThermalMeter
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
/* 4 5. Calculate delta, delta_LCK, delta_IQK. */
|
||||
/* delta" here is used to determine whether thermal value changes or not. */
|
||||
delta =
|
||||
(ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue) ?
|
||||
(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue) :
|
||||
(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue);
|
||||
delta_LCK =
|
||||
(ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK) ?
|
||||
(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK) :
|
||||
(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue);
|
||||
delta_IQK =
|
||||
(ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK) ?
|
||||
(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK) :
|
||||
(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue);
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n",
|
||||
delta,
|
||||
delta_LCK,
|
||||
delta_IQK
|
||||
)
|
||||
);
|
||||
|
||||
/* 4 6. If necessary, do LCK. */
|
||||
/* Delta temperature is equal to or larger than 20 centigrade. */
|
||||
if (delta_LCK >= c.Threshold_IQK) {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"delta_LCK(%d) >= Threshold_IQK(%d)\n",
|
||||
delta_LCK,
|
||||
c.Threshold_IQK
|
||||
)
|
||||
);
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue;
|
||||
if (c.PHY_LCCalibrate)
|
||||
(*c.PHY_LCCalibrate)(pDM_Odm);
|
||||
}
|
||||
|
||||
/* 3 7. If necessary, move the index of swing table to adjust Tx power. */
|
||||
if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) {
|
||||
/* delta" here is used to record the absolute value of differrence. */
|
||||
delta =
|
||||
ThermalValue > pHalData->EEPROMThermalMeter ?
|
||||
(ThermalValue - pHalData->EEPROMThermalMeter) :
|
||||
(pHalData->EEPROMThermalMeter - ThermalValue);
|
||||
|
||||
if (delta >= TXPWR_TRACK_TABLE_SIZE)
|
||||
delta = TXPWR_TRACK_TABLE_SIZE - 1;
|
||||
|
||||
/* 4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset */
|
||||
if (ThermalValue > pHalData->EEPROMThermalMeter) {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"deltaSwingTableIdx_TUP_A[%d] = %d\n",
|
||||
delta,
|
||||
deltaSwingTableIdx_TUP_A[delta]
|
||||
)
|
||||
);
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_A] =
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A];
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A] =
|
||||
deltaSwingTableIdx_TUP_A[delta];
|
||||
|
||||
/* Record delta swing for mix mode power tracking */
|
||||
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] =
|
||||
deltaSwingTableIdx_TUP_A[delta];
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n",
|
||||
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A]
|
||||
)
|
||||
);
|
||||
|
||||
if (c.RfPathCount > 1) {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"deltaSwingTableIdx_TUP_B[%d] = %d\n",
|
||||
delta,
|
||||
deltaSwingTableIdx_TUP_B[delta]
|
||||
)
|
||||
);
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] =
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B];
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] =
|
||||
deltaSwingTableIdx_TUP_B[delta];
|
||||
|
||||
/* Record delta swing for mix mode power tracking */
|
||||
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] =
|
||||
deltaSwingTableIdx_TUP_B[delta];
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n",
|
||||
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B]
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
} else {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"deltaSwingTableIdx_TDOWN_A[%d] = %d\n",
|
||||
delta,
|
||||
deltaSwingTableIdx_TDOWN_A[delta]
|
||||
)
|
||||
);
|
||||
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_A] =
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A];
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_A] =
|
||||
-1 * deltaSwingTableIdx_TDOWN_A[delta];
|
||||
|
||||
/* Record delta swing for mix mode power tracking */
|
||||
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] =
|
||||
-1 * deltaSwingTableIdx_TDOWN_A[delta];
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n",
|
||||
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A]
|
||||
)
|
||||
);
|
||||
|
||||
if (c.RfPathCount > 1) {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"deltaSwingTableIdx_TDOWN_B[%d] = %d\n",
|
||||
delta,
|
||||
deltaSwingTableIdx_TDOWN_B[delta]
|
||||
)
|
||||
);
|
||||
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[ODM_RF_PATH_B] =
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B];
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[ODM_RF_PATH_B] =
|
||||
-1 * deltaSwingTableIdx_TDOWN_B[delta];
|
||||
|
||||
/* Record delta swing for mix mode power tracking */
|
||||
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] =
|
||||
-1 * deltaSwingTableIdx_TDOWN_B[delta];
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n",
|
||||
pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B]
|
||||
)
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"\n\n ================================ [Path-%c] Calculating PowerIndexOffset ================================\n",
|
||||
(p == ODM_RF_PATH_A ? 'A' : 'B')
|
||||
)
|
||||
);
|
||||
|
||||
if (
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] ==
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]
|
||||
) /* If Thermal value changes but lookup table value still the same */
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
|
||||
else
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]; /* Power Index Diff between 2 times Power Tracking */
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"[Path-%c] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n",
|
||||
(
|
||||
p == ODM_RF_PATH_A ? 'A' : 'B'),
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p],
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p],
|
||||
pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]
|
||||
)
|
||||
);
|
||||
|
||||
pDM_Odm->RFCalibrateInfo.OFDM_index[p] =
|
||||
pDM_Odm->BbSwingIdxOfdmBase[p] +
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p];
|
||||
|
||||
pDM_Odm->RFCalibrateInfo.CCK_index =
|
||||
pDM_Odm->BbSwingIdxCckBase +
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p];
|
||||
|
||||
pDM_Odm->BbSwingIdxCck =
|
||||
pDM_Odm->RFCalibrateInfo.CCK_index;
|
||||
|
||||
pDM_Odm->BbSwingIdxOfdm[p] =
|
||||
pDM_Odm->RFCalibrateInfo.OFDM_index[p];
|
||||
|
||||
/* *************Print BB Swing Base and Index Offset************* */
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n",
|
||||
pDM_Odm->BbSwingIdxCck,
|
||||
pDM_Odm->BbSwingIdxCckBase,
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]
|
||||
)
|
||||
);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"The 'OFDM' final index(%d) = BaseIndex[%c](%d) + PowerIndexOffset(%d)\n",
|
||||
pDM_Odm->BbSwingIdxOfdm[p],
|
||||
(p == ODM_RF_PATH_A ? 'A' : 'B'),
|
||||
pDM_Odm->BbSwingIdxOfdmBase[p],
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]
|
||||
)
|
||||
);
|
||||
|
||||
/* 4 7.1 Handle boundary conditions of index. */
|
||||
if (pDM_Odm->RFCalibrateInfo.OFDM_index[p] > c.SwingTableSize_OFDM-1)
|
||||
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = c.SwingTableSize_OFDM-1;
|
||||
else if (pDM_Odm->RFCalibrateInfo.OFDM_index[p] < OFDM_min_index)
|
||||
pDM_Odm->RFCalibrateInfo.OFDM_index[p] = OFDM_min_index;
|
||||
}
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
("\n\n ========================================================================================================\n")
|
||||
);
|
||||
if (pDM_Odm->RFCalibrateInfo.CCK_index > c.SwingTableSize_CCK-1)
|
||||
pDM_Odm->RFCalibrateInfo.CCK_index = c.SwingTableSize_CCK-1;
|
||||
/* else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0) */
|
||||
/* pDM_Odm->RFCalibrateInfo.CCK_index = 0; */
|
||||
} else {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d\n",
|
||||
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl,
|
||||
ThermalValue,
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue
|
||||
)
|
||||
);
|
||||
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
|
||||
}
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
|
||||
pDM_Odm->RFCalibrateInfo.CCK_index,
|
||||
pDM_Odm->BbSwingIdxCckBase
|
||||
)
|
||||
);
|
||||
|
||||
/* Print Swing base & current */
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%c]: %d\n",
|
||||
pDM_Odm->RFCalibrateInfo.OFDM_index[p],
|
||||
(p == ODM_RF_PATH_A ? 'A' : 'B'),
|
||||
pDM_Odm->BbSwingIdxOfdmBase[p]
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
if (
|
||||
(pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A] != 0 ||
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B] != 0) &&
|
||||
pDM_Odm->RFCalibrateInfo.TxPowerTrackControl
|
||||
) {
|
||||
/* 4 7.2 Configure the Swing Table to adjust Tx Power. */
|
||||
|
||||
pDM_Odm->RFCalibrateInfo.bTxPowerChanged = true; /* Always true after Tx Power is adjusted by power tracking. */
|
||||
/* */
|
||||
/* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */
|
||||
/* to increase TX power. Otherwise, EVM will be bad. */
|
||||
/* */
|
||||
/* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */
|
||||
if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue) {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"Temperature Increasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A],
|
||||
delta,
|
||||
ThermalValue,
|
||||
pHalData->EEPROMThermalMeter,
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue
|
||||
)
|
||||
);
|
||||
|
||||
if (c.RfPathCount > 1)
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"Temperature Increasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B],
|
||||
delta,
|
||||
ThermalValue,
|
||||
pHalData->EEPROMThermalMeter,
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue
|
||||
)
|
||||
);
|
||||
|
||||
} else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue) { /* Low temperature */
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"Temperature Decreasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A],
|
||||
delta,
|
||||
ThermalValue,
|
||||
pHalData->EEPROMThermalMeter,
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue
|
||||
)
|
||||
);
|
||||
|
||||
if (c.RfPathCount > 1)
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"Temperature Decreasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
|
||||
pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B],
|
||||
delta,
|
||||
ThermalValue,
|
||||
pHalData->EEPROMThermalMeter,
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue
|
||||
)
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
if (ThermalValue > pHalData->EEPROMThermalMeter) {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"Temperature(%d) higher than PG value(%d)\n",
|
||||
ThermalValue,
|
||||
pHalData->EEPROMThermalMeter
|
||||
)
|
||||
);
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
("**********Enter POWER Tracking MIX_MODE**********\n")
|
||||
);
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0);
|
||||
} else {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"Temperature(%d) lower than PG value(%d)\n",
|
||||
ThermalValue,
|
||||
pHalData->EEPROMThermalMeter
|
||||
)
|
||||
);
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
("**********Enter POWER Tracking MIX_MODE**********\n")
|
||||
);
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
(*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel);
|
||||
}
|
||||
|
||||
/* Record last time Power Tracking result as base. */
|
||||
pDM_Odm->BbSwingIdxCckBase = pDM_Odm->BbSwingIdxCck;
|
||||
for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++)
|
||||
pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->BbSwingIdxOfdm[p];
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
|
||||
(
|
||||
"pDM_Odm->RFCalibrateInfo.ThermalValue = %d ThermalValue = %d\n",
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue,
|
||||
ThermalValue
|
||||
)
|
||||
);
|
||||
|
||||
/* Record last Power Tracking Thermal Value */
|
||||
pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_TX_PWR_TRACK,
|
||||
ODM_DBG_LOUD,
|
||||
("<===ODM_TXPowerTrackingCallback_ThermalMeter\n")
|
||||
);
|
||||
|
||||
pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* 3 ============================================================ */
|
||||
/* 3 IQ Calibration */
|
||||
/* 3 ============================================================ */
|
||||
|
||||
u8 ODM_GetRightChnlPlaceforIQK(u8 chnl)
|
||||
{
|
||||
u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
|
||||
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
|
||||
36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
|
||||
60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
|
||||
114, 116, 118, 120, 122, 124, 126, 128, 130, 132,
|
||||
134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
|
||||
161, 163, 165
|
||||
};
|
||||
u8 place = chnl;
|
||||
|
||||
|
||||
if (chnl > 14) {
|
||||
for (place = 14; place < sizeof(channel_all); place++) {
|
||||
if (channel_all[place] == chnl)
|
||||
return place-13;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_H__
|
||||
#define __HAL_PHY_RF_H__
|
||||
|
||||
typedef enum _SPUR_CAL_METHOD {
|
||||
PLL_RESET,
|
||||
AFE_PHASE_SEL
|
||||
} SPUR_CAL_METHOD;
|
||||
|
||||
typedef enum _PWRTRACK_CONTROL_METHOD {
|
||||
BBSWING,
|
||||
TXAGC,
|
||||
MIX_MODE
|
||||
} PWRTRACK_METHOD;
|
||||
|
||||
typedef void (*FuncSetPwr)(PDM_ODM_T, PWRTRACK_METHOD, u8, u8);
|
||||
typedef void (*FuncIQK)(PDM_ODM_T, u8, u8, u8);
|
||||
typedef void (*FuncLCK)(PDM_ODM_T);
|
||||
typedef void (*FuncSwing)(PDM_ODM_T, u8 **, u8 **, u8 **, u8 **);
|
||||
|
||||
typedef struct _TXPWRTRACK_CFG {
|
||||
u8 SwingTableSize_CCK;
|
||||
u8 SwingTableSize_OFDM;
|
||||
u8 Threshold_IQK;
|
||||
u8 AverageThermalNum;
|
||||
u8 RfPathCount;
|
||||
u32 ThermalRegAddr;
|
||||
FuncSetPwr ODM_TxPwrTrackSetPwr;
|
||||
FuncIQK DoIQK;
|
||||
FuncLCK PHY_LCCalibrate;
|
||||
FuncSwing GetDeltaSwingTable;
|
||||
} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
|
||||
|
||||
void ConfigureTxpowerTrack(PDM_ODM_T pDM_Odm, PTXPWRTRACK_CFG pConfig);
|
||||
|
||||
|
||||
void ODM_ClearTxPowerTrackingState(PDM_ODM_T pDM_Odm);
|
||||
|
||||
void ODM_TXPowerTrackingCallback_ThermalMeter(struct adapter *Adapter);
|
||||
|
||||
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
|
||||
|
||||
u8 ODM_GetRightChnlPlaceforIQK(u8 chnl);
|
||||
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,83 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_8723B_H__
|
||||
#define __HAL_PHY_RF_8723B_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define IQK_DELAY_TIME_8723B 20 /* ms */
|
||||
#define IQK_DEFERRED_TIME_8723B 4
|
||||
#define index_mapping_NUM_8723B 15
|
||||
#define AVG_THERMAL_NUM_8723B 4
|
||||
#define RF_T_METER_8723B 0x42 /* */
|
||||
|
||||
|
||||
void ConfigureTxpowerTrack_8723B(PTXPWRTRACK_CFG pConfig);
|
||||
|
||||
void DoIQK_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u8 DeltaThermalIndex,
|
||||
u8 ThermalValue,
|
||||
u8 Threshold
|
||||
);
|
||||
|
||||
void ODM_TxPwrTrackSetPwr_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
PWRTRACK_METHOD Method,
|
||||
u8 RFPath,
|
||||
u8 ChannelMappedIndex
|
||||
);
|
||||
|
||||
/* 1 7. IQK */
|
||||
void PHY_IQCalibrate_8723B(
|
||||
struct adapter *Adapter,
|
||||
bool bReCovery,
|
||||
bool bRestore,
|
||||
bool Is2ant,
|
||||
u8 RF_Path
|
||||
);
|
||||
|
||||
void ODM_SetIQCbyRFpath(PDM_ODM_T pDM_Odm, u32 RFpath);
|
||||
|
||||
/* */
|
||||
/* LC calibrate */
|
||||
/* */
|
||||
void PHY_LCCalibrate_8723B(PDM_ODM_T pDM_Odm);
|
||||
|
||||
/* */
|
||||
/* AP calibrate */
|
||||
/* */
|
||||
void PHY_DigitalPredistortion_8723B(struct adapter *padapter);
|
||||
|
||||
|
||||
void _PHY_SaveADDARegisters_8723B(
|
||||
struct adapter *padapter,
|
||||
u32 *ADDAReg,
|
||||
u32 *ADDABackup,
|
||||
u32 RegisterNum
|
||||
);
|
||||
|
||||
void _PHY_PathADDAOn_8723B(
|
||||
struct adapter *padapter,
|
||||
u32 *ADDAReg,
|
||||
bool isPathAOn,
|
||||
bool is2T
|
||||
);
|
||||
|
||||
void _PHY_MACSettingCalibration_8723B(
|
||||
struct adapter *padapter, u32 *MACReg, u32 *MACBackup
|
||||
);
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*++
|
||||
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
|
||||
|
||||
Module Name:
|
||||
HalPwrSeqCmd.c
|
||||
|
||||
Abstract:
|
||||
Implement HW Power sequence configuration CMD handling routine for Realtek devices.
|
||||
|
||||
Major Change History:
|
||||
When Who What
|
||||
---------- --------------- -------------------------------
|
||||
2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
|
||||
2011-07-07 Roger Create.
|
||||
|
||||
--*/
|
||||
#include <drv_types.h>
|
||||
#include <rtw_debug.h>
|
||||
#include <HalPwrSeqCmd.h>
|
||||
|
||||
|
||||
/* */
|
||||
/* Description: */
|
||||
/* This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. */
|
||||
/* */
|
||||
/* Assumption: */
|
||||
/* We should follow specific format which was released from HW SD. */
|
||||
/* */
|
||||
/* 2011.07.07, added by Roger. */
|
||||
/* */
|
||||
u8 HalPwrSeqCmdParsing(
|
||||
struct adapter *padapter,
|
||||
u8 CutVersion,
|
||||
u8 FabVersion,
|
||||
u8 InterfaceType,
|
||||
WLAN_PWR_CFG PwrSeqCmd[]
|
||||
)
|
||||
{
|
||||
WLAN_PWR_CFG PwrCfgCmd = {0};
|
||||
u8 bPollingBit = false;
|
||||
u32 AryIdx = 0;
|
||||
u8 value = 0;
|
||||
u32 offset = 0;
|
||||
u32 pollingCount = 0; /* polling autoload done. */
|
||||
u32 maxPollingCnt = 5000;
|
||||
|
||||
do {
|
||||
PwrCfgCmd = PwrSeqCmd[AryIdx];
|
||||
|
||||
RT_TRACE(
|
||||
_module_hal_init_c_,
|
||||
_drv_info_,
|
||||
(
|
||||
"HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
|
||||
GET_PWR_CFG_OFFSET(PwrCfgCmd),
|
||||
GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
|
||||
GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
|
||||
GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
|
||||
GET_PWR_CFG_BASE(PwrCfgCmd),
|
||||
GET_PWR_CFG_CMD(PwrCfgCmd),
|
||||
GET_PWR_CFG_MASK(PwrCfgCmd),
|
||||
GET_PWR_CFG_VALUE(PwrCfgCmd)
|
||||
)
|
||||
);
|
||||
|
||||
/* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
|
||||
if (
|
||||
(GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
|
||||
(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
|
||||
(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)
|
||||
) {
|
||||
switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
|
||||
case PWR_CMD_READ:
|
||||
RT_TRACE(
|
||||
_module_hal_init_c_,
|
||||
_drv_info_,
|
||||
("HalPwrSeqCmdParsing: PWR_CMD_READ\n")
|
||||
);
|
||||
break;
|
||||
|
||||
case PWR_CMD_WRITE:
|
||||
RT_TRACE(
|
||||
_module_hal_init_c_,
|
||||
_drv_info_,
|
||||
("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n")
|
||||
);
|
||||
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
|
||||
|
||||
/* */
|
||||
/* <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface */
|
||||
/* 2011.07.07. */
|
||||
/* */
|
||||
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
|
||||
/* Read Back SDIO Local value */
|
||||
value = SdioLocalCmd52Read1Byte(padapter, offset);
|
||||
|
||||
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
|
||||
value |= (
|
||||
GET_PWR_CFG_VALUE(PwrCfgCmd) &
|
||||
GET_PWR_CFG_MASK(PwrCfgCmd)
|
||||
);
|
||||
|
||||
/* Write Back SDIO Local value */
|
||||
SdioLocalCmd52Write1Byte(padapter, offset, value);
|
||||
} else {
|
||||
/* Read the value from system register */
|
||||
value = rtw_read8(padapter, offset);
|
||||
|
||||
value &= (~(GET_PWR_CFG_MASK(PwrCfgCmd)));
|
||||
value |= (
|
||||
GET_PWR_CFG_VALUE(PwrCfgCmd)
|
||||
&GET_PWR_CFG_MASK(PwrCfgCmd)
|
||||
);
|
||||
|
||||
/* Write the value back to sytem register */
|
||||
rtw_write8(padapter, offset, value);
|
||||
}
|
||||
break;
|
||||
|
||||
case PWR_CMD_POLLING:
|
||||
RT_TRACE(
|
||||
_module_hal_init_c_,
|
||||
_drv_info_,
|
||||
("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n")
|
||||
);
|
||||
|
||||
bPollingBit = false;
|
||||
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
|
||||
do {
|
||||
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
|
||||
value = SdioLocalCmd52Read1Byte(padapter, offset);
|
||||
else
|
||||
value = rtw_read8(padapter, offset);
|
||||
|
||||
value = value&GET_PWR_CFG_MASK(PwrCfgCmd);
|
||||
if (
|
||||
value == (GET_PWR_CFG_VALUE(PwrCfgCmd) &
|
||||
GET_PWR_CFG_MASK(PwrCfgCmd))
|
||||
)
|
||||
bPollingBit = true;
|
||||
else
|
||||
udelay(10);
|
||||
|
||||
if (pollingCount++ > maxPollingCnt) {
|
||||
DBG_871X(
|
||||
"Fail to polling Offset[%#x]=%02x\n",
|
||||
offset,
|
||||
value
|
||||
);
|
||||
return false;
|
||||
}
|
||||
} while (!bPollingBit);
|
||||
|
||||
break;
|
||||
|
||||
case PWR_CMD_DELAY:
|
||||
RT_TRACE(
|
||||
_module_hal_init_c_,
|
||||
_drv_info_,
|
||||
("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n")
|
||||
);
|
||||
if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
|
||||
udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd));
|
||||
else
|
||||
udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
|
||||
break;
|
||||
|
||||
case PWR_CMD_END:
|
||||
/* When this command is parsed, end the process */
|
||||
RT_TRACE(
|
||||
_module_hal_init_c_,
|
||||
_drv_info_,
|
||||
("HalPwrSeqCmdParsing: PWR_CMD_END\n")
|
||||
);
|
||||
return true;
|
||||
|
||||
default:
|
||||
RT_TRACE(
|
||||
_module_hal_init_c_,
|
||||
_drv_err_,
|
||||
("HalPwrSeqCmdParsing: Unknown CMD!!\n")
|
||||
);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
AryIdx++;/* Add Array Index */
|
||||
} while (1);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2013 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __MP_PRECOMP_H__
|
||||
#define __MP_PRECOMP_H__
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <hal_data.h>
|
||||
|
||||
#define BT_TMP_BUF_SIZE 100
|
||||
|
||||
#define DCMD_Printf DBG_BT_INFO
|
||||
|
||||
#ifdef bEnable
|
||||
#undef bEnable
|
||||
#endif
|
||||
|
||||
#include "HalBtcOutSrc.h"
|
||||
#include "HalBtc8723b1Ant.h"
|
||||
#include "HalBtc8723b2Ant.h"
|
||||
|
||||
#endif /* __MP_PRECOMP_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,474 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#define _HAL_INTF_C_
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <rtw_debug.h>
|
||||
#include <hal_data.h>
|
||||
|
||||
void rtw_hal_chip_configure(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.intf_chip_configure)
|
||||
padapter->HalFunc.intf_chip_configure(padapter);
|
||||
}
|
||||
|
||||
void rtw_hal_read_chip_info(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.read_adapter_info)
|
||||
padapter->HalFunc.read_adapter_info(padapter);
|
||||
}
|
||||
|
||||
void rtw_hal_read_chip_version(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.read_chip_version)
|
||||
padapter->HalFunc.read_chip_version(padapter);
|
||||
}
|
||||
|
||||
void rtw_hal_def_value_init(struct adapter *padapter)
|
||||
{
|
||||
if (is_primary_adapter(padapter))
|
||||
if (padapter->HalFunc.init_default_value)
|
||||
padapter->HalFunc.init_default_value(padapter);
|
||||
}
|
||||
|
||||
void rtw_hal_free_data(struct adapter *padapter)
|
||||
{
|
||||
/* free HAL Data */
|
||||
rtw_hal_data_deinit(padapter);
|
||||
|
||||
if (is_primary_adapter(padapter))
|
||||
if (padapter->HalFunc.free_hal_data)
|
||||
padapter->HalFunc.free_hal_data(padapter);
|
||||
}
|
||||
|
||||
void rtw_hal_dm_init(struct adapter *padapter)
|
||||
{
|
||||
if (is_primary_adapter(padapter))
|
||||
if (padapter->HalFunc.dm_init)
|
||||
padapter->HalFunc.dm_init(padapter);
|
||||
}
|
||||
|
||||
void rtw_hal_dm_deinit(struct adapter *padapter)
|
||||
{
|
||||
/* cancel dm timer */
|
||||
if (is_primary_adapter(padapter))
|
||||
if (padapter->HalFunc.dm_deinit)
|
||||
padapter->HalFunc.dm_deinit(padapter);
|
||||
}
|
||||
|
||||
static void rtw_hal_init_opmode(struct adapter *padapter)
|
||||
{
|
||||
enum NDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax;
|
||||
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
|
||||
sint fw_state;
|
||||
|
||||
fw_state = get_fwstate(pmlmepriv);
|
||||
|
||||
if (fw_state & WIFI_ADHOC_STATE)
|
||||
networkType = Ndis802_11IBSS;
|
||||
else if (fw_state & WIFI_STATION_STATE)
|
||||
networkType = Ndis802_11Infrastructure;
|
||||
else if (fw_state & WIFI_AP_STATE)
|
||||
networkType = Ndis802_11APMode;
|
||||
else
|
||||
return;
|
||||
|
||||
rtw_setopmode_cmd(padapter, networkType, false);
|
||||
}
|
||||
|
||||
uint rtw_hal_init(struct adapter *padapter)
|
||||
{
|
||||
uint status;
|
||||
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
|
||||
|
||||
status = padapter->HalFunc.hal_init(padapter);
|
||||
|
||||
if (status == _SUCCESS) {
|
||||
rtw_hal_init_opmode(padapter);
|
||||
|
||||
dvobj->padapters->hw_init_completed = true;
|
||||
|
||||
if (padapter->registrypriv.notch_filter == 1)
|
||||
rtw_hal_notch_filter(padapter, 1);
|
||||
|
||||
rtw_hal_reset_security_engine(padapter);
|
||||
|
||||
rtw_sec_restore_wep_key(dvobj->padapters);
|
||||
|
||||
init_hw_mlme_ext(padapter);
|
||||
|
||||
rtw_bb_rf_gain_offset(padapter);
|
||||
} else {
|
||||
dvobj->padapters->hw_init_completed = false;
|
||||
DBG_871X("rtw_hal_init: hal__init fail\n");
|
||||
}
|
||||
|
||||
RT_TRACE(_module_hal_init_c_, _drv_err_, ("-rtl871x_hal_init:status = 0x%x\n", status));
|
||||
|
||||
return status;
|
||||
|
||||
}
|
||||
|
||||
uint rtw_hal_deinit(struct adapter *padapter)
|
||||
{
|
||||
uint status = _SUCCESS;
|
||||
struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
|
||||
|
||||
status = padapter->HalFunc.hal_deinit(padapter);
|
||||
|
||||
if (status == _SUCCESS) {
|
||||
padapter = dvobj->padapters;
|
||||
padapter->hw_init_completed = false;
|
||||
} else {
|
||||
DBG_871X("\n rtw_hal_deinit: hal_init fail\n");
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
void rtw_hal_set_hwreg(struct adapter *padapter, u8 variable, u8 *val)
|
||||
{
|
||||
if (padapter->HalFunc.SetHwRegHandler)
|
||||
padapter->HalFunc.SetHwRegHandler(padapter, variable, val);
|
||||
}
|
||||
|
||||
void rtw_hal_get_hwreg(struct adapter *padapter, u8 variable, u8 *val)
|
||||
{
|
||||
if (padapter->HalFunc.GetHwRegHandler)
|
||||
padapter->HalFunc.GetHwRegHandler(padapter, variable, val);
|
||||
}
|
||||
|
||||
void rtw_hal_set_hwreg_with_buf(struct adapter *padapter, u8 variable, u8 *pbuf, int len)
|
||||
{
|
||||
if (padapter->HalFunc.SetHwRegHandlerWithBuf)
|
||||
padapter->HalFunc.SetHwRegHandlerWithBuf(padapter, variable, pbuf, len);
|
||||
}
|
||||
|
||||
u8 rtw_hal_set_def_var(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void *pValue)
|
||||
{
|
||||
if (padapter->HalFunc.SetHalDefVarHandler)
|
||||
return padapter->HalFunc.SetHalDefVarHandler(padapter, eVariable, pValue);
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
u8 rtw_hal_get_def_var(struct adapter *padapter, enum HAL_DEF_VARIABLE eVariable, void *pValue)
|
||||
{
|
||||
if (padapter->HalFunc.GetHalDefVarHandler)
|
||||
return padapter->HalFunc.GetHalDefVarHandler(padapter, eVariable, pValue);
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
void rtw_hal_set_odm_var(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void *pValue1, bool bSet)
|
||||
{
|
||||
if (padapter->HalFunc.SetHalODMVarHandler)
|
||||
padapter->HalFunc.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet);
|
||||
}
|
||||
|
||||
void rtw_hal_get_odm_var(struct adapter *padapter, enum HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2)
|
||||
{
|
||||
if (padapter->HalFunc.GetHalODMVarHandler)
|
||||
padapter->HalFunc.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2);
|
||||
}
|
||||
|
||||
void rtw_hal_enable_interrupt(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.enable_interrupt)
|
||||
padapter->HalFunc.enable_interrupt(padapter);
|
||||
else
|
||||
DBG_871X("%s: HalFunc.enable_interrupt is NULL!\n", __func__);
|
||||
|
||||
}
|
||||
|
||||
void rtw_hal_disable_interrupt(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.disable_interrupt)
|
||||
padapter->HalFunc.disable_interrupt(padapter);
|
||||
else
|
||||
DBG_871X("%s: HalFunc.disable_interrupt is NULL!\n", __func__);
|
||||
|
||||
}
|
||||
|
||||
u8 rtw_hal_check_ips_status(struct adapter *padapter)
|
||||
{
|
||||
u8 val = false;
|
||||
if (padapter->HalFunc.check_ips_status)
|
||||
val = padapter->HalFunc.check_ips_status(padapter);
|
||||
else
|
||||
DBG_871X("%s: HalFunc.check_ips_status is NULL!\n", __func__);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
s32 rtw_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe)
|
||||
{
|
||||
if (padapter->HalFunc.hal_xmitframe_enqueue)
|
||||
return padapter->HalFunc.hal_xmitframe_enqueue(padapter, pxmitframe);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
s32 rtw_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe)
|
||||
{
|
||||
if (padapter->HalFunc.hal_xmit)
|
||||
return padapter->HalFunc.hal_xmit(padapter, pxmitframe);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* [IMPORTANT] This function would be run in interrupt context.
|
||||
*/
|
||||
s32 rtw_hal_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe)
|
||||
{
|
||||
s32 ret = _FAIL;
|
||||
update_mgntframe_attrib_addr(padapter, pmgntframe);
|
||||
/* pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; */
|
||||
/* pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; */
|
||||
/* memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN); */
|
||||
|
||||
if (padapter->securitypriv.binstallBIPkey == true) {
|
||||
if (IS_MCAST(pmgntframe->attrib.ra)) {
|
||||
pmgntframe->attrib.encrypt = _BIP_;
|
||||
/* pmgntframe->attrib.bswenc = true; */
|
||||
} else {
|
||||
pmgntframe->attrib.encrypt = _AES_;
|
||||
pmgntframe->attrib.bswenc = true;
|
||||
}
|
||||
rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe);
|
||||
}
|
||||
|
||||
if (padapter->HalFunc.mgnt_xmit)
|
||||
ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe);
|
||||
return ret;
|
||||
}
|
||||
|
||||
s32 rtw_hal_init_xmit_priv(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.init_xmit_priv != NULL)
|
||||
return padapter->HalFunc.init_xmit_priv(padapter);
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
void rtw_hal_free_xmit_priv(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.free_xmit_priv != NULL)
|
||||
padapter->HalFunc.free_xmit_priv(padapter);
|
||||
}
|
||||
|
||||
s32 rtw_hal_init_recv_priv(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.init_recv_priv)
|
||||
return padapter->HalFunc.init_recv_priv(padapter);
|
||||
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
void rtw_hal_free_recv_priv(struct adapter *padapter)
|
||||
{
|
||||
|
||||
if (padapter->HalFunc.free_recv_priv)
|
||||
padapter->HalFunc.free_recv_priv(padapter);
|
||||
}
|
||||
|
||||
void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level)
|
||||
{
|
||||
struct adapter *padapter;
|
||||
struct mlme_priv *pmlmepriv;
|
||||
|
||||
if (!psta)
|
||||
return;
|
||||
|
||||
padapter = psta->padapter;
|
||||
|
||||
pmlmepriv = &(padapter->mlmepriv);
|
||||
|
||||
if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == true)
|
||||
add_RATid(padapter, psta, rssi_level);
|
||||
else {
|
||||
if (padapter->HalFunc.UpdateRAMaskHandler)
|
||||
padapter->HalFunc.UpdateRAMaskHandler(padapter, psta->mac_id, rssi_level);
|
||||
}
|
||||
}
|
||||
|
||||
void rtw_hal_add_ra_tid(struct adapter *padapter, u32 bitmap, u8 *arg, u8 rssi_level)
|
||||
{
|
||||
if (padapter->HalFunc.Add_RateATid)
|
||||
padapter->HalFunc.Add_RateATid(padapter, bitmap, arg, rssi_level);
|
||||
}
|
||||
|
||||
/*Start specifical interface thread */
|
||||
void rtw_hal_start_thread(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.run_thread)
|
||||
padapter->HalFunc.run_thread(padapter);
|
||||
}
|
||||
/*Start specifical interface thread */
|
||||
void rtw_hal_stop_thread(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.cancel_thread)
|
||||
padapter->HalFunc.cancel_thread(padapter);
|
||||
}
|
||||
|
||||
u32 rtw_hal_read_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask)
|
||||
{
|
||||
u32 data = 0;
|
||||
if (padapter->HalFunc.read_bbreg)
|
||||
data = padapter->HalFunc.read_bbreg(padapter, RegAddr, BitMask);
|
||||
return data;
|
||||
}
|
||||
void rtw_hal_write_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data)
|
||||
{
|
||||
if (padapter->HalFunc.write_bbreg)
|
||||
padapter->HalFunc.write_bbreg(padapter, RegAddr, BitMask, Data);
|
||||
}
|
||||
|
||||
u32 rtw_hal_read_rfreg(struct adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask)
|
||||
{
|
||||
u32 data = 0;
|
||||
if (padapter->HalFunc.read_rfreg)
|
||||
data = padapter->HalFunc.read_rfreg(padapter, eRFPath, RegAddr, BitMask);
|
||||
return data;
|
||||
}
|
||||
void rtw_hal_write_rfreg(struct adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
|
||||
{
|
||||
if (padapter->HalFunc.write_rfreg)
|
||||
padapter->HalFunc.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data);
|
||||
}
|
||||
|
||||
void rtw_hal_set_chan(struct adapter *padapter, u8 channel)
|
||||
{
|
||||
if (padapter->HalFunc.set_channel_handler)
|
||||
padapter->HalFunc.set_channel_handler(padapter, channel);
|
||||
}
|
||||
|
||||
void rtw_hal_set_chnl_bw(struct adapter *padapter, u8 channel,
|
||||
enum CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80)
|
||||
{
|
||||
if (padapter->HalFunc.set_chnl_bw_handler)
|
||||
padapter->HalFunc.set_chnl_bw_handler(padapter, channel,
|
||||
Bandwidth, Offset40,
|
||||
Offset80);
|
||||
}
|
||||
|
||||
void rtw_hal_dm_watchdog(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.hal_dm_watchdog)
|
||||
padapter->HalFunc.hal_dm_watchdog(padapter);
|
||||
|
||||
}
|
||||
|
||||
void rtw_hal_dm_watchdog_in_lps(struct adapter *padapter)
|
||||
{
|
||||
if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == true) {
|
||||
if (padapter->HalFunc.hal_dm_watchdog_in_lps)
|
||||
padapter->HalFunc.hal_dm_watchdog_in_lps(padapter); /* this fuction caller is in interrupt context */
|
||||
}
|
||||
}
|
||||
|
||||
void rtw_hal_bcn_related_reg_setting(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.SetBeaconRelatedRegistersHandler)
|
||||
padapter->HalFunc.SetBeaconRelatedRegistersHandler(padapter);
|
||||
}
|
||||
|
||||
|
||||
s32 rtw_hal_xmit_thread_handler(struct adapter *padapter)
|
||||
{
|
||||
if (padapter->HalFunc.xmit_thread_handler)
|
||||
return padapter->HalFunc.xmit_thread_handler(padapter);
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
void rtw_hal_notch_filter(struct adapter *adapter, bool enable)
|
||||
{
|
||||
if (adapter->HalFunc.hal_notch_filter)
|
||||
adapter->HalFunc.hal_notch_filter(adapter, enable);
|
||||
}
|
||||
|
||||
void rtw_hal_reset_security_engine(struct adapter *adapter)
|
||||
{
|
||||
if (adapter->HalFunc.hal_reset_security_engine)
|
||||
adapter->HalFunc.hal_reset_security_engine(adapter);
|
||||
}
|
||||
|
||||
bool rtw_hal_c2h_valid(struct adapter *adapter, u8 *buf)
|
||||
{
|
||||
return c2h_evt_valid((struct c2h_evt_hdr_88xx *)buf);
|
||||
}
|
||||
|
||||
s32 rtw_hal_c2h_evt_read(struct adapter *adapter, u8 *buf)
|
||||
{
|
||||
return c2h_evt_read_88xx(adapter, buf);
|
||||
}
|
||||
|
||||
s32 rtw_hal_c2h_handler(struct adapter *adapter, u8 *c2h_evt)
|
||||
{
|
||||
s32 ret = _FAIL;
|
||||
if (adapter->HalFunc.c2h_handler)
|
||||
ret = adapter->HalFunc.c2h_handler(adapter, c2h_evt);
|
||||
return ret;
|
||||
}
|
||||
|
||||
c2h_id_filter rtw_hal_c2h_id_filter_ccx(struct adapter *adapter)
|
||||
{
|
||||
return adapter->HalFunc.c2h_id_filter_ccx;
|
||||
}
|
||||
|
||||
s32 rtw_hal_is_disable_sw_channel_plan(struct adapter *padapter)
|
||||
{
|
||||
return GET_HAL_DATA(padapter)->bDisableSWChannelPlan;
|
||||
}
|
||||
|
||||
s32 rtw_hal_macid_sleep(struct adapter *padapter, u32 macid)
|
||||
{
|
||||
u8 support;
|
||||
|
||||
|
||||
support = false;
|
||||
rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support);
|
||||
if (false == support)
|
||||
return _FAIL;
|
||||
|
||||
rtw_hal_set_hwreg(padapter, HW_VAR_MACID_SLEEP, (u8 *)&macid);
|
||||
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
s32 rtw_hal_macid_wakeup(struct adapter *padapter, u32 macid)
|
||||
{
|
||||
u8 support;
|
||||
|
||||
|
||||
support = false;
|
||||
rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support);
|
||||
if (false == support)
|
||||
return _FAIL;
|
||||
|
||||
rtw_hal_set_hwreg(padapter, HW_VAR_MACID_WAKEUP, (u8 *)&macid);
|
||||
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
s32 rtw_hal_fill_h2c_cmd(struct adapter *padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
|
||||
{
|
||||
s32 ret = _FAIL;
|
||||
|
||||
if (padapter->HalFunc.fill_h2c_cmd)
|
||||
ret = padapter->HalFunc.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
|
||||
else
|
||||
DBG_871X("%s: func[fill_h2c_cmd] not defined!\n", __func__);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define _HAL_PHY_C_
|
||||
|
||||
#include <drv_types.h>
|
||||
|
||||
/**
|
||||
* Function: PHY_CalculateBitShift
|
||||
*
|
||||
* OverView: Get shifted position of the BitMask
|
||||
*
|
||||
* Input:
|
||||
* u32 BitMask,
|
||||
*
|
||||
* Output: none
|
||||
* Return: u32 Return the shift bit bit position of the mask
|
||||
*/
|
||||
u32 PHY_CalculateBitShift(u32 BitMask)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i <= 31; i++) {
|
||||
if (((BitMask>>i) & 0x1) == 1)
|
||||
break;
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
|
||||
/* */
|
||||
/* ==> RF shadow Operation API Code Section!!! */
|
||||
/* */
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: PHY_RFShadowRead
|
||||
* PHY_RFShadowWrite
|
||||
* PHY_RFShadowCompare
|
||||
* PHY_RFShadowRecorver
|
||||
* PHY_RFShadowCompareAll
|
||||
* PHY_RFShadowRecorverAll
|
||||
* PHY_RFShadowCompareFlagSet
|
||||
* PHY_RFShadowRecorverFlagSet
|
||||
*
|
||||
* Overview: When we set RF register, we must write shadow at first.
|
||||
* When we are running, we must compare shadow abd locate error addr.
|
||||
* Decide to recorver or not.
|
||||
*
|
||||
* Input: NONE
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Revised History:
|
||||
* When Who Remark
|
||||
* 11/20/2008 MHC Create Version 0.
|
||||
*
|
||||
*---------------------------------------------------------------------------*/
|
||||
u32 PHY_RFShadowRead(IN PADAPTER Adapter, IN u8 eRFPath, IN u32 Offset)
|
||||
{
|
||||
return RF_Shadow[eRFPath][Offset].Value;
|
||||
|
||||
} /* PHY_RFShadowRead */
|
||||
|
||||
|
||||
void PHY_RFShadowWrite(
|
||||
IN PADAPTER Adapter, IN u8 eRFPath, IN u32 Offset, IN u32 Data
|
||||
)
|
||||
{
|
||||
RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
|
||||
RF_Shadow[eRFPath][Offset].Driver_Write = true;
|
||||
|
||||
} /* PHY_RFShadowWrite */
|
||||
|
||||
|
||||
bool PHY_RFShadowCompare(IN PADAPTER Adapter, IN u8 eRFPath, IN u32 Offset)
|
||||
{
|
||||
u32 reg;
|
||||
/* Check if we need to check the register */
|
||||
if (RF_Shadow[eRFPath][Offset].Compare == true) {
|
||||
reg = rtw_hal_read_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask);
|
||||
/* Compare shadow and real rf register for 20bits!! */
|
||||
if (RF_Shadow[eRFPath][Offset].Value != reg) {
|
||||
/* Locate error position. */
|
||||
RF_Shadow[eRFPath][Offset].ErrorOrNot = true;
|
||||
/* RT_TRACE(COMP_INIT, DBG_LOUD, */
|
||||
/* PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n", */
|
||||
/* eRFPath, Offset, reg)); */
|
||||
}
|
||||
return RF_Shadow[eRFPath][Offset].ErrorOrNot;
|
||||
}
|
||||
return false;
|
||||
} /* PHY_RFShadowCompare */
|
||||
|
||||
|
||||
void PHY_RFShadowRecorver(IN PADAPTER Adapter, IN u8 eRFPath, IN u32 Offset)
|
||||
{
|
||||
/* Check if the address is error */
|
||||
if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true) {
|
||||
/* Check if we need to recorver the register. */
|
||||
if (RF_Shadow[eRFPath][Offset].Recorver == true) {
|
||||
rtw_hal_write_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask,
|
||||
RF_Shadow[eRFPath][Offset].Value);
|
||||
/* RT_TRACE(COMP_INIT, DBG_LOUD, */
|
||||
/* PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx", */
|
||||
/* eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value)); */
|
||||
}
|
||||
}
|
||||
|
||||
} /* PHY_RFShadowRecorver */
|
||||
|
||||
|
||||
void PHY_RFShadowCompareAll(IN PADAPTER Adapter)
|
||||
{
|
||||
u8 eRFPath = 0;
|
||||
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
|
||||
|
||||
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
|
||||
for (Offset = 0; Offset < maxReg; Offset++) {
|
||||
PHY_RFShadowCompare(Adapter, eRFPath, Offset);
|
||||
}
|
||||
}
|
||||
|
||||
} /* PHY_RFShadowCompareAll */
|
||||
|
||||
|
||||
void PHY_RFShadowRecorverAll(IN PADAPTER Adapter)
|
||||
{
|
||||
u8 eRFPath = 0;
|
||||
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
|
||||
|
||||
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
|
||||
for (Offset = 0; Offset < maxReg; Offset++) {
|
||||
PHY_RFShadowRecorver(Adapter, eRFPath, Offset);
|
||||
}
|
||||
}
|
||||
|
||||
} /* PHY_RFShadowRecorverAll */
|
||||
|
||||
|
||||
void
|
||||
PHY_RFShadowCompareFlagSet(
|
||||
IN PADAPTER Adapter, IN u8 eRFPath, IN u32 Offset, IN u8 Type
|
||||
)
|
||||
{
|
||||
/* Set True or False!!! */
|
||||
RF_Shadow[eRFPath][Offset].Compare = Type;
|
||||
|
||||
} /* PHY_RFShadowCompareFlagSet */
|
||||
|
||||
|
||||
void PHY_RFShadowRecorverFlagSet(
|
||||
IN PADAPTER Adapter, IN u8 eRFPath, IN u32 Offset, IN u8 Type
|
||||
)
|
||||
{
|
||||
/* Set True or False!!! */
|
||||
RF_Shadow[eRFPath][Offset].Recorver = Type;
|
||||
|
||||
} /* PHY_RFShadowRecorverFlagSet */
|
||||
|
||||
|
||||
void PHY_RFShadowCompareFlagSetAll(IN PADAPTER Adapter)
|
||||
{
|
||||
u8 eRFPath = 0;
|
||||
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
|
||||
|
||||
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
|
||||
for (Offset = 0; Offset < maxReg; Offset++) {
|
||||
/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */
|
||||
if (Offset != 0x26 && Offset != 0x27)
|
||||
PHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, false);
|
||||
else
|
||||
PHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, true);
|
||||
}
|
||||
}
|
||||
|
||||
} /* PHY_RFShadowCompareFlagSetAll */
|
||||
|
||||
|
||||
void PHY_RFShadowRecorverFlagSetAll(IN PADAPTER Adapter)
|
||||
{
|
||||
u8 eRFPath = 0;
|
||||
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
|
||||
|
||||
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
|
||||
for (Offset = 0; Offset < maxReg; Offset++) {
|
||||
/* 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! */
|
||||
if (Offset != 0x26 && Offset != 0x27)
|
||||
PHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, false);
|
||||
else
|
||||
PHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, true);
|
||||
}
|
||||
}
|
||||
|
||||
} /* PHY_RFShadowCompareFlagSetAll */
|
||||
|
||||
void PHY_RFShadowRefresh(IN PADAPTER Adapter)
|
||||
{
|
||||
u8 eRFPath = 0;
|
||||
u32 Offset = 0, maxReg = GET_RF6052_REAL_MAX_REG(Adapter);
|
||||
|
||||
for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) {
|
||||
for (Offset = 0; Offset < maxReg; Offset++) {
|
||||
RF_Shadow[eRFPath][Offset].Value = 0;
|
||||
RF_Shadow[eRFPath][Offset].Compare = false;
|
||||
RF_Shadow[eRFPath][Offset].Recorver = false;
|
||||
RF_Shadow[eRFPath][Offset].ErrorOrNot = false;
|
||||
RF_Shadow[eRFPath][Offset].Driver_Write = false;
|
||||
}
|
||||
}
|
||||
|
||||
} /* PHY_RFShadowRead */
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define _HAL_SDIO_C_
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <rtw_debug.h>
|
||||
#include <hal_data.h>
|
||||
|
||||
u8 rtw_hal_sdio_max_txoqt_free_space(struct adapter *padapter)
|
||||
{
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
|
||||
|
||||
if (pHalData->SdioTxOQTMaxFreeSpace < 8)
|
||||
pHalData->SdioTxOQTMaxFreeSpace = 8;
|
||||
|
||||
return pHalData->SdioTxOQTMaxFreeSpace;
|
||||
}
|
||||
|
||||
u8 rtw_hal_sdio_query_tx_freepage(
|
||||
struct adapter *padapter, u8 PageIdx, u8 RequiredPageNum
|
||||
)
|
||||
{
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
|
||||
|
||||
if ((pHalData->SdioTxFIFOFreePage[PageIdx]+pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]) >= (RequiredPageNum))
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
void rtw_hal_sdio_update_tx_freepage(
|
||||
struct adapter *padapter, u8 PageIdx, u8 RequiredPageNum
|
||||
)
|
||||
{
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
|
||||
u8 DedicatedPgNum = 0;
|
||||
u8 RequiredPublicFreePgNum = 0;
|
||||
/* _irqL irql; */
|
||||
|
||||
/* spin_lock_bh(&pHalData->SdioTxFIFOFreePageLock); */
|
||||
|
||||
DedicatedPgNum = pHalData->SdioTxFIFOFreePage[PageIdx];
|
||||
if (RequiredPageNum <= DedicatedPgNum) {
|
||||
pHalData->SdioTxFIFOFreePage[PageIdx] -= RequiredPageNum;
|
||||
} else {
|
||||
pHalData->SdioTxFIFOFreePage[PageIdx] = 0;
|
||||
RequiredPublicFreePgNum = RequiredPageNum - DedicatedPgNum;
|
||||
pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= RequiredPublicFreePgNum;
|
||||
}
|
||||
|
||||
/* spin_unlock_bh(&pHalData->SdioTxFIFOFreePageLock); */
|
||||
}
|
||||
|
||||
void rtw_hal_set_sdio_tx_max_length(
|
||||
struct adapter *padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ
|
||||
)
|
||||
{
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
|
||||
u32 page_size;
|
||||
u32 lenHQ, lenNQ, lenLQ;
|
||||
|
||||
rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_SIZE, &page_size);
|
||||
|
||||
lenHQ = ((numHQ + numPubQ) >> 1) * page_size;
|
||||
lenNQ = ((numNQ + numPubQ) >> 1) * page_size;
|
||||
lenLQ = ((numLQ + numPubQ) >> 1) * page_size;
|
||||
|
||||
pHalData->sdio_tx_max_len[HI_QUEUE_IDX] =
|
||||
(lenHQ > MAX_XMITBUF_SZ) ? MAX_XMITBUF_SZ : lenHQ;
|
||||
pHalData->sdio_tx_max_len[MID_QUEUE_IDX] =
|
||||
(lenNQ > MAX_XMITBUF_SZ) ? MAX_XMITBUF_SZ : lenNQ;
|
||||
pHalData->sdio_tx_max_len[LOW_QUEUE_IDX] =
|
||||
(lenLQ > MAX_XMITBUF_SZ) ? MAX_XMITBUF_SZ : lenLQ;
|
||||
}
|
||||
|
||||
u32 rtw_hal_get_sdio_tx_max_length(struct adapter *padapter, u8 queue_idx)
|
||||
{
|
||||
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
|
||||
u32 deviceId, max_len;
|
||||
|
||||
|
||||
deviceId = ffaddr2deviceId(pdvobjpriv, queue_idx);
|
||||
switch (deviceId) {
|
||||
case WLAN_TX_HIQ_DEVICE_ID:
|
||||
max_len = pHalData->sdio_tx_max_len[HI_QUEUE_IDX];
|
||||
break;
|
||||
|
||||
case WLAN_TX_MIQ_DEVICE_ID:
|
||||
max_len = pHalData->sdio_tx_max_len[MID_QUEUE_IDX];
|
||||
break;
|
||||
|
||||
case WLAN_TX_LOQ_DEVICE_ID:
|
||||
max_len = pHalData->sdio_tx_max_len[LOW_QUEUE_IDX];
|
||||
break;
|
||||
|
||||
default:
|
||||
max_len = pHalData->sdio_tx_max_len[MID_QUEUE_IDX];
|
||||
break;
|
||||
}
|
||||
|
||||
return max_len;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,70 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
//============================================================
|
||||
// include files
|
||||
//============================================================
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
//======================================================
|
||||
// when antenna test utility is on or some testing
|
||||
// need to disable antenna diversity
|
||||
// call this function to disable all ODM related mechanisms
|
||||
// which will switch antenna.
|
||||
//======================================================
|
||||
void ODM_StopAntennaSwitchDm(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
// disable ODM antenna diversity
|
||||
pDM_Odm->SupportAbility &= ~ODM_BB_ANT_DIV;
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_ANT_DIV,
|
||||
ODM_DBG_LOUD,
|
||||
("STOP Antenna Diversity\n")
|
||||
);
|
||||
}
|
||||
|
||||
void ODM_SetAntConfig(PDM_ODM_T pDM_Odm, u8 antSetting)// 0=A, 1=B, 2=C, ....
|
||||
{
|
||||
if (antSetting == 0) // ant A
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000);
|
||||
else if (antSetting == 1)
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280);
|
||||
}
|
||||
|
||||
//======================================================
|
||||
|
||||
|
||||
void ODM_SwAntDivRestAfterLink(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
|
||||
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
|
||||
u32 i;
|
||||
|
||||
pDM_Odm->RSSI_test = false;
|
||||
pDM_SWAT_Table->try_flag = 0xff;
|
||||
pDM_SWAT_Table->RSSI_Trying = 0;
|
||||
pDM_SWAT_Table->Double_chk_flag = 0;
|
||||
|
||||
pDM_FatTable->RxIdleAnt = MAIN_ANT;
|
||||
|
||||
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
|
||||
pDM_FatTable->MainAnt_Sum[i] = 0;
|
||||
pDM_FatTable->AuxAnt_Sum[i] = 0;
|
||||
pDM_FatTable->MainAnt_Cnt[i] = 0;
|
||||
pDM_FatTable->AuxAnt_Cnt[i] = 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODMANTDIV_H__
|
||||
#define __ODMANTDIV_H__
|
||||
|
||||
|
||||
|
||||
#define ANT1_2G 0 /* = ANT2_5G */
|
||||
#define ANT2_2G 1 /* = ANT1_5G */
|
||||
|
||||
/* Antenna Diversty Control Type */
|
||||
#define ODM_AUTO_ANT 0
|
||||
#define ODM_FIX_MAIN_ANT 1
|
||||
#define ODM_FIX_AUX_ANT 2
|
||||
|
||||
#define TX_BY_REG 0
|
||||
|
||||
#define ANTDIV_ON 1
|
||||
#define ANTDIV_OFF 0
|
||||
|
||||
#define INIT_ANTDIV_TIMMER 0
|
||||
#define CANCEL_ANTDIV_TIMMER 1
|
||||
#define RELEASE_ANTDIV_TIMMER 2
|
||||
|
||||
#endif /* ifndef __ODMANTDIV_H__ */
|
||||
|
|
@ -0,0 +1,338 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
static void odm_SetCrystalCap(void *pDM_VOID, u8 CrystalCap)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
|
||||
bool bEEPROMCheck;
|
||||
struct adapter *Adapter = pDM_Odm->Adapter;
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
bEEPROMCheck = (pHalData->EEPROMVersion >= 0x01) ? true : false;
|
||||
|
||||
if (pCfoTrack->CrystalCap == CrystalCap)
|
||||
return;
|
||||
|
||||
pCfoTrack->CrystalCap = CrystalCap;
|
||||
|
||||
/* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */
|
||||
CrystalCap = CrystalCap & 0x3F;
|
||||
PHY_SetBBReg(
|
||||
pDM_Odm->Adapter,
|
||||
REG_MAC_PHY_CTRL,
|
||||
0x00FFF000,
|
||||
(CrystalCap | (CrystalCap << 6))
|
||||
);
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"odm_SetCrystalCap(): CrystalCap = 0x%x\n",
|
||||
CrystalCap
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
static u8 odm_GetDefaultCrytaltalCap(void *pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
u8 CrystalCap = 0x20;
|
||||
|
||||
struct adapter *Adapter = pDM_Odm->Adapter;
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
CrystalCap = pHalData->CrystalCap;
|
||||
|
||||
CrystalCap = CrystalCap & 0x3f;
|
||||
|
||||
return CrystalCap;
|
||||
}
|
||||
|
||||
static void odm_SetATCStatus(void *pDM_VOID, bool ATCStatus)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
|
||||
|
||||
if (pCfoTrack->bATCStatus == ATCStatus)
|
||||
return;
|
||||
|
||||
PHY_SetBBReg(
|
||||
pDM_Odm->Adapter,
|
||||
ODM_REG(BB_ATC, pDM_Odm),
|
||||
ODM_BIT(BB_ATC, pDM_Odm),
|
||||
ATCStatus
|
||||
);
|
||||
pCfoTrack->bATCStatus = ATCStatus;
|
||||
}
|
||||
|
||||
static bool odm_GetATCStatus(void *pDM_VOID)
|
||||
{
|
||||
bool ATCStatus;
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
ATCStatus = (bool)PHY_QueryBBReg(
|
||||
pDM_Odm->Adapter,
|
||||
ODM_REG(BB_ATC, pDM_Odm),
|
||||
ODM_BIT(BB_ATC, pDM_Odm)
|
||||
);
|
||||
return ATCStatus;
|
||||
}
|
||||
|
||||
void ODM_CfoTrackingReset(void *pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
|
||||
|
||||
pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
|
||||
pCfoTrack->bAdjust = true;
|
||||
|
||||
odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap);
|
||||
odm_SetATCStatus(pDM_Odm, true);
|
||||
}
|
||||
|
||||
void ODM_CfoTrackingInit(void *pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
|
||||
|
||||
pCfoTrack->DefXCap =
|
||||
pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
|
||||
pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm);
|
||||
pCfoTrack->bAdjust = true;
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
("ODM_CfoTracking_init() =========>\n")
|
||||
);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x\n",
|
||||
pCfoTrack->bATCStatus,
|
||||
pCfoTrack->DefXCap
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
void ODM_CfoTracking(void *pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
|
||||
int CFO_kHz_A, CFO_kHz_B, CFO_ave = 0;
|
||||
int CFO_ave_diff;
|
||||
int CrystalCap = (int)pCfoTrack->CrystalCap;
|
||||
u8 Adjust_Xtal = 1;
|
||||
|
||||
/* 4 Support ability */
|
||||
if (!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled\n")
|
||||
);
|
||||
return;
|
||||
}
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
("ODM_CfoTracking() =========>\n")
|
||||
);
|
||||
|
||||
if (!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly) {
|
||||
/* 4 No link or more than one entry */
|
||||
ODM_CfoTrackingReset(pDM_Odm);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"ODM_CfoTracking(): Reset: bLinked = %d, bOneEntryOnly = %d\n",
|
||||
pDM_Odm->bLinked,
|
||||
pDM_Odm->bOneEntryOnly
|
||||
)
|
||||
);
|
||||
} else {
|
||||
/* 3 1. CFO Tracking */
|
||||
/* 4 1.1 No new packet */
|
||||
if (pCfoTrack->packetCount == pCfoTrack->packetCount_pre) {
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"ODM_CfoTracking(): packet counter doesn't change\n"
|
||||
)
|
||||
);
|
||||
return;
|
||||
}
|
||||
pCfoTrack->packetCount_pre = pCfoTrack->packetCount;
|
||||
|
||||
/* 4 1.2 Calculate CFO */
|
||||
CFO_kHz_A = (int)(pCfoTrack->CFO_tail[0] * 3125) / 1280;
|
||||
CFO_kHz_B = (int)(pCfoTrack->CFO_tail[1] * 3125) / 1280;
|
||||
|
||||
if (pDM_Odm->RFType < ODM_2T2R)
|
||||
CFO_ave = CFO_kHz_A;
|
||||
else
|
||||
CFO_ave = (int)(CFO_kHz_A + CFO_kHz_B) >> 1;
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"ODM_CfoTracking(): CFO_kHz_A = %dkHz, CFO_kHz_B = %dkHz, CFO_ave = %dkHz\n",
|
||||
CFO_kHz_A,
|
||||
CFO_kHz_B,
|
||||
CFO_ave
|
||||
)
|
||||
);
|
||||
|
||||
/* 4 1.3 Avoid abnormal large CFO */
|
||||
CFO_ave_diff =
|
||||
(pCfoTrack->CFO_ave_pre >= CFO_ave) ?
|
||||
(pCfoTrack->CFO_ave_pre-CFO_ave) :
|
||||
(CFO_ave-pCfoTrack->CFO_ave_pre);
|
||||
|
||||
if (
|
||||
CFO_ave_diff > 20 &&
|
||||
pCfoTrack->largeCFOHit == 0 &&
|
||||
!pCfoTrack->bAdjust
|
||||
) {
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): first large CFO hit\n"));
|
||||
pCfoTrack->largeCFOHit = 1;
|
||||
return;
|
||||
} else
|
||||
pCfoTrack->largeCFOHit = 0;
|
||||
pCfoTrack->CFO_ave_pre = CFO_ave;
|
||||
|
||||
/* 4 1.4 Dynamic Xtal threshold */
|
||||
if (pCfoTrack->bAdjust == false) {
|
||||
if (CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH))
|
||||
pCfoTrack->bAdjust = true;
|
||||
} else {
|
||||
if (CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW))
|
||||
pCfoTrack->bAdjust = false;
|
||||
}
|
||||
|
||||
/* 4 1.5 BT case: Disable CFO tracking */
|
||||
if (pDM_Odm->bBtEnabled) {
|
||||
pCfoTrack->bAdjust = false;
|
||||
odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
("ODM_CfoTracking(): Disable CFO tracking for BT!!\n")
|
||||
);
|
||||
}
|
||||
|
||||
/* 4 1.6 Big jump */
|
||||
if (pCfoTrack->bAdjust) {
|
||||
if (CFO_ave > CFO_TH_XTAL_LOW)
|
||||
Adjust_Xtal = Adjust_Xtal+((CFO_ave-CFO_TH_XTAL_LOW)>>2);
|
||||
else if (CFO_ave < (-CFO_TH_XTAL_LOW))
|
||||
Adjust_Xtal = Adjust_Xtal+((CFO_TH_XTAL_LOW-CFO_ave)>>2);
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"ODM_CfoTracking(): Crystal cap offset = %d\n",
|
||||
Adjust_Xtal
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
/* 4 1.7 Adjust Crystal Cap. */
|
||||
if (pCfoTrack->bAdjust) {
|
||||
if (CFO_ave > CFO_TH_XTAL_LOW)
|
||||
CrystalCap = CrystalCap + Adjust_Xtal;
|
||||
else if (CFO_ave < (-CFO_TH_XTAL_LOW))
|
||||
CrystalCap = CrystalCap - Adjust_Xtal;
|
||||
|
||||
if (CrystalCap > 0x3f)
|
||||
CrystalCap = 0x3f;
|
||||
else if (CrystalCap < 0)
|
||||
CrystalCap = 0;
|
||||
|
||||
odm_SetCrystalCap(pDM_Odm, (u8)CrystalCap);
|
||||
}
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"ODM_CfoTracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
|
||||
pCfoTrack->CrystalCap,
|
||||
pCfoTrack->DefXCap
|
||||
)
|
||||
);
|
||||
|
||||
/* 3 2. Dynamic ATC switch */
|
||||
if (CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) {
|
||||
odm_SetATCStatus(pDM_Odm, false);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
("ODM_CfoTracking(): Disable ATC!!\n")
|
||||
);
|
||||
} else {
|
||||
odm_SetATCStatus(pDM_Odm, true);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_CFO_TRACKING,
|
||||
ODM_DBG_LOUD,
|
||||
("ODM_CfoTracking(): Enable ATC!!\n")
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ODM_ParsingCFO(void *pDM_VOID, void *pPktinfo_VOID, s8 *pcfotail)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
PODM_PACKET_INFO_T pPktinfo = (PODM_PACKET_INFO_T)pPktinfo_VOID;
|
||||
PCFO_TRACKING pCfoTrack = &pDM_Odm->DM_CfoTrack;
|
||||
u8 i;
|
||||
|
||||
if (!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
|
||||
return;
|
||||
|
||||
if (pPktinfo->StationID != 0) {
|
||||
/* 3 Update CFO report for path-A & path-B */
|
||||
/* Only paht-A and path-B have CFO tail and short CFO */
|
||||
for (i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++)
|
||||
pCfoTrack->CFO_tail[i] = (int)pcfotail[i];
|
||||
|
||||
/* 3 Update packet counter */
|
||||
if (pCfoTrack->packetCount == 0xffffffff)
|
||||
pCfoTrack->packetCount = 0;
|
||||
else
|
||||
pCfoTrack->packetCount++;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODMCFOTRACK_H__
|
||||
#define __ODMCFOTRACK_H__
|
||||
|
||||
#define CFO_TH_XTAL_HIGH 20 /* kHz */
|
||||
#define CFO_TH_XTAL_LOW 10 /* kHz */
|
||||
#define CFO_TH_ATC 80 /* kHz */
|
||||
|
||||
typedef struct _CFO_TRACKING_ {
|
||||
bool bATCStatus;
|
||||
bool largeCFOHit;
|
||||
bool bAdjust;
|
||||
u8 CrystalCap;
|
||||
u8 DefXCap;
|
||||
int CFO_tail[2];
|
||||
int CFO_ave_pre;
|
||||
u32 packetCount;
|
||||
u32 packetCount_pre;
|
||||
|
||||
bool bForceXtalCap;
|
||||
bool bReset;
|
||||
} CFO_TRACKING, *PCFO_TRACKING;
|
||||
|
||||
void ODM_CfoTrackingReset(void *pDM_VOID
|
||||
);
|
||||
|
||||
void ODM_CfoTrackingInit(void *pDM_VOID);
|
||||
|
||||
void ODM_CfoTracking(void *pDM_VOID);
|
||||
|
||||
void ODM_ParsingCFO(void *pDM_VOID, void *pPktinfo_VOID, s8 *pcfotail);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,195 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODMDIG_H__
|
||||
#define __ODMDIG_H__
|
||||
|
||||
typedef struct _Dynamic_Initial_Gain_Threshold_ {
|
||||
bool bStopDIG;
|
||||
bool bPSDInProgress;
|
||||
|
||||
u8 Dig_Enable_Flag;
|
||||
u8 Dig_Ext_Port_Stage;
|
||||
|
||||
int RssiLowThresh;
|
||||
int RssiHighThresh;
|
||||
|
||||
u32 FALowThresh;
|
||||
u32 FAHighThresh;
|
||||
|
||||
u8 CurSTAConnectState;
|
||||
u8 PreSTAConnectState;
|
||||
u8 CurMultiSTAConnectState;
|
||||
|
||||
u8 PreIGValue;
|
||||
u8 CurIGValue;
|
||||
u8 BackupIGValue; /* MP DIG */
|
||||
u8 BT30_CurIGI;
|
||||
u8 IGIBackup;
|
||||
|
||||
s8 BackoffVal;
|
||||
s8 BackoffVal_range_max;
|
||||
s8 BackoffVal_range_min;
|
||||
u8 rx_gain_range_max;
|
||||
u8 rx_gain_range_min;
|
||||
u8 Rssi_val_min;
|
||||
|
||||
u8 PreCCK_CCAThres;
|
||||
u8 CurCCK_CCAThres;
|
||||
u8 PreCCKPDState;
|
||||
u8 CurCCKPDState;
|
||||
u8 CCKPDBackup;
|
||||
|
||||
u8 LargeFAHit;
|
||||
u8 ForbiddenIGI;
|
||||
u32 Recover_cnt;
|
||||
|
||||
u8 DIG_Dynamic_MIN_0;
|
||||
u8 DIG_Dynamic_MIN_1;
|
||||
bool bMediaConnect_0;
|
||||
bool bMediaConnect_1;
|
||||
|
||||
u32 AntDiv_RSSI_max;
|
||||
u32 RSSI_max;
|
||||
|
||||
u8 *pbP2pLinkInProgress;
|
||||
} DIG_T, *pDIG_T;
|
||||
|
||||
typedef struct false_ALARM_STATISTICS {
|
||||
u32 Cnt_Parity_Fail;
|
||||
u32 Cnt_Rate_Illegal;
|
||||
u32 Cnt_Crc8_fail;
|
||||
u32 Cnt_Mcs_fail;
|
||||
u32 Cnt_Ofdm_fail;
|
||||
u32 Cnt_Ofdm_fail_pre; /* For RTL8881A */
|
||||
u32 Cnt_Cck_fail;
|
||||
u32 Cnt_all;
|
||||
u32 Cnt_Fast_Fsync;
|
||||
u32 Cnt_SB_Search_fail;
|
||||
u32 Cnt_OFDM_CCA;
|
||||
u32 Cnt_CCK_CCA;
|
||||
u32 Cnt_CCA_all;
|
||||
u32 Cnt_BW_USC; /* Gary */
|
||||
u32 Cnt_BW_LSC; /* Gary */
|
||||
} false_ALARM_STATISTICS, *Pfalse_ALARM_STATISTICS;
|
||||
|
||||
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition {
|
||||
DIG_TYPE_THRESH_HIGH = 0,
|
||||
DIG_TYPE_THRESH_LOW = 1,
|
||||
DIG_TYPE_BACKOFF = 2,
|
||||
DIG_TYPE_RX_GAIN_MIN = 3,
|
||||
DIG_TYPE_RX_GAIN_MAX = 4,
|
||||
DIG_TYPE_ENABLE = 5,
|
||||
DIG_TYPE_DISABLE = 6,
|
||||
DIG_OP_TYPE_MAX
|
||||
} DM_DIG_OP_E;
|
||||
|
||||
typedef enum tag_ODM_PauseDIG_Type {
|
||||
ODM_PAUSE_DIG = BIT0,
|
||||
ODM_RESUME_DIG = BIT1
|
||||
} ODM_Pause_DIG_TYPE;
|
||||
|
||||
typedef enum tag_ODM_PauseCCKPD_Type {
|
||||
ODM_PAUSE_CCKPD = BIT0,
|
||||
ODM_RESUME_CCKPD = BIT1
|
||||
} ODM_Pause_CCKPD_TYPE;
|
||||
|
||||
#define DM_DIG_THRESH_HIGH 40
|
||||
#define DM_DIG_THRESH_LOW 35
|
||||
|
||||
#define DMfalseALARM_THRESH_LOW 400
|
||||
#define DMfalseALARM_THRESH_HIGH 1000
|
||||
|
||||
#define DM_DIG_MAX_NIC 0x3e
|
||||
#define DM_DIG_MIN_NIC 0x1e /* 0x22//0x1c */
|
||||
#define DM_DIG_MAX_OF_MIN_NIC 0x3e
|
||||
|
||||
#define DM_DIG_MAX_AP 0x3e
|
||||
#define DM_DIG_MIN_AP 0x1c
|
||||
#define DM_DIG_MAX_OF_MIN 0x2A /* 0x32 */
|
||||
#define DM_DIG_MIN_AP_DFS 0x20
|
||||
|
||||
#define DM_DIG_MAX_NIC_HP 0x46
|
||||
#define DM_DIG_MIN_NIC_HP 0x2e
|
||||
|
||||
#define DM_DIG_MAX_AP_HP 0x42
|
||||
#define DM_DIG_MIN_AP_HP 0x30
|
||||
|
||||
#define DM_DIG_FA_TH0 0x200/* 0x20 */
|
||||
|
||||
#define DM_DIG_FA_TH1 0x300
|
||||
#define DM_DIG_FA_TH2 0x400
|
||||
/* this is for 92d */
|
||||
#define DM_DIG_FA_TH0_92D 0x100
|
||||
#define DM_DIG_FA_TH1_92D 0x400
|
||||
#define DM_DIG_FA_TH2_92D 0x600
|
||||
|
||||
#define DM_DIG_BACKOFF_MAX 12
|
||||
#define DM_DIG_BACKOFF_MIN -4
|
||||
#define DM_DIG_BACKOFF_DEFAULT 10
|
||||
|
||||
#define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */
|
||||
#define DM_DIG_FA_TH1_LPS 15 /* 15 lps */
|
||||
#define DM_DIG_FA_TH2_LPS 30 /* 30 lps */
|
||||
#define RSSI_OFFSET_DIG 0x05
|
||||
|
||||
void odm_NHMCounterStatisticsInit(void *pDM_VOID);
|
||||
|
||||
void odm_NHMCounterStatistics(void *pDM_VOID);
|
||||
|
||||
void odm_NHMBBInit(void *pDM_VOID);
|
||||
|
||||
void odm_NHMBB(void *pDM_VOID);
|
||||
|
||||
void odm_NHMCounterStatisticsReset(void *pDM_VOID);
|
||||
|
||||
void odm_GetNHMCounterStatistics(void *pDM_VOID);
|
||||
|
||||
void odm_SearchPwdBLowerBound(void *pDM_VOID, u8 IGI_target);
|
||||
|
||||
void odm_AdaptivityInit(void *pDM_VOID);
|
||||
|
||||
void odm_Adaptivity(void *pDM_VOID, u8 IGI);
|
||||
|
||||
void ODM_Write_DIG(void *pDM_VOID, u8 CurrentIGI);
|
||||
|
||||
void odm_PauseDIG(void *pDM_VOID, ODM_Pause_DIG_TYPE PauseType, u8 IGIValue);
|
||||
|
||||
void odm_DIGInit(void *pDM_VOID);
|
||||
|
||||
void odm_DIG(void *pDM_VOID);
|
||||
|
||||
void odm_DIGbyRSSI_LPS(void *pDM_VOID);
|
||||
|
||||
void odm_FalseAlarmCounterStatistics(void *pDM_VOID);
|
||||
|
||||
void odm_FAThresholdCheck(
|
||||
void *pDM_VOID,
|
||||
bool bDFSBand,
|
||||
bool bPerformance,
|
||||
u32 RxTp,
|
||||
u32 TxTp,
|
||||
u32 *dm_FA_thres
|
||||
);
|
||||
|
||||
u8 odm_ForbiddenIGICheck(void *pDM_VOID, u8 DIG_Dynamic_MIN, u8 CurrentIGI);
|
||||
|
||||
bool odm_DigAbort(void *pDM_VOID);
|
||||
|
||||
void odm_CCKPacketDetectionThresh(void *pDM_VOID);
|
||||
|
||||
void ODM_Write_CCK_CCA_Thres(void *pDM_VOID, u8 CurCCK_CCAThres);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
void odm_DynamicBBPowerSavingInit(void *pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
|
||||
|
||||
pDM_PSTable->PreCCAState = CCA_MAX;
|
||||
pDM_PSTable->CurCCAState = CCA_MAX;
|
||||
pDM_PSTable->PreRFState = RF_MAX;
|
||||
pDM_PSTable->CurRFState = RF_MAX;
|
||||
pDM_PSTable->Rssi_val_min = 0;
|
||||
pDM_PSTable->initialize = 0;
|
||||
}
|
||||
|
||||
void ODM_RF_Saving(void *pDM_VOID, u8 bForceInNormal)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
|
||||
u8 Rssi_Up_bound = 30;
|
||||
u8 Rssi_Low_bound = 25;
|
||||
|
||||
if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
|
||||
Rssi_Up_bound = 50;
|
||||
Rssi_Low_bound = 45;
|
||||
}
|
||||
|
||||
if (pDM_PSTable->initialize == 0) {
|
||||
|
||||
pDM_PSTable->Reg874 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0x874, bMaskDWord)&0x1CC000)>>14;
|
||||
pDM_PSTable->RegC70 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xc70, bMaskDWord)&BIT3)>>3;
|
||||
pDM_PSTable->Reg85C = (PHY_QueryBBReg(pDM_Odm->Adapter, 0x85c, bMaskDWord)&0xFF000000)>>24;
|
||||
pDM_PSTable->RegA74 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xa74, bMaskDWord)&0xF000)>>12;
|
||||
/* Reg818 = PHY_QueryBBReg(padapter, 0x818, bMaskDWord); */
|
||||
pDM_PSTable->initialize = 1;
|
||||
}
|
||||
|
||||
if (!bForceInNormal) {
|
||||
if (pDM_Odm->RSSI_Min != 0xFF) {
|
||||
if (pDM_PSTable->PreRFState == RF_Normal) {
|
||||
if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
|
||||
pDM_PSTable->CurRFState = RF_Save;
|
||||
else
|
||||
pDM_PSTable->CurRFState = RF_Normal;
|
||||
} else {
|
||||
if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
|
||||
pDM_PSTable->CurRFState = RF_Normal;
|
||||
else
|
||||
pDM_PSTable->CurRFState = RF_Save;
|
||||
}
|
||||
} else
|
||||
pDM_PSTable->CurRFState = RF_MAX;
|
||||
} else
|
||||
pDM_PSTable->CurRFState = RF_Normal;
|
||||
|
||||
if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
|
||||
if (pDM_PSTable->CurRFState == RF_Save) {
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, 0); /* RegC70[3]= 1'b0 */
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]= 0x63 */
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]= 0x3 */
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x0); /* Reg818[28]= 1'b0 */
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x1); /* Reg818[28]= 1'b1 */
|
||||
} else {
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0x874, 0x1CC000, pDM_PSTable->Reg874);
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0xc70, BIT3, pDM_PSTable->RegC70);
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0xa74, 0xF000, pDM_PSTable->RegA74);
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, 0x818, BIT28, 0x0);
|
||||
}
|
||||
pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODMDYNAMICBBPOWERSAVING_H__
|
||||
#define __ODMDYNAMICBBPOWERSAVING_H__
|
||||
|
||||
typedef struct _Dynamic_Power_Saving_ {
|
||||
u8 PreCCAState;
|
||||
u8 CurCCAState;
|
||||
|
||||
u8 PreRFState;
|
||||
u8 CurRFState;
|
||||
|
||||
int Rssi_val_min;
|
||||
|
||||
u8 initialize;
|
||||
u32 Reg874, RegC70, Reg85C, RegA74;
|
||||
|
||||
} PS_T, *pPS_T;
|
||||
|
||||
#define dm_RF_Saving ODM_RF_Saving
|
||||
|
||||
void ODM_RF_Saving(void *pDM_VOID, u8 bForceInNormal);
|
||||
|
||||
void odm_DynamicBBPowerSavingInit(void *pDM_VOID);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
void odm_DynamicTxPowerInit(void *pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
struct adapter *Adapter = pDM_Odm->Adapter;
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
struct dm_priv *pdmpriv = &pHalData->dmpriv;
|
||||
|
||||
pdmpriv->bDynamicTxPowerEnable = false;
|
||||
|
||||
pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
|
||||
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODMDYNAMICTXPOWER_H__
|
||||
#define __ODMDYNAMICTXPOWER_H__
|
||||
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
|
||||
#define TX_POWER_NEAR_FIELD_THRESH_8812 60
|
||||
|
||||
#define TxHighPwrLevel_Normal 0
|
||||
#define TxHighPwrLevel_Level1 1
|
||||
#define TxHighPwrLevel_Level2 2
|
||||
#define TxHighPwrLevel_BT1 3
|
||||
#define TxHighPwrLevel_BT2 4
|
||||
#define TxHighPwrLevel_15 5
|
||||
#define TxHighPwrLevel_35 6
|
||||
#define TxHighPwrLevel_50 7
|
||||
#define TxHighPwrLevel_70 8
|
||||
#define TxHighPwrLevel_100 9
|
||||
|
||||
void odm_DynamicTxPowerInit(void *pDM_VOID);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
static u32 edca_setting_DL_GMode[HT_IOT_PEER_MAX] = {
|
||||
/*UNKNOWN, REALTEK_90, ALTEK_92SE BROADCOM, LINK ATHEROS,
|
||||
*CISCO, MERU, MARVELL, 92U_AP, SELF_AP
|
||||
*/
|
||||
0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322,
|
||||
0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b
|
||||
};
|
||||
|
||||
static u32 edca_setting_UL[HT_IOT_PEER_MAX] = {
|
||||
/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM, RALINK, ATHEROS,
|
||||
*CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx)
|
||||
*/
|
||||
0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322,
|
||||
0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
|
||||
|
||||
static u32 edca_setting_DL[HT_IOT_PEER_MAX] = {
|
||||
/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM, RALINK, ATHEROS,
|
||||
*CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)
|
||||
*/
|
||||
0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630,
|
||||
0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
|
||||
|
||||
void ODM_EdcaTurboInit(void *pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
struct adapter *Adapter = pDM_Odm->Adapter;
|
||||
|
||||
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
|
||||
pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
|
||||
Adapter->recvpriv.bIsAnyNonBEPkts = false;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
|
||||
("Orginial VO PARAM: 0x%x\n",
|
||||
rtw_read32(pDM_Odm->Adapter, ODM_EDCA_VO_PARAM)));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
|
||||
("Orginial VI PARAM: 0x%x\n",
|
||||
rtw_read32(pDM_Odm->Adapter, ODM_EDCA_VI_PARAM)));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
|
||||
("Orginial BE PARAM: 0x%x\n",
|
||||
rtw_read32(pDM_Odm->Adapter, ODM_EDCA_BE_PARAM)));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
|
||||
("Orginial BK PARAM: 0x%x\n",
|
||||
rtw_read32(pDM_Odm->Adapter, ODM_EDCA_BK_PARAM)));
|
||||
} /* ODM_InitEdcaTurbo */
|
||||
|
||||
void odm_EdcaTurboCheck(void *pDM_VOID)
|
||||
{
|
||||
/* In HW integration first stage, we provide 4 different handles to
|
||||
* operate at the same time. In stage2/3, we need to prove universal
|
||||
* interface and merge all HW dynamic mechanism.
|
||||
*/
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
|
||||
("odm_EdcaTurboCheck ========================>\n"));
|
||||
|
||||
if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
|
||||
return;
|
||||
|
||||
odm_EdcaTurboCheckCE(pDM_Odm);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD,
|
||||
("<========================odm_EdcaTurboCheck\n"));
|
||||
} /* odm_CheckEdcaTurbo */
|
||||
|
||||
void odm_EdcaTurboCheckCE(void *pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
struct adapter *Adapter = pDM_Odm->Adapter;
|
||||
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
|
||||
struct recv_priv *precvpriv = &(Adapter->recvpriv);
|
||||
struct registry_priv *pregpriv = &Adapter->registrypriv;
|
||||
struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv);
|
||||
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
|
||||
u32 EDCA_BE_UL = 0x5ea42b;
|
||||
u32 EDCA_BE_DL = 0x5ea42b;
|
||||
u32 iot_peer = 0;
|
||||
u8 wirelessmode = 0xFF; /* invalid value */
|
||||
u32 trafficIndex;
|
||||
u32 edca_param;
|
||||
u64 cur_tx_bytes = 0;
|
||||
u64 cur_rx_bytes = 0;
|
||||
u8 bbtchange = false;
|
||||
u8 biasonrx = false;
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
if (!pDM_Odm->bLinked) {
|
||||
precvpriv->bIsAnyNonBEPkts = false;
|
||||
return;
|
||||
}
|
||||
|
||||
if ((pregpriv->wifi_spec == 1)) {
|
||||
precvpriv->bIsAnyNonBEPkts = false;
|
||||
return;
|
||||
}
|
||||
|
||||
if (pDM_Odm->pwirelessmode)
|
||||
wirelessmode = *(pDM_Odm->pwirelessmode);
|
||||
|
||||
iot_peer = pmlmeinfo->assoc_AP_vendor;
|
||||
|
||||
if (iot_peer >= HT_IOT_PEER_MAX) {
|
||||
precvpriv->bIsAnyNonBEPkts = false;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Check if the status needs to be changed. */
|
||||
if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
|
||||
cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes;
|
||||
cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes;
|
||||
|
||||
/* traffic, TX or RX */
|
||||
if (biasonrx) {
|
||||
if (cur_tx_bytes > (cur_rx_bytes << 2)) {
|
||||
/* Uplink TP is present. */
|
||||
trafficIndex = UP_LINK;
|
||||
} else { /* Balance TP is present. */
|
||||
trafficIndex = DOWN_LINK;
|
||||
}
|
||||
} else {
|
||||
if (cur_rx_bytes > (cur_tx_bytes << 2)) {
|
||||
/* Downlink TP is present. */
|
||||
trafficIndex = DOWN_LINK;
|
||||
} else { /* Balance TP is present. */
|
||||
trafficIndex = UP_LINK;
|
||||
}
|
||||
}
|
||||
|
||||
/* 92D txop can't be set to 0x3e for cisco1250 */
|
||||
if ((iot_peer == HT_IOT_PEER_CISCO) &&
|
||||
(wirelessmode == ODM_WM_N24G)) {
|
||||
EDCA_BE_DL = edca_setting_DL[iot_peer];
|
||||
EDCA_BE_UL = edca_setting_UL[iot_peer];
|
||||
} else if ((iot_peer == HT_IOT_PEER_CISCO) &&
|
||||
((wirelessmode == ODM_WM_G) ||
|
||||
(wirelessmode == (ODM_WM_B | ODM_WM_G)) ||
|
||||
(wirelessmode == ODM_WM_A) ||
|
||||
(wirelessmode == ODM_WM_B))) {
|
||||
EDCA_BE_DL = edca_setting_DL_GMode[iot_peer];
|
||||
} else if ((iot_peer == HT_IOT_PEER_AIRGO) &&
|
||||
((wirelessmode == ODM_WM_G) ||
|
||||
(wirelessmode == ODM_WM_A))) {
|
||||
EDCA_BE_DL = 0xa630;
|
||||
} else if (iot_peer == HT_IOT_PEER_MARVELL) {
|
||||
EDCA_BE_DL = edca_setting_DL[iot_peer];
|
||||
EDCA_BE_UL = edca_setting_UL[iot_peer];
|
||||
} else if (iot_peer == HT_IOT_PEER_ATHEROS) {
|
||||
/* Set DL EDCA for Atheros peer to 0x3ea42b. */
|
||||
EDCA_BE_DL = edca_setting_DL[iot_peer];
|
||||
}
|
||||
|
||||
if (trafficIndex == DOWN_LINK)
|
||||
edca_param = EDCA_BE_DL;
|
||||
else
|
||||
edca_param = EDCA_BE_UL;
|
||||
|
||||
rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
|
||||
|
||||
pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
|
||||
|
||||
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
|
||||
} else {
|
||||
/* Turn Off EDCA turbo here. */
|
||||
/* Restore original EDCA according to the declaration of AP. */
|
||||
if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
|
||||
rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
|
||||
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODMEDCATURBOCHECK_H__
|
||||
#define __ODMEDCATURBOCHECK_H__
|
||||
|
||||
typedef struct _EDCA_TURBO_ {
|
||||
bool bCurrentTurboEDCA;
|
||||
bool bIsCurRDLState;
|
||||
|
||||
u32 prv_traffic_idx; /* edca turbo */
|
||||
} EDCA_T, *pEDCA_T;
|
||||
|
||||
void odm_EdcaTurboCheck(void *pDM_VOID);
|
||||
void ODM_EdcaTurboInit(void *pDM_VOID);
|
||||
|
||||
void odm_EdcaTurboCheckCE(void *pDM_VOID);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,535 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig_MP_##ic##txt(pDM_Odm))
|
||||
#define READ_AND_CONFIG READ_AND_CONFIG_MP
|
||||
#define GET_VERSION_MP(ic, txt) (ODM_GetVersion_MP_##ic##txt())
|
||||
#define GET_VERSION(ic, txt) (pDM_Odm->bIsMPChip?GET_VERSION_MP(ic, txt):GET_VERSION_TC(ic, txt))
|
||||
|
||||
static u8 odm_QueryRxPwrPercentage(s8 AntPower)
|
||||
{
|
||||
if ((AntPower <= -100) || (AntPower >= 20))
|
||||
return 0;
|
||||
else if (AntPower >= 0)
|
||||
return 100;
|
||||
else
|
||||
return (100+AntPower);
|
||||
|
||||
}
|
||||
|
||||
static s32 odm_SignalScaleMapping_92CSeries(PDM_ODM_T pDM_Odm, s32 CurrSig)
|
||||
{
|
||||
s32 RetSig = 0;
|
||||
|
||||
if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) {
|
||||
if (CurrSig >= 51 && CurrSig <= 100)
|
||||
RetSig = 100;
|
||||
else if (CurrSig >= 41 && CurrSig <= 50)
|
||||
RetSig = 80 + ((CurrSig - 40)*2);
|
||||
else if (CurrSig >= 31 && CurrSig <= 40)
|
||||
RetSig = 66 + (CurrSig - 30);
|
||||
else if (CurrSig >= 21 && CurrSig <= 30)
|
||||
RetSig = 54 + (CurrSig - 20);
|
||||
else if (CurrSig >= 10 && CurrSig <= 20)
|
||||
RetSig = 42 + (((CurrSig - 10) * 2) / 3);
|
||||
else if (CurrSig >= 5 && CurrSig <= 9)
|
||||
RetSig = 22 + (((CurrSig - 5) * 3) / 2);
|
||||
else if (CurrSig >= 1 && CurrSig <= 4)
|
||||
RetSig = 6 + (((CurrSig - 1) * 3) / 2);
|
||||
else
|
||||
RetSig = CurrSig;
|
||||
}
|
||||
|
||||
return RetSig;
|
||||
}
|
||||
|
||||
s32 odm_SignalScaleMapping(PDM_ODM_T pDM_Odm, s32 CurrSig)
|
||||
{
|
||||
return odm_SignalScaleMapping_92CSeries(pDM_Odm, CurrSig);
|
||||
}
|
||||
|
||||
static u8 odm_EVMdbToPercentage(s8 Value)
|
||||
{
|
||||
/* */
|
||||
/* -33dB~0dB to 0%~99% */
|
||||
/* */
|
||||
s8 ret_val;
|
||||
|
||||
ret_val = Value;
|
||||
ret_val /= 2;
|
||||
|
||||
/* DbgPrint("Value =%d\n", Value); */
|
||||
/* ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value =%d / %x\n", ret_val, ret_val)); */
|
||||
|
||||
if (ret_val >= 0)
|
||||
ret_val = 0;
|
||||
if (ret_val <= -33)
|
||||
ret_val = -33;
|
||||
|
||||
ret_val = 0 - ret_val;
|
||||
ret_val *= 3;
|
||||
|
||||
if (ret_val == 99)
|
||||
ret_val = 100;
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
static void odm_RxPhyStatus92CSeries_Parsing(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
PODM_PHY_INFO_T pPhyInfo,
|
||||
u8 *pPhyStatus,
|
||||
PODM_PACKET_INFO_T pPktinfo
|
||||
)
|
||||
{
|
||||
u8 i, Max_spatial_stream;
|
||||
s8 rx_pwr[4], rx_pwr_all = 0;
|
||||
u8 EVM, PWDB_ALL = 0, PWDB_ALL_BT;
|
||||
u8 RSSI, total_rssi = 0;
|
||||
bool isCCKrate = false;
|
||||
u8 rf_rx_num = 0;
|
||||
u8 cck_highpwr = 0;
|
||||
u8 LNA_idx, VGA_idx;
|
||||
PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus;
|
||||
|
||||
isCCKrate = (pPktinfo->DataRate <= DESC_RATE11M) ? true : false;
|
||||
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1;
|
||||
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1;
|
||||
|
||||
|
||||
if (isCCKrate) {
|
||||
u8 cck_agc_rpt;
|
||||
|
||||
pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++;
|
||||
/* */
|
||||
/* (1)Hardware does not provide RSSI for CCK */
|
||||
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
|
||||
/* */
|
||||
|
||||
/* if (pHalData->eRFPowerState == eRfOn) */
|
||||
cck_highpwr = pDM_Odm->bCckHighPower;
|
||||
/* else */
|
||||
/* cck_highpwr = false; */
|
||||
|
||||
cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ;
|
||||
|
||||
/* 2011.11.28 LukeLee: 88E use different LNA & VGA gain table */
|
||||
/* The RSSI formula should be modified according to the gain table */
|
||||
/* In 88E, cck_highpwr is always set to 1 */
|
||||
LNA_idx = ((cck_agc_rpt & 0xE0)>>5);
|
||||
VGA_idx = (cck_agc_rpt & 0x1F);
|
||||
rx_pwr_all = odm_CCKRSSI_8723B(LNA_idx, VGA_idx);
|
||||
PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
|
||||
if (PWDB_ALL > 100)
|
||||
PWDB_ALL = 100;
|
||||
|
||||
pPhyInfo->RxPWDBAll = PWDB_ALL;
|
||||
pPhyInfo->BTRxRSSIPercentage = PWDB_ALL;
|
||||
pPhyInfo->RecvSignalPower = rx_pwr_all;
|
||||
/* */
|
||||
/* (3) Get Signal Quality (EVM) */
|
||||
/* */
|
||||
/* if (pPktinfo->bPacketMatchBSSID) */
|
||||
{
|
||||
u8 SQ, SQ_rpt;
|
||||
|
||||
if (pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest)
|
||||
SQ = 100;
|
||||
else {
|
||||
SQ_rpt = pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all;
|
||||
|
||||
if (SQ_rpt > 64)
|
||||
SQ = 0;
|
||||
else if (SQ_rpt < 20)
|
||||
SQ = 100;
|
||||
else
|
||||
SQ = ((64-SQ_rpt) * 100) / 44;
|
||||
|
||||
}
|
||||
|
||||
/* DbgPrint("cck SQ = %d\n", SQ); */
|
||||
pPhyInfo->SignalQuality = SQ;
|
||||
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ;
|
||||
pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1;
|
||||
}
|
||||
} else { /* is OFDM rate */
|
||||
pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++;
|
||||
|
||||
/* */
|
||||
/* (1)Get RSSI for HT rate */
|
||||
/* */
|
||||
|
||||
for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) {
|
||||
/* 2008/01/30 MH we will judge RF RX path now. */
|
||||
if (pDM_Odm->RFPathRxEnable & BIT(i))
|
||||
rf_rx_num++;
|
||||
/* else */
|
||||
/* continue; */
|
||||
|
||||
rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain&0x3F)*2) - 110;
|
||||
|
||||
|
||||
pPhyInfo->RxPwr[i] = rx_pwr[i];
|
||||
|
||||
/* Translate DBM to percentage. */
|
||||
RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]);
|
||||
total_rssi += RSSI;
|
||||
/* RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR =%x RSSI =%d\n", i, rx_pwr[i], RSSI)); */
|
||||
|
||||
pPhyInfo->RxMIMOSignalStrength[i] = (u8) RSSI;
|
||||
|
||||
/* Get Rx snr value in DB */
|
||||
pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s32)(pPhyStaRpt->path_rxsnr[i]/2);
|
||||
}
|
||||
|
||||
|
||||
/* */
|
||||
/* (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) */
|
||||
/* */
|
||||
rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1)&0x7f)-110;
|
||||
|
||||
PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all);
|
||||
/* RT_DISP(FRX, RX_PHY_SS, ("PWDB_ALL =%d\n", PWDB_ALL)); */
|
||||
|
||||
pPhyInfo->RxPWDBAll = PWDB_ALL;
|
||||
/* ODM_RT_TRACE(pDM_Odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI =%d\n", pPhyInfo->RxPWDBAll)); */
|
||||
pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT;
|
||||
pPhyInfo->RxPower = rx_pwr_all;
|
||||
pPhyInfo->RecvSignalPower = rx_pwr_all;
|
||||
|
||||
{/* pMgntInfo->CustomerID != RT_CID_819x_Lenovo */
|
||||
/* */
|
||||
/* (3)EVM of HT rate */
|
||||
/* */
|
||||
if (pPktinfo->DataRate >= DESC_RATEMCS8 && pPktinfo->DataRate <= DESC_RATEMCS15)
|
||||
Max_spatial_stream = 2; /* both spatial stream make sense */
|
||||
else
|
||||
Max_spatial_stream = 1; /* only spatial stream 1 makes sense */
|
||||
|
||||
for (i = 0; i < Max_spatial_stream; i++) {
|
||||
/* Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment */
|
||||
/* fill most significant bit to "zero" when doing shifting operation which may change a negative */
|
||||
/* value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. */
|
||||
EVM = odm_EVMdbToPercentage((pPhyStaRpt->stream_rxevm[i])); /* dbm */
|
||||
|
||||
/* RT_DISP(FRX, RX_PHY_SQ, ("RXRATE =%x RXEVM =%x EVM =%s%d\n", */
|
||||
/* GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); */
|
||||
|
||||
/* if (pPktinfo->bPacketMatchBSSID) */
|
||||
{
|
||||
if (i == ODM_RF_PATH_A) /* Fill value in RFD, Get the first spatial stream only */
|
||||
pPhyInfo->SignalQuality = (u8)(EVM & 0xff);
|
||||
|
||||
pPhyInfo->RxMIMOSignalQuality[i] = (u8)(EVM & 0xff);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->path_cfotail);
|
||||
|
||||
}
|
||||
|
||||
/* UI BSS List signal strength(in percentage), make it good looking, from 0~100. */
|
||||
/* It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). */
|
||||
if (isCCKrate) {
|
||||
#ifdef CONFIG_SKIP_SIGNAL_SCALE_MAPPING
|
||||
pPhyInfo->SignalStrength = (u8)PWDB_ALL;
|
||||
#else
|
||||
pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/* PWDB_ALL; */
|
||||
#endif
|
||||
} else {
|
||||
if (rf_rx_num != 0) {
|
||||
#ifdef CONFIG_SKIP_SIGNAL_SCALE_MAPPING
|
||||
total_rssi /= rf_rx_num;
|
||||
pPhyInfo->SignalStrength = (u8)total_rssi;
|
||||
#else
|
||||
pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, total_rssi /= rf_rx_num));
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/* DbgPrint("isCCKrate = %d, pPhyInfo->RxPWDBAll = %d, pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a = 0x%x\n", */
|
||||
/* isCCKrate, pPhyInfo->RxPWDBAll, pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a); */
|
||||
}
|
||||
|
||||
static void odm_Process_RSSIForDM(
|
||||
PDM_ODM_T pDM_Odm, PODM_PHY_INFO_T pPhyInfo, PODM_PACKET_INFO_T pPktinfo
|
||||
)
|
||||
{
|
||||
|
||||
s32 UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK, UndecoratedSmoothedOFDM, RSSI_Ave;
|
||||
u8 isCCKrate = 0;
|
||||
u8 RSSI_max, RSSI_min, i;
|
||||
u32 OFDM_pkt = 0;
|
||||
u32 Weighting = 0;
|
||||
PSTA_INFO_T pEntry;
|
||||
|
||||
|
||||
if (pPktinfo->StationID == 0xFF)
|
||||
return;
|
||||
|
||||
pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID];
|
||||
|
||||
if (!IS_STA_VALID(pEntry))
|
||||
return;
|
||||
|
||||
if ((!pPktinfo->bPacketMatchBSSID))
|
||||
return;
|
||||
|
||||
if (pPktinfo->bPacketBeacon)
|
||||
pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++;
|
||||
|
||||
isCCKrate = ((pPktinfo->DataRate <= DESC_RATE11M)) ? true : false;
|
||||
pDM_Odm->RxRate = pPktinfo->DataRate;
|
||||
|
||||
/* Statistic for antenna/path diversity------------------ */
|
||||
if (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) {
|
||||
|
||||
}
|
||||
|
||||
/* Smart Antenna Debug Message------------------ */
|
||||
|
||||
UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK;
|
||||
UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM;
|
||||
UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB;
|
||||
|
||||
if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) {
|
||||
|
||||
if (!isCCKrate) { /* ofdm rate */
|
||||
if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0) {
|
||||
RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
|
||||
pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
|
||||
pDM_Odm->RSSI_B = 0;
|
||||
} else {
|
||||
/* DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d\n", */
|
||||
/* pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]); */
|
||||
pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
|
||||
pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B];
|
||||
|
||||
if (
|
||||
pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A] >
|
||||
pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]
|
||||
) {
|
||||
RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
|
||||
RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B];
|
||||
} else {
|
||||
RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B];
|
||||
RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A];
|
||||
}
|
||||
|
||||
if ((RSSI_max-RSSI_min) < 3)
|
||||
RSSI_Ave = RSSI_max;
|
||||
else if ((RSSI_max-RSSI_min) < 6)
|
||||
RSSI_Ave = RSSI_max - 1;
|
||||
else if ((RSSI_max-RSSI_min) < 10)
|
||||
RSSI_Ave = RSSI_max - 2;
|
||||
else
|
||||
RSSI_Ave = RSSI_max - 3;
|
||||
}
|
||||
|
||||
/* 1 Process OFDM RSSI */
|
||||
if (UndecoratedSmoothedOFDM <= 0) /* initialize */
|
||||
UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll;
|
||||
else {
|
||||
if (pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedOFDM) {
|
||||
UndecoratedSmoothedOFDM =
|
||||
((UndecoratedSmoothedOFDM*(Rx_Smooth_Factor-1)) +
|
||||
RSSI_Ave)/Rx_Smooth_Factor;
|
||||
UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1;
|
||||
} else {
|
||||
UndecoratedSmoothedOFDM =
|
||||
((UndecoratedSmoothedOFDM*(Rx_Smooth_Factor-1)) +
|
||||
RSSI_Ave)/Rx_Smooth_Factor;
|
||||
}
|
||||
}
|
||||
|
||||
pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0;
|
||||
|
||||
} else {
|
||||
RSSI_Ave = pPhyInfo->RxPWDBAll;
|
||||
pDM_Odm->RSSI_A = (u8) pPhyInfo->RxPWDBAll;
|
||||
pDM_Odm->RSSI_B = 0;
|
||||
|
||||
/* 1 Process CCK RSSI */
|
||||
if (UndecoratedSmoothedCCK <= 0) /* initialize */
|
||||
UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll;
|
||||
else {
|
||||
if (pPhyInfo->RxPWDBAll > (u32)UndecoratedSmoothedCCK) {
|
||||
UndecoratedSmoothedCCK =
|
||||
((UndecoratedSmoothedCCK*(Rx_Smooth_Factor-1)) +
|
||||
pPhyInfo->RxPWDBAll)/Rx_Smooth_Factor;
|
||||
UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1;
|
||||
} else {
|
||||
UndecoratedSmoothedCCK =
|
||||
((UndecoratedSmoothedCCK*(Rx_Smooth_Factor-1)) +
|
||||
pPhyInfo->RxPWDBAll)/Rx_Smooth_Factor;
|
||||
}
|
||||
}
|
||||
pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1;
|
||||
}
|
||||
|
||||
/* if (pEntry) */
|
||||
{
|
||||
/* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */
|
||||
if (pEntry->rssi_stat.ValidBit >= 64)
|
||||
pEntry->rssi_stat.ValidBit = 64;
|
||||
else
|
||||
pEntry->rssi_stat.ValidBit++;
|
||||
|
||||
for (i = 0; i < pEntry->rssi_stat.ValidBit; i++)
|
||||
OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0;
|
||||
|
||||
if (pEntry->rssi_stat.ValidBit == 64) {
|
||||
Weighting = ((OFDM_pkt<<4) > 64)?64:(OFDM_pkt<<4);
|
||||
UndecoratedSmoothedPWDB = (Weighting*UndecoratedSmoothedOFDM+(64-Weighting)*UndecoratedSmoothedCCK)>>6;
|
||||
} else {
|
||||
if (pEntry->rssi_stat.ValidBit != 0)
|
||||
UndecoratedSmoothedPWDB = (OFDM_pkt*UndecoratedSmoothedOFDM+(pEntry->rssi_stat.ValidBit-OFDM_pkt)*UndecoratedSmoothedCCK)/pEntry->rssi_stat.ValidBit;
|
||||
else
|
||||
UndecoratedSmoothedPWDB = 0;
|
||||
}
|
||||
|
||||
pEntry->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK;
|
||||
pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM;
|
||||
pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;
|
||||
|
||||
/* DbgPrint("OFDM_pkt =%d, Weighting =%d\n", OFDM_pkt, Weighting); */
|
||||
/* DbgPrint("UndecoratedSmoothedOFDM =%d, UndecoratedSmoothedPWDB =%d, UndecoratedSmoothedCCK =%d\n", */
|
||||
/* UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK); */
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* */
|
||||
/* Endianness before calling this API */
|
||||
/* */
|
||||
static void ODM_PhyStatusQuery_92CSeries(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
PODM_PHY_INFO_T pPhyInfo,
|
||||
u8 *pPhyStatus,
|
||||
PODM_PACKET_INFO_T pPktinfo
|
||||
)
|
||||
{
|
||||
|
||||
odm_RxPhyStatus92CSeries_Parsing(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo);
|
||||
|
||||
if (!pDM_Odm->RSSI_test)
|
||||
odm_Process_RSSIForDM(pDM_Odm, pPhyInfo, pPktinfo);
|
||||
}
|
||||
|
||||
void ODM_PhyStatusQuery(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
PODM_PHY_INFO_T pPhyInfo,
|
||||
u8 *pPhyStatus,
|
||||
PODM_PACKET_INFO_T pPktinfo
|
||||
)
|
||||
{
|
||||
|
||||
ODM_PhyStatusQuery_92CSeries(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo);
|
||||
}
|
||||
|
||||
/* */
|
||||
/* If you want to add a new IC, Please follow below template and generate a new one. */
|
||||
/* */
|
||||
/* */
|
||||
|
||||
HAL_STATUS ODM_ConfigRFWithHeaderFile(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
ODM_RF_Config_Type ConfigType,
|
||||
ODM_RF_RADIO_PATH_E eRFPath
|
||||
)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
|
||||
("===>ODM_ConfigRFWithHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip"));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
|
||||
("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n",
|
||||
pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType));
|
||||
|
||||
if (ConfigType == CONFIG_RF_RADIO)
|
||||
READ_AND_CONFIG(8723B, _RadioA);
|
||||
else if (ConfigType == CONFIG_RF_TXPWR_LMT)
|
||||
READ_AND_CONFIG(8723B, _TXPWR_LMT);
|
||||
|
||||
return HAL_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
HAL_STATUS ODM_ConfigRFWithTxPwrTrackHeaderFile(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
|
||||
("===>ODM_ConfigRFWithTxPwrTrackHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip"));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
|
||||
("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n",
|
||||
pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType));
|
||||
|
||||
if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO)
|
||||
READ_AND_CONFIG(8723B, _TxPowerTrack_SDIO);
|
||||
|
||||
return HAL_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
HAL_STATUS ODM_ConfigBBWithHeaderFile(
|
||||
PDM_ODM_T pDM_Odm, ODM_BB_Config_Type ConfigType
|
||||
)
|
||||
{
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
|
||||
("===>ODM_ConfigBBWithHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip"));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD,
|
||||
("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n",
|
||||
pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType));
|
||||
|
||||
if (ConfigType == CONFIG_BB_PHY_REG)
|
||||
READ_AND_CONFIG(8723B, _PHY_REG);
|
||||
else if (ConfigType == CONFIG_BB_AGC_TAB)
|
||||
READ_AND_CONFIG(8723B, _AGC_TAB);
|
||||
else if (ConfigType == CONFIG_BB_PHY_REG_PG)
|
||||
READ_AND_CONFIG(8723B, _PHY_REG_PG);
|
||||
|
||||
return HAL_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
HAL_STATUS ODM_ConfigMACWithHeaderFile(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
u8 result = HAL_STATUS_SUCCESS;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"===>ODM_ConfigMACWithHeaderFile (%s)\n",
|
||||
(pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip"
|
||||
)
|
||||
);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n",
|
||||
pDM_Odm->SupportPlatform,
|
||||
pDM_Odm->SupportInterface,
|
||||
pDM_Odm->BoardType
|
||||
)
|
||||
);
|
||||
|
||||
READ_AND_CONFIG(8723B, _MAC_REG);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
@ -0,0 +1,162 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __HALHWOUTSRC_H__
|
||||
#define __HALHWOUTSRC_H__
|
||||
|
||||
|
||||
/*--------------------------Define -------------------------------------------*/
|
||||
/* define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0) */
|
||||
#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
|
||||
sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
|
||||
#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
|
||||
sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
|
||||
|
||||
#define AGC_DIFF_CONFIG(ic, band)\
|
||||
do {\
|
||||
if (pDM_Odm->bIsMPChip)\
|
||||
AGC_DIFF_CONFIG_MP(ic, band);\
|
||||
else\
|
||||
AGC_DIFF_CONFIG_TC(ic, band);\
|
||||
} while (0)
|
||||
|
||||
|
||||
/* */
|
||||
/* structure and define */
|
||||
/* */
|
||||
|
||||
typedef struct _Phy_Rx_AGC_Info {
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 gain:7, trsw:1;
|
||||
#else
|
||||
u8 trsw:1, gain:7;
|
||||
#endif
|
||||
} PHY_RX_AGC_INFO_T, *pPHY_RX_AGC_INFO_T;
|
||||
|
||||
typedef struct _Phy_Status_Rpt_8192cd {
|
||||
PHY_RX_AGC_INFO_T path_agc[2];
|
||||
u8 ch_corr[2];
|
||||
u8 cck_sig_qual_ofdm_pwdb_all;
|
||||
u8 cck_agc_rpt_ofdm_cfosho_a;
|
||||
u8 cck_rpt_b_ofdm_cfosho_b;
|
||||
u8 rsvd_1;/* ch_corr_msb; */
|
||||
u8 noise_power_db_msb;
|
||||
s8 path_cfotail[2];
|
||||
u8 pcts_mask[2];
|
||||
s8 stream_rxevm[2];
|
||||
u8 path_rxsnr[2];
|
||||
u8 noise_power_db_lsb;
|
||||
u8 rsvd_2[3];
|
||||
u8 stream_csi[2];
|
||||
u8 stream_target_csi[2];
|
||||
s8 sig_evm;
|
||||
u8 rsvd_3;
|
||||
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
|
||||
u8 sgi_en:1;
|
||||
u8 rxsc:2;
|
||||
u8 idle_long:1;
|
||||
u8 r_ant_train_en:1;
|
||||
u8 ant_sel_b:1;
|
||||
u8 ant_sel:1;
|
||||
#else /* _BIG_ENDIAN_ */
|
||||
u8 ant_sel:1;
|
||||
u8 ant_sel_b:1;
|
||||
u8 r_ant_train_en:1;
|
||||
u8 idle_long:1;
|
||||
u8 rxsc:2;
|
||||
u8 sgi_en:1;
|
||||
u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
|
||||
#endif
|
||||
} PHY_STATUS_RPT_8192CD_T, *PPHY_STATUS_RPT_8192CD_T;
|
||||
|
||||
|
||||
typedef struct _Phy_Status_Rpt_8812 {
|
||||
/* 2012.05.24 LukeLee: This structure should take big/little endian in consideration later..... */
|
||||
|
||||
/* DWORD 0 */
|
||||
u8 gain_trsw[2];
|
||||
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
|
||||
u16 chl_num:10;
|
||||
u16 sub_chnl:4;
|
||||
u16 r_RFMOD:2;
|
||||
#else /* _BIG_ENDIAN_ */
|
||||
u16 r_RFMOD:2;
|
||||
u16 sub_chnl:4;
|
||||
u16 chl_num:10;
|
||||
#endif
|
||||
|
||||
/* DWORD 1 */
|
||||
u8 pwdb_all;
|
||||
u8 cfosho[4]; /* DW 1 byte 1 DW 2 byte 0 */
|
||||
|
||||
/* DWORD 2 */
|
||||
s8 cfotail[4]; /* DW 2 byte 1 DW 3 byte 0 */
|
||||
|
||||
/* DWORD 3 */
|
||||
s8 rxevm[2]; /* DW 3 byte 1 DW 3 byte 2 */
|
||||
s8 rxsnr[2]; /* DW 3 byte 3 DW 4 byte 0 */
|
||||
|
||||
/* DWORD 4 */
|
||||
u8 PCTS_MSK_RPT[2];
|
||||
u8 pdsnr[2]; /* DW 4 byte 3 DW 5 Byte 0 */
|
||||
|
||||
/* DWORD 5 */
|
||||
u8 csi_current[2];
|
||||
u8 rx_gain_c;
|
||||
|
||||
/* DWORD 6 */
|
||||
u8 rx_gain_d;
|
||||
s8 sigevm;
|
||||
u8 resvd_0;
|
||||
u8 antidx_anta:3;
|
||||
u8 antidx_antb:3;
|
||||
u8 resvd_1:2;
|
||||
} PHY_STATUS_RPT_8812_T, *PPHY_STATUS_RPT_8812_T;
|
||||
|
||||
|
||||
void ODM_PhyStatusQuery(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
PODM_PHY_INFO_T pPhyInfo,
|
||||
u8 *pPhyStatus,
|
||||
PODM_PACKET_INFO_T pPktinfo
|
||||
);
|
||||
|
||||
HAL_STATUS ODM_ConfigRFWithTxPwrTrackHeaderFile(PDM_ODM_T pDM_Odm);
|
||||
|
||||
HAL_STATUS ODM_ConfigRFWithHeaderFile(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
ODM_RF_Config_Type ConfigType,
|
||||
ODM_RF_RADIO_PATH_E eRFPath
|
||||
);
|
||||
|
||||
HAL_STATUS ODM_ConfigBBWithHeaderFile(
|
||||
PDM_ODM_T pDM_Odm, ODM_BB_Config_Type ConfigType
|
||||
);
|
||||
|
||||
HAL_STATUS ODM_ConfigMACWithHeaderFile(PDM_ODM_T pDM_Odm);
|
||||
|
||||
HAL_STATUS ODM_ConfigFWWithHeaderFile(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
ODM_FW_Config_Type ConfigType,
|
||||
u8 *pFirmware,
|
||||
u32 *pSize
|
||||
);
|
||||
|
||||
s32 odm_SignalScaleMapping(PDM_ODM_T pDM_Odm, s32 CurrSig);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
/* This function is for inband noise test utility only */
|
||||
/* To obtain the inband noise level(dbm), do the following. */
|
||||
/* 1. disable DIG and Power Saving */
|
||||
/* 2. Set initial gain = 0x1a */
|
||||
/* 3. Stop updating idle time pwer report (for driver read) */
|
||||
/* - 0x80c[25] */
|
||||
|
||||
#define Valid_Min -35
|
||||
#define Valid_Max 10
|
||||
#define ValidCnt 5
|
||||
|
||||
static s16 odm_InbandNoise_Monitor_NSeries(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u8 bPauseDIG,
|
||||
u8 IGIValue,
|
||||
u32 max_time
|
||||
)
|
||||
{
|
||||
u32 tmp4b;
|
||||
u8 max_rf_path = 0, rf_path;
|
||||
u8 reg_c50, reg_c58, valid_done = 0;
|
||||
struct noise_level noise_data;
|
||||
u32 start = 0, func_start = 0, func_end = 0;
|
||||
|
||||
func_start = jiffies;
|
||||
pDM_Odm->noise_level.noise_all = 0;
|
||||
|
||||
if ((pDM_Odm->RFType == ODM_1T2R) || (pDM_Odm->RFType == ODM_2T2R))
|
||||
max_rf_path = 2;
|
||||
else
|
||||
max_rf_path = 1;
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() ==>\n"));
|
||||
|
||||
memset(&noise_data, 0, sizeof(struct noise_level));
|
||||
|
||||
/* */
|
||||
/* Step 1. Disable DIG && Set initial gain. */
|
||||
/* */
|
||||
|
||||
if (bPauseDIG)
|
||||
odm_PauseDIG(pDM_Odm, ODM_PAUSE_DIG, IGIValue);
|
||||
/* */
|
||||
/* Step 2. Disable all power save for read registers */
|
||||
/* */
|
||||
/* dcmd_DebugControlPowerSave(padapter, PSDisable); */
|
||||
|
||||
/* */
|
||||
/* Step 3. Get noise power level */
|
||||
/* */
|
||||
start = jiffies;
|
||||
while (1) {
|
||||
|
||||
/* Stop updating idle time pwer report (for driver read) */
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 1);
|
||||
|
||||
/* Read Noise Floor Report */
|
||||
tmp4b = PHY_QueryBBReg(pDM_Odm->Adapter, 0x8f8, bMaskDWord);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b));
|
||||
|
||||
/* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XAAGCCore1, bMaskByte0, TestInitialGain); */
|
||||
/* if (max_rf_path == 2) */
|
||||
/* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBAGCCore1, bMaskByte0, TestInitialGain); */
|
||||
|
||||
/* update idle time pwer report per 5us */
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 0);
|
||||
|
||||
noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b&0xff);
|
||||
noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b&0xff00)>>8);
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
|
||||
noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B]));
|
||||
|
||||
for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
|
||||
noise_data.sval[rf_path] = (s8)noise_data.value[rf_path];
|
||||
noise_data.sval[rf_path] /= 2;
|
||||
}
|
||||
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("sval_a = %d, sval_b = %d\n",
|
||||
noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B]));
|
||||
/* mdelay(10); */
|
||||
/* msleep(10); */
|
||||
|
||||
for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
|
||||
if ((noise_data.valid_cnt[rf_path] < ValidCnt) && (noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min)) {
|
||||
noise_data.valid_cnt[rf_path]++;
|
||||
noise_data.sum[rf_path] += noise_data.sval[rf_path];
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RF_Path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path]));
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", noise_data.sum[rf_path]));
|
||||
if (noise_data.valid_cnt[rf_path] == ValidCnt) {
|
||||
valid_done++;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, RF_Path:%d , sum = %d\n", rf_path, noise_data.sum[rf_path]));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* printk("####### valid_done:%d #############\n", valid_done); */
|
||||
if ((valid_done == max_rf_path) || (jiffies_to_msecs(jiffies - start) > max_time)) {
|
||||
for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
|
||||
/* printk("%s PATH_%d - sum = %d, valid_cnt = %d\n", __func__, rf_path, noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]); */
|
||||
if (noise_data.valid_cnt[rf_path])
|
||||
noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path];
|
||||
else
|
||||
noise_data.sum[rf_path] = 0;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
reg_c50 = (s32)PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XAAGCCore1, bMaskByte0);
|
||||
reg_c50 &= ~BIT7;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", rOFDM0_XAAGCCore1, reg_c50, reg_c50));
|
||||
pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = -110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A];
|
||||
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A];
|
||||
|
||||
if (max_rf_path == 2) {
|
||||
reg_c58 = (s32)PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBAGCCore1, bMaskByte0);
|
||||
reg_c58 &= ~BIT7;
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", rOFDM0_XBAGCCore1, reg_c58, reg_c58));
|
||||
pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = -110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B];
|
||||
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B];
|
||||
}
|
||||
pDM_Odm->noise_level.noise_all /= max_rf_path;
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_COMMON,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"noise_a = %d, noise_b = %d\n",
|
||||
pDM_Odm->noise_level.noise[ODM_RF_PATH_A],
|
||||
pDM_Odm->noise_level.noise[ODM_RF_PATH_B]
|
||||
)
|
||||
);
|
||||
|
||||
/* */
|
||||
/* Step 4. Recover the Dig */
|
||||
/* */
|
||||
if (bPauseDIG)
|
||||
odm_PauseDIG(pDM_Odm, ODM_RESUME_DIG, IGIValue);
|
||||
|
||||
func_end = jiffies_to_msecs(jiffies - func_start);
|
||||
/* printk("%s noise_a = %d, noise_b = %d noise_all:%d (%d ms)\n", __func__, */
|
||||
/* pDM_Odm->noise_level.noise[ODM_RF_PATH_A], */
|
||||
/* pDM_Odm->noise_level.noise[ODM_RF_PATH_B], */
|
||||
/* pDM_Odm->noise_level.noise_all, func_end); */
|
||||
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n"));
|
||||
return pDM_Odm->noise_level.noise_all;
|
||||
|
||||
}
|
||||
|
||||
s16 ODM_InbandNoise_Monitor(void *pDM_VOID, u8 bPauseDIG, u8 IGIValue, u32 max_time)
|
||||
{
|
||||
return odm_InbandNoise_Monitor_NSeries(pDM_VOID, bPauseDIG, IGIValue, max_time);
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __ODMNOISEMONITOR_H__
|
||||
#define __ODMNOISEMONITOR_H__
|
||||
|
||||
#define ODM_MAX_CHANNEL_NUM 38/* 14+24 */
|
||||
struct noise_level {
|
||||
/* u8 value_a, value_b; */
|
||||
u8 value[MAX_RF_PATH];
|
||||
/* s8 sval_a, sval_b; */
|
||||
s8 sval[MAX_RF_PATH];
|
||||
|
||||
/* s32 noise_a = 0, noise_b = 0, sum_a = 0, sum_b = 0; */
|
||||
/* s32 noise[ODM_RF_PATH_MAX]; */
|
||||
s32 sum[MAX_RF_PATH];
|
||||
/* u8 valid_cnt_a = 0, valid_cnt_b = 0, */
|
||||
u8 valid[MAX_RF_PATH];
|
||||
u8 valid_cnt[MAX_RF_PATH];
|
||||
|
||||
};
|
||||
|
||||
|
||||
typedef struct _ODM_NOISE_MONITOR_ {
|
||||
s8 noise[MAX_RF_PATH];
|
||||
s16 noise_all;
|
||||
} ODM_NOISE_MONITOR;
|
||||
|
||||
s16 ODM_InbandNoise_Monitor(
|
||||
void *pDM_VOID,
|
||||
u8 bPauseDIG,
|
||||
u8 IGIValue,
|
||||
u32 max_time
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
void odm_PathDiversityInit(void *pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
if (!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_PATH_DIV,
|
||||
ODM_DBG_LOUD,
|
||||
("Return: Not Support PathDiv\n")
|
||||
);
|
||||
}
|
||||
|
||||
void odm_PathDiversity(void *pDM_VOID)
|
||||
{
|
||||
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
|
||||
|
||||
if (!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_PATH_DIV,
|
||||
ODM_DBG_LOUD,
|
||||
("Return: Not Support PathDiv\n")
|
||||
);
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODMPATHDIV_H__
|
||||
#define __ODMPATHDIV_H__
|
||||
|
||||
void
|
||||
odm_PathDiversityInit(
|
||||
void *pDM_VOID
|
||||
);
|
||||
|
||||
void
|
||||
odm_PathDiversity(
|
||||
void *pDM_VOID
|
||||
);
|
||||
|
||||
#endif /* ifndef __ODMPATHDIV_H__ */
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
s8 odm_CCKRSSI_8723B(u8 LNA_idx, u8 VGA_idx)
|
||||
{
|
||||
s8 rx_pwr_all = 0x00;
|
||||
|
||||
switch (LNA_idx) {
|
||||
/* 46 53 73 95 201301231630 */
|
||||
/* 46 53 77 99 201301241630 */
|
||||
|
||||
case 6:
|
||||
rx_pwr_all = -34 - (2 * VGA_idx);
|
||||
break;
|
||||
case 4:
|
||||
rx_pwr_all = -14 - (2 * VGA_idx);
|
||||
break;
|
||||
case 1:
|
||||
rx_pwr_all = 6 - (2 * VGA_idx);
|
||||
break;
|
||||
case 0:
|
||||
rx_pwr_all = 16 - (2 * VGA_idx);
|
||||
break;
|
||||
default:
|
||||
/* rx_pwr_all = -53+(2*(31-VGA_idx)); */
|
||||
/* DbgPrint("wrong LNA index\n"); */
|
||||
break;
|
||||
|
||||
}
|
||||
return rx_pwr_all;
|
||||
}
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __ODM_RTL8723B_H__
|
||||
#define __ODM_RTL8723B_H__
|
||||
|
||||
#define DM_DIG_MIN_NIC_8723 0x1C
|
||||
|
||||
s8 odm_CCKRSSI_8723B(u8 LNA_idx, u8 VGA_idx);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
void odm_ConfigRFReg_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u32 Addr,
|
||||
u32 Data,
|
||||
ODM_RF_RADIO_PATH_E RF_PATH,
|
||||
u32 RegAddr
|
||||
)
|
||||
{
|
||||
if (Addr == 0xfe || Addr == 0xffe)
|
||||
msleep(50);
|
||||
else {
|
||||
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
|
||||
/* Add 1us delay between BB/RF register setting. */
|
||||
udelay(1);
|
||||
|
||||
/* For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25. */
|
||||
if (Addr == 0xb6) {
|
||||
u32 getvalue = 0;
|
||||
u8 count = 0;
|
||||
|
||||
getvalue = PHY_QueryRFReg(
|
||||
pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
|
||||
);
|
||||
|
||||
udelay(1);
|
||||
|
||||
while ((getvalue>>8) != (Data>>8)) {
|
||||
count++;
|
||||
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
|
||||
udelay(1);
|
||||
getvalue = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
"===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n",
|
||||
getvalue,
|
||||
Data,
|
||||
count
|
||||
)
|
||||
);
|
||||
if (count > 5)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (Addr == 0xb2) {
|
||||
u32 getvalue = 0;
|
||||
u8 count = 0;
|
||||
|
||||
getvalue = PHY_QueryRFReg(
|
||||
pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
|
||||
);
|
||||
|
||||
udelay(1);
|
||||
|
||||
while (getvalue != Data) {
|
||||
count++;
|
||||
PHY_SetRFReg(
|
||||
pDM_Odm->Adapter,
|
||||
RF_PATH,
|
||||
RegAddr,
|
||||
bRFRegOffsetMask,
|
||||
Data
|
||||
);
|
||||
udelay(1);
|
||||
/* Do LCK againg */
|
||||
PHY_SetRFReg(
|
||||
pDM_Odm->Adapter,
|
||||
RF_PATH,
|
||||
0x18,
|
||||
bRFRegOffsetMask,
|
||||
0x0fc07
|
||||
);
|
||||
udelay(1);
|
||||
getvalue = PHY_QueryRFReg(
|
||||
pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
|
||||
);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
"===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n",
|
||||
getvalue,
|
||||
Data,
|
||||
count
|
||||
)
|
||||
);
|
||||
|
||||
if (count > 5)
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void odm_ConfigRF_RadioA_8723B(PDM_ODM_T pDM_Odm, u32 Addr, u32 Data)
|
||||
{
|
||||
u32 content = 0x1000; /* RF_Content: radioa_txt */
|
||||
u32 maskforPhySet = (u32)(content&0xE000);
|
||||
|
||||
odm_ConfigRFReg_8723B(
|
||||
pDM_Odm,
|
||||
Addr,
|
||||
Data,
|
||||
ODM_RF_PATH_A,
|
||||
Addr|maskforPhySet
|
||||
);
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
"===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n",
|
||||
Addr,
|
||||
Data
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
void odm_ConfigMAC_8723B(PDM_ODM_T pDM_Odm, u32 Addr, u8 Data)
|
||||
{
|
||||
rtw_write8(pDM_Odm->Adapter, Addr, Data);
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
"===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n",
|
||||
Addr,
|
||||
Data
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
void odm_ConfigBB_AGC_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u32 Addr,
|
||||
u32 Bitmask,
|
||||
u32 Data
|
||||
)
|
||||
{
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
|
||||
/* Add 1us delay between BB/RF register setting. */
|
||||
udelay(1);
|
||||
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_TRACE,
|
||||
(
|
||||
"===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n",
|
||||
Addr,
|
||||
Data
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
void odm_ConfigBB_PHY_REG_PG_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u32 Band,
|
||||
u32 RfPath,
|
||||
u32 TxNum,
|
||||
u32 Addr,
|
||||
u32 Bitmask,
|
||||
u32 Data
|
||||
)
|
||||
{
|
||||
if (Addr == 0xfe || Addr == 0xffe)
|
||||
msleep(50);
|
||||
else {
|
||||
PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
|
||||
}
|
||||
ODM_RT_TRACE(
|
||||
pDM_Odm,
|
||||
ODM_COMP_INIT,
|
||||
ODM_DBG_LOUD,
|
||||
(
|
||||
"===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n",
|
||||
Addr,
|
||||
Bitmask,
|
||||
Data
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
void odm_ConfigBB_PHY_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u32 Addr,
|
||||
u32 Bitmask,
|
||||
u32 Data
|
||||
)
|
||||
{
|
||||
if (Addr == 0xfe)
|
||||
msleep(50);
|
||||
else if (Addr == 0xfd)
|
||||
mdelay(5);
|
||||
else if (Addr == 0xfc)
|
||||
mdelay(1);
|
||||
else if (Addr == 0xfb)
|
||||
udelay(50);
|
||||
else if (Addr == 0xfa)
|
||||
udelay(5);
|
||||
else if (Addr == 0xf9)
|
||||
udelay(1);
|
||||
else {
|
||||
PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
|
||||
}
|
||||
|
||||
/* Add 1us delay between BB/RF register setting. */
|
||||
udelay(1);
|
||||
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
|
||||
}
|
||||
|
||||
void odm_ConfigBB_TXPWR_LMT_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u8 *Regulation,
|
||||
u8 *Band,
|
||||
u8 *Bandwidth,
|
||||
u8 *RateSection,
|
||||
u8 *RfPath,
|
||||
u8 *Channel,
|
||||
u8 *PowerLimit
|
||||
)
|
||||
{
|
||||
PHY_SetTxPowerLimit(
|
||||
pDM_Odm->Adapter,
|
||||
Regulation,
|
||||
Band,
|
||||
Bandwidth,
|
||||
RateSection,
|
||||
RfPath,
|
||||
Channel,
|
||||
PowerLimit
|
||||
);
|
||||
}
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __INC_ODM_REGCONFIG_H_8723B
|
||||
#define __INC_ODM_REGCONFIG_H_8723B
|
||||
|
||||
void odm_ConfigRFReg_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u32 Addr,
|
||||
u32 Data,
|
||||
ODM_RF_RADIO_PATH_E RF_PATH,
|
||||
u32 RegAddr
|
||||
);
|
||||
|
||||
void odm_ConfigRF_RadioA_8723B(PDM_ODM_T pDM_Odm, u32 Addr, u32 Data);
|
||||
|
||||
void odm_ConfigMAC_8723B(PDM_ODM_T pDM_Odm, u32 Addr, u8 Data);
|
||||
|
||||
void odm_ConfigBB_AGC_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u32 Addr,
|
||||
u32 Bitmask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
void odm_ConfigBB_PHY_REG_PG_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u32 Band,
|
||||
u32 RfPath,
|
||||
u32 TxNum,
|
||||
u32 Addr,
|
||||
u32 Bitmask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
void odm_ConfigBB_PHY_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u32 Addr,
|
||||
u32 Bitmask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
void odm_ConfigBB_TXPWR_LMT_8723B(
|
||||
PDM_ODM_T pDM_Odm,
|
||||
u8 *Regulation,
|
||||
u8 *Band,
|
||||
u8 *Bandwidth,
|
||||
u8 *RateSection,
|
||||
u8 *RfPath,
|
||||
u8 *Channel,
|
||||
u8 *PowerLimit
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODM_REGDEFINE11N_H__
|
||||
#define __ODM_REGDEFINE11N_H__
|
||||
|
||||
|
||||
/* 2 RF REG LIST */
|
||||
#define ODM_REG_RF_MODE_11N 0x00
|
||||
#define ODM_REG_RF_0B_11N 0x0B
|
||||
#define ODM_REG_CHNBW_11N 0x18
|
||||
#define ODM_REG_T_METER_11N 0x24
|
||||
#define ODM_REG_RF_25_11N 0x25
|
||||
#define ODM_REG_RF_26_11N 0x26
|
||||
#define ODM_REG_RF_27_11N 0x27
|
||||
#define ODM_REG_RF_2B_11N 0x2B
|
||||
#define ODM_REG_RF_2C_11N 0x2C
|
||||
#define ODM_REG_RXRF_A3_11N 0x3C
|
||||
#define ODM_REG_T_METER_92D_11N 0x42
|
||||
#define ODM_REG_T_METER_88E_11N 0x42
|
||||
|
||||
/* 2 BB REG LIST */
|
||||
/* PAGE 8 */
|
||||
#define ODM_REG_BB_CTRL_11N 0x800
|
||||
#define ODM_REG_RF_PIN_11N 0x804
|
||||
#define ODM_REG_PSD_CTRL_11N 0x808
|
||||
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
|
||||
#define ODM_REG_BB_PWR_SAV5_11N 0x818
|
||||
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
|
||||
#define ODM_REG_RX_DEFUALT_A_11N 0x858
|
||||
#define ODM_REG_RX_DEFUALT_B_11N 0x85A
|
||||
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
|
||||
#define ODM_REG_ANTSEL_CTRL_11N 0x860
|
||||
#define ODM_REG_RX_ANT_CTRL_11N 0x864
|
||||
#define ODM_REG_PIN_CTRL_11N 0x870
|
||||
#define ODM_REG_BB_PWR_SAV1_11N 0x874
|
||||
#define ODM_REG_ANTSEL_PATH_11N 0x878
|
||||
#define ODM_REG_BB_3WIRE_11N 0x88C
|
||||
#define ODM_REG_SC_CNT_11N 0x8C4
|
||||
#define ODM_REG_PSD_DATA_11N 0x8B4
|
||||
#define ODM_REG_PSD_DATA_11N 0x8B4
|
||||
#define ODM_REG_NHM_TIMER_11N 0x894
|
||||
#define ODM_REG_NHM_TH9_TH10_11N 0x890
|
||||
#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
|
||||
#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
|
||||
#define ODM_REG_NHM_CNT_11N 0x8d8
|
||||
/* PAGE 9 */
|
||||
#define ODM_REG_DBG_RPT_11N 0x908
|
||||
#define ODM_REG_ANT_MAPPING1_11N 0x914
|
||||
#define ODM_REG_ANT_MAPPING2_11N 0x918
|
||||
/* PAGE A */
|
||||
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
|
||||
#define ODM_REG_CCK_CCA_11N 0xA0A
|
||||
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
|
||||
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
|
||||
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
|
||||
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
|
||||
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
|
||||
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
|
||||
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
|
||||
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
|
||||
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
|
||||
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
|
||||
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
|
||||
#define ODM_REG_CCK_FA_RST_11N 0xA2C
|
||||
#define ODM_REG_CCK_FA_MSB_11N 0xA58
|
||||
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
|
||||
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
|
||||
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
|
||||
/* PAGE B */
|
||||
#define ODM_REG_LNA_SWITCH_11N 0xB2C
|
||||
#define ODM_REG_PATH_SWITCH_11N 0xB30
|
||||
#define ODM_REG_RSSI_CTRL_11N 0xB38
|
||||
#define ODM_REG_CONFIG_ANTA_11N 0xB68
|
||||
#define ODM_REG_RSSI_BT_11N 0xB9C
|
||||
/* PAGE C */
|
||||
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
|
||||
#define ODM_REG_BB_RX_PATH_11N 0xC04
|
||||
#define ODM_REG_TRMUX_11N 0xC08
|
||||
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
|
||||
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
|
||||
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
|
||||
#define ODM_REG_IGI_A_11N 0xC50
|
||||
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
|
||||
#define ODM_REG_IGI_B_11N 0xC58
|
||||
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
|
||||
#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
|
||||
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
|
||||
#define ODM_REG_RX_OFF_11N 0xC7C
|
||||
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
|
||||
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
|
||||
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
|
||||
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
|
||||
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
|
||||
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
|
||||
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
|
||||
/* PAGE D */
|
||||
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
|
||||
#define ODM_REG_BB_ATC_11N 0xD2C
|
||||
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
|
||||
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
|
||||
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
|
||||
#define ODM_REG_RPT_11N 0xDF4
|
||||
/* PAGE E */
|
||||
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
|
||||
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
|
||||
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
|
||||
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
|
||||
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
|
||||
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
|
||||
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
|
||||
#define ODM_REG_FPGA0_IQK_11N 0xE28
|
||||
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
|
||||
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
|
||||
#define ODM_REG_TXIQK_PI_A_11N 0xE38
|
||||
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
|
||||
#define ODM_REG_TXIQK_11N 0xE40
|
||||
#define ODM_REG_RXIQK_11N 0xE44
|
||||
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
|
||||
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
|
||||
#define ODM_REG_BLUETOOTH_11N 0xE6C
|
||||
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
|
||||
#define ODM_REG_TX_CCK_RFON_11N 0xE74
|
||||
#define ODM_REG_TX_CCK_BBON_11N 0xE78
|
||||
#define ODM_REG_OFDM_RFON_11N 0xE7C
|
||||
#define ODM_REG_OFDM_BBON_11N 0xE80
|
||||
#define ODM_REG_TX2RX_11N 0xE84
|
||||
#define ODM_REG_TX2TX_11N 0xE88
|
||||
#define ODM_REG_RX_CCK_11N 0xE8C
|
||||
#define ODM_REG_RX_OFDM_11N 0xED0
|
||||
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
|
||||
#define ODM_REG_RX2RX_11N 0xED8
|
||||
#define ODM_REG_STANDBY_11N 0xEDC
|
||||
#define ODM_REG_SLEEP_11N 0xEE0
|
||||
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
|
||||
#define ODM_REG_IGI_C_11N 0xF84
|
||||
#define ODM_REG_IGI_D_11N 0xF88
|
||||
|
||||
/* 2 MAC REG LIST */
|
||||
#define ODM_REG_BB_RST_11N 0x02
|
||||
#define ODM_REG_ANTSEL_PIN_11N 0x4C
|
||||
#define ODM_REG_EARLY_MODE_11N 0x4D0
|
||||
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
|
||||
#define ODM_REG_EDCA_VO_11N 0x500
|
||||
#define ODM_REG_EDCA_VI_11N 0x504
|
||||
#define ODM_REG_EDCA_BE_11N 0x508
|
||||
#define ODM_REG_EDCA_BK_11N 0x50C
|
||||
#define ODM_REG_TXPAUSE_11N 0x522
|
||||
#define ODM_REG_RESP_TX_11N 0x6D8
|
||||
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
|
||||
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
|
||||
|
||||
|
||||
/* DIG Related */
|
||||
#define ODM_BIT_IGI_11N 0x0000007F
|
||||
#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9
|
||||
#define ODM_BIT_BB_RX_PATH_11N 0xF
|
||||
#define ODM_BIT_BB_ATC_11N BIT11
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "odm_precomp.h"
|
||||
|
||||
void ODM_InitDebugSetting(PDM_ODM_T pDM_Odm)
|
||||
{
|
||||
pDM_Odm->DebugLevel = ODM_DBG_LOUD;
|
||||
|
||||
pDM_Odm->DebugComponents =
|
||||
/* BB Functions */
|
||||
/* ODM_COMP_DIG | */
|
||||
/* ODM_COMP_RA_MASK | */
|
||||
/* ODM_COMP_DYNAMIC_TXPWR | */
|
||||
/* ODM_COMP_FA_CNT | */
|
||||
/* ODM_COMP_RSSI_MONITOR | */
|
||||
/* ODM_COMP_CCK_PD | */
|
||||
/* ODM_COMP_ANT_DIV | */
|
||||
/* ODM_COMP_PWR_SAVE | */
|
||||
/* ODM_COMP_PWR_TRAIN | */
|
||||
/* ODM_COMP_RATE_ADAPTIVE | */
|
||||
/* ODM_COMP_PATH_DIV | */
|
||||
/* ODM_COMP_DYNAMIC_PRICCA | */
|
||||
/* ODM_COMP_RXHP | */
|
||||
/* ODM_COMP_MP | */
|
||||
/* ODM_COMP_CFO_TRACKING | */
|
||||
|
||||
/* MAC Functions */
|
||||
/* ODM_COMP_EDCA_TURBO | */
|
||||
/* ODM_COMP_EARLY_MODE | */
|
||||
/* RF Functions */
|
||||
/* ODM_COMP_TX_PWR_TRACK | */
|
||||
/* ODM_COMP_RX_GAIN_TRACK | */
|
||||
/* ODM_COMP_CALIBRATION | */
|
||||
/* Common */
|
||||
/* ODM_COMP_COMMON | */
|
||||
/* ODM_COMP_INIT | */
|
||||
/* ODM_COMP_PSD | */
|
||||
0;
|
||||
}
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODM_DBG_H__
|
||||
#define __ODM_DBG_H__
|
||||
|
||||
|
||||
/* */
|
||||
/* Define the debug levels */
|
||||
/* */
|
||||
/* 1. DBG_TRACE and DBG_LOUD are used for normal cases. */
|
||||
/* So that, they can help SW engineer to develope or trace states changed */
|
||||
/* and also help HW enginner to trace every operation to and from HW, */
|
||||
/* e.g IO, Tx, Rx. */
|
||||
/* */
|
||||
/* 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, */
|
||||
/* which help us to debug SW or HW. */
|
||||
/* */
|
||||
/* */
|
||||
/* */
|
||||
/* Never used in a call to ODM_RT_TRACE()! */
|
||||
/* */
|
||||
#define ODM_DBG_OFF 1
|
||||
|
||||
/* */
|
||||
/* Fatal bug. */
|
||||
/* For example, Tx/Rx/IO locked up, OS hangs, memory access violation, */
|
||||
/* resource allocation failed, unexpected HW behavior, HW BUG and so on. */
|
||||
/* */
|
||||
#define ODM_DBG_SERIOUS 2
|
||||
|
||||
/* */
|
||||
/* Abnormal, rare, or unexpeted cases. */
|
||||
/* For example, */
|
||||
/* IRP/Packet/OID canceled, */
|
||||
/* device suprisely unremoved and so on. */
|
||||
/* */
|
||||
#define ODM_DBG_WARNING 3
|
||||
|
||||
/* */
|
||||
/* Normal case with useful information about current SW or HW state. */
|
||||
/* For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, */
|
||||
/* SW protocol state change, dynamic mechanism state change and so on. */
|
||||
/* */
|
||||
#define ODM_DBG_LOUD 4
|
||||
|
||||
/* */
|
||||
/* Normal case with detail execution flow or information. */
|
||||
/* */
|
||||
#define ODM_DBG_TRACE 5
|
||||
|
||||
/* */
|
||||
/* Define the tracing components */
|
||||
/* */
|
||||
/* */
|
||||
/* BB Functions */
|
||||
#define ODM_COMP_DIG BIT0
|
||||
#define ODM_COMP_RA_MASK BIT1
|
||||
#define ODM_COMP_DYNAMIC_TXPWR BIT2
|
||||
#define ODM_COMP_FA_CNT BIT3
|
||||
#define ODM_COMP_RSSI_MONITOR BIT4
|
||||
#define ODM_COMP_CCK_PD BIT5
|
||||
#define ODM_COMP_ANT_DIV BIT6
|
||||
#define ODM_COMP_PWR_SAVE BIT7
|
||||
#define ODM_COMP_PWR_TRAIN BIT8
|
||||
#define ODM_COMP_RATE_ADAPTIVE BIT9
|
||||
#define ODM_COMP_PATH_DIV BIT10
|
||||
#define ODM_COMP_PSD BIT11
|
||||
#define ODM_COMP_DYNAMIC_PRICCA BIT12
|
||||
#define ODM_COMP_RXHP BIT13
|
||||
#define ODM_COMP_MP BIT14
|
||||
#define ODM_COMP_CFO_TRACKING BIT15
|
||||
/* MAC Functions */
|
||||
#define ODM_COMP_EDCA_TURBO BIT16
|
||||
#define ODM_COMP_EARLY_MODE BIT17
|
||||
/* RF Functions */
|
||||
#define ODM_COMP_TX_PWR_TRACK BIT24
|
||||
#define ODM_COMP_RX_GAIN_TRACK BIT25
|
||||
#define ODM_COMP_CALIBRATION BIT26
|
||||
/* Common Functions */
|
||||
#define ODM_COMP_COMMON BIT30
|
||||
#define ODM_COMP_INIT BIT31
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
#define DbgPrint printk
|
||||
#define RT_PRINTK(fmt, args...)\
|
||||
DbgPrint("%s(): " fmt, __func__, ## args)
|
||||
#define RT_DISP(dbgtype, dbgflag, printstr)
|
||||
|
||||
#ifndef ASSERT
|
||||
#define ASSERT(expr)
|
||||
#endif
|
||||
|
||||
#if DBG
|
||||
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)\
|
||||
if (\
|
||||
(comp & pDM_Odm->DebugComponents) &&\
|
||||
(level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)\
|
||||
) {\
|
||||
RT_PRINTK fmt;\
|
||||
}
|
||||
|
||||
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)\
|
||||
if (\
|
||||
(comp & pDM_Odm->DebugComponents) &&\
|
||||
(level <= pDM_Odm->DebugLevel)\
|
||||
) {\
|
||||
RT_PRINTK fmt;\
|
||||
}
|
||||
|
||||
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)\
|
||||
if (!expr) {\
|
||||
DbgPrint("Assertion failed! %s at ......\n", #expr);\
|
||||
DbgPrint(\
|
||||
" ......%s,%s, line =%d\n",\
|
||||
__FILE__,\
|
||||
__func__,\
|
||||
__LINE__\
|
||||
);\
|
||||
RT_PRINTK fmt;\
|
||||
ASSERT(false);\
|
||||
}
|
||||
#define ODM_dbg_enter() { DbgPrint("==> %s\n", __func__); }
|
||||
#define ODM_dbg_exit() { DbgPrint("<== %s\n", __func__); }
|
||||
#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __func__, str); }
|
||||
|
||||
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)\
|
||||
if (\
|
||||
(comp & pDM_Odm->DebugComponents) &&\
|
||||
(level <= pDM_Odm->DebugLevel)\
|
||||
) {\
|
||||
int __i;\
|
||||
u8 *__ptr = (u8 *)ptr;\
|
||||
DbgPrint("[ODM] ");\
|
||||
DbgPrint(title_str);\
|
||||
DbgPrint(" ");\
|
||||
for (__i = 0; __i < 6; __i++)\
|
||||
DbgPrint("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");\
|
||||
DbgPrint("\n");\
|
||||
}
|
||||
#else
|
||||
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)
|
||||
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)
|
||||
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)
|
||||
#define ODM_dbg_enter()
|
||||
#define ODM_dbg_exit()
|
||||
#define ODM_dbg_trace(str)
|
||||
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
|
||||
#endif
|
||||
|
||||
void ODM_InitDebugSetting(PDM_ODM_T pDM_Odm);
|
||||
|
||||
#endif /* __ODM_DBG_H__ */
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __ODM_INTERFACE_H__
|
||||
#define __ODM_INTERFACE_H__
|
||||
|
||||
|
||||
|
||||
/* =========== Constant/Structure/Enum/... Define */
|
||||
|
||||
/* =========== Macro Define */
|
||||
|
||||
#define _reg_all(_name) ODM_##_name
|
||||
#define _reg_ic(_name, _ic) ODM_##_name##_ic
|
||||
#define _bit_all(_name) BIT_##_name
|
||||
#define _bit_ic(_name, _ic) BIT_##_name##_ic
|
||||
|
||||
/*===================================
|
||||
|
||||
#define ODM_REG_DIG_11N 0xC50
|
||||
#define ODM_REG_DIG_11AC 0xDDD
|
||||
|
||||
ODM_REG(DIG, _pDM_Odm)
|
||||
=====================================*/
|
||||
|
||||
#define _reg_11N(_name) ODM_REG_##_name##_11N
|
||||
#define _bit_11N(_name) ODM_BIT_##_name##_11N
|
||||
|
||||
#define _cat(_name, _ic_type, _func) _func##_11N(_name)
|
||||
|
||||
/* _name: name of register or bit. */
|
||||
/* Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" */
|
||||
/* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. */
|
||||
#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg)
|
||||
#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
|
||||
|
||||
typedef enum _ODM_H2C_CMD {
|
||||
ODM_H2C_RSSI_REPORT = 0,
|
||||
ODM_H2C_PSD_RESULT = 1,
|
||||
ODM_H2C_PathDiv = 2,
|
||||
ODM_H2C_WIFI_CALIBRATION = 3,
|
||||
ODM_MAX_H2CCMD
|
||||
} ODM_H2C_CMD;
|
||||
|
||||
|
||||
#endif /* __ODM_INTERFACE_H__ */
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ODM_PRECOMP_H__
|
||||
#define __ODM_PRECOMP_H__
|
||||
|
||||
#include "odm_types.h"
|
||||
|
||||
#define TEST_FALG___ 1
|
||||
|
||||
/* 2 Config Flags and Structs - defined by each ODM Type */
|
||||
|
||||
/* include <basic_types.h> */
|
||||
/* include <osdep_service.h> */
|
||||
/* include <drv_types.h> */
|
||||
/* include <rtw_byteorder.h> */
|
||||
/* include <hal_intf.h> */
|
||||
#define BEAMFORMING_SUPPORT 0
|
||||
|
||||
/* 2 Hardware Parameter Files */
|
||||
|
||||
/* 2 OutSrc Header Files */
|
||||
|
||||
#include "odm.h"
|
||||
#include "odm_HWConfig.h"
|
||||
#include "odm_debug.h"
|
||||
#include "odm_RegDefine11N.h"
|
||||
#include "odm_AntDiv.h"
|
||||
#include "odm_EdcaTurboCheck.h"
|
||||
#include "odm_DIG.h"
|
||||
#include "odm_PathDiv.h"
|
||||
#include "odm_DynamicBBPowerSaving.h"
|
||||
#include "odm_DynamicTxPower.h"
|
||||
#include "odm_CfoTracking.h"
|
||||
#include "odm_NoiseMonitor.h"
|
||||
#include "HalPhyRf.h"
|
||||
#include "HalPhyRf_8723B.h"/* for IQK, LCK, Power-tracking */
|
||||
#include "rtl8723b_hal.h"
|
||||
#include "odm_interface.h"
|
||||
#include "odm_reg.h"
|
||||
#include "HalHWImg8723B_MAC.h"
|
||||
#include "HalHWImg8723B_RF.h"
|
||||
#include "HalHWImg8723B_BB.h"
|
||||
#include "Hal8723BReg.h"
|
||||
#include "odm_RTL8723B.h"
|
||||
#include "odm_RegConfig8723B.h"
|
||||
|
||||
#endif /* __ODM_PRECOMP_H__ */
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
/* File Name: odm_reg.h */
|
||||
/* Description: */
|
||||
/* This file is for general register definition. */
|
||||
#ifndef __HAL_ODM_REG_H__
|
||||
#define __HAL_ODM_REG_H__
|
||||
|
||||
/* Register Definition */
|
||||
|
||||
/* MAC REG */
|
||||
#define ODM_BB_RESET 0x002
|
||||
#define ODM_DUMMY 0x4fe
|
||||
#define RF_T_METER_OLD 0x24
|
||||
#define RF_T_METER_NEW 0x42
|
||||
|
||||
#define ODM_EDCA_VO_PARAM 0x500
|
||||
#define ODM_EDCA_VI_PARAM 0x504
|
||||
#define ODM_EDCA_BE_PARAM 0x508
|
||||
#define ODM_EDCA_BK_PARAM 0x50C
|
||||
#define ODM_TXPAUSE 0x522
|
||||
|
||||
/* BB REG */
|
||||
#define ODM_FPGA_PHY0_PAGE8 0x800
|
||||
#define ODM_PSD_SETTING 0x808
|
||||
#define ODM_AFE_SETTING 0x818
|
||||
#define ODM_TXAGC_B_24_54 0x834
|
||||
#define ODM_TXAGC_B_MCS32_5 0x838
|
||||
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
|
||||
#define ODM_TXAGC_B_MCS4_MCS7 0x848
|
||||
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
|
||||
#define ODM_ANALOG_REGISTER 0x85c
|
||||
#define ODM_RF_INTERFACE_OUTPUT 0x860
|
||||
#define ODM_TXAGC_B_MCS12_MCS15 0x868
|
||||
#define ODM_TXAGC_B_11_A_2_11 0x86c
|
||||
#define ODM_AD_DA_LSB_MASK 0x874
|
||||
#define ODM_ENABLE_3_WIRE 0x88c
|
||||
#define ODM_PSD_REPORT 0x8b4
|
||||
#define ODM_R_ANT_SELECT 0x90c
|
||||
#define ODM_CCK_ANT_SELECT 0xa07
|
||||
#define ODM_CCK_PD_THRESH 0xa0a
|
||||
#define ODM_CCK_RF_REG1 0xa11
|
||||
#define ODM_CCK_MATCH_FILTER 0xa20
|
||||
#define ODM_CCK_RAKE_MAC 0xa2e
|
||||
#define ODM_CCK_CNT_RESET 0xa2d
|
||||
#define ODM_CCK_TX_DIVERSITY 0xa2f
|
||||
#define ODM_CCK_FA_CNT_MSB 0xa5b
|
||||
#define ODM_CCK_FA_CNT_LSB 0xa5c
|
||||
#define ODM_CCK_NEW_FUNCTION 0xa75
|
||||
#define ODM_OFDM_PHY0_PAGE_C 0xc00
|
||||
#define ODM_OFDM_RX_ANT 0xc04
|
||||
#define ODM_R_A_RXIQI 0xc14
|
||||
#define ODM_R_A_AGC_CORE1 0xc50
|
||||
#define ODM_R_A_AGC_CORE2 0xc54
|
||||
#define ODM_R_B_AGC_CORE1 0xc58
|
||||
#define ODM_R_AGC_PAR 0xc70
|
||||
#define ODM_R_HTSTF_AGC_PAR 0xc7c
|
||||
#define ODM_TX_PWR_TRAINING_A 0xc90
|
||||
#define ODM_TX_PWR_TRAINING_B 0xc98
|
||||
#define ODM_OFDM_FA_CNT1 0xcf0
|
||||
#define ODM_OFDM_PHY0_PAGE_D 0xd00
|
||||
#define ODM_OFDM_FA_CNT2 0xda0
|
||||
#define ODM_OFDM_FA_CNT3 0xda4
|
||||
#define ODM_OFDM_FA_CNT4 0xda8
|
||||
#define ODM_TXAGC_A_6_18 0xe00
|
||||
#define ODM_TXAGC_A_24_54 0xe04
|
||||
#define ODM_TXAGC_A_1_MCS32 0xe08
|
||||
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
|
||||
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
|
||||
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
|
||||
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
|
||||
|
||||
/* RF REG */
|
||||
#define ODM_GAIN_SETTING 0x00
|
||||
#define ODM_CHANNEL 0x18
|
||||
|
||||
/* Ant Detect Reg */
|
||||
#define ODM_DPDT 0x300
|
||||
|
||||
/* PSD Init */
|
||||
#define ODM_PSDREG 0x808
|
||||
|
||||
/* 92D Path Div */
|
||||
#define PATHDIV_REG 0xB30
|
||||
#define PATHDIV_TRI 0xBA0
|
||||
|
||||
/* Bitmap Definition */
|
||||
|
||||
#define BIT_FA_RESET BIT0
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __ODM_TYPES_H__
|
||||
#define __ODM_TYPES_H__
|
||||
|
||||
#include <drv_types.h>
|
||||
|
||||
/* Deifne HW endian support */
|
||||
#define ODM_ENDIAN_BIG 0
|
||||
#define ODM_ENDIAN_LITTLE 1
|
||||
|
||||
#define GET_ODM(__padapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__padapter))->odmpriv)))
|
||||
|
||||
typedef enum _HAL_STATUS {
|
||||
HAL_STATUS_SUCCESS,
|
||||
HAL_STATUS_FAILURE,
|
||||
/*RT_STATUS_PENDING,
|
||||
RT_STATUS_RESOURCE,
|
||||
RT_STATUS_INVALID_CONTEXT,
|
||||
RT_STATUS_INVALID_PARAMETER,
|
||||
RT_STATUS_NOT_SUPPORT,
|
||||
RT_STATUS_OS_API_FAILED,*/
|
||||
} HAL_STATUS, *PHAL_STATUS;
|
||||
|
||||
|
||||
/* */
|
||||
/* Declare for ODM spin lock defintion temporarily fro compile pass. */
|
||||
/* */
|
||||
typedef enum _RT_SPINLOCK_TYPE {
|
||||
RT_TX_SPINLOCK = 1,
|
||||
RT_RX_SPINLOCK = 2,
|
||||
RT_RM_SPINLOCK = 3,
|
||||
RT_CAM_SPINLOCK = 4,
|
||||
RT_SCAN_SPINLOCK = 5,
|
||||
RT_LOG_SPINLOCK = 7,
|
||||
RT_BW_SPINLOCK = 8,
|
||||
RT_CHNLOP_SPINLOCK = 9,
|
||||
RT_RF_OPERATE_SPINLOCK = 10,
|
||||
RT_INITIAL_SPINLOCK = 11,
|
||||
RT_RF_STATE_SPINLOCK = 12, /* For RF state. Added by Bruce, 2007-10-30. */
|
||||
/* Shall we define Ndis 6.2 SpinLock Here ? */
|
||||
RT_PORT_SPINLOCK = 16,
|
||||
RT_H2C_SPINLOCK = 20, /* For H2C cmd. Added by tynli. 2009.11.09. */
|
||||
|
||||
RT_BTData_SPINLOCK = 25,
|
||||
|
||||
RT_WAPI_OPTION_SPINLOCK = 26,
|
||||
RT_WAPI_RX_SPINLOCK = 27,
|
||||
|
||||
/* add for 92D CCK control issue */
|
||||
RT_CCK_PAGEA_SPINLOCK = 28,
|
||||
RT_BUFFER_SPINLOCK = 29,
|
||||
RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
|
||||
RT_GEN_TEMP_BUF_SPINLOCK = 31,
|
||||
RT_AWB_SPINLOCK = 32,
|
||||
RT_FW_PS_SPINLOCK = 33,
|
||||
RT_HW_TIMER_SPIN_LOCK = 34,
|
||||
RT_MPT_WI_SPINLOCK = 35,
|
||||
RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */
|
||||
RT_DBG_SPIN_LOCK = 37,
|
||||
RT_IQK_SPINLOCK = 38,
|
||||
RT_PENDED_OID_SPINLOCK = 39,
|
||||
RT_CHNLLIST_SPINLOCK = 40,
|
||||
RT_INDIC_SPINLOCK = 41, /* protect indication */
|
||||
} RT_SPINLOCK_TYPE;
|
||||
|
||||
#if defined(__LITTLE_ENDIAN)
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
|
||||
#else
|
||||
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
|
||||
#endif
|
||||
|
||||
typedef struct timer_list RT_TIMER, *PRT_TIMER;
|
||||
typedef void *RT_TIMER_CALL_BACK;
|
||||
#define STA_INFO_T struct sta_info
|
||||
#define PSTA_INFO_T struct sta_info *
|
||||
|
||||
#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
|
||||
|
||||
/* define useless flag to avoid compile warning */
|
||||
#define USE_WORKITEM 0
|
||||
#define FPGA_TWO_MAC_VERIFICATION 0
|
||||
|
||||
#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)
|
||||
#define COND_ELSE 2
|
||||
#define COND_ENDIF 3
|
||||
|
||||
#endif /* __ODM_TYPES_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,300 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Description: */
|
||||
/* This file is for 92CE/92CU dynamic mechanism only */
|
||||
|
||||
#define _RTL8723B_DM_C_
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <rtw_debug.h>
|
||||
#include <rtl8723b_hal.h>
|
||||
|
||||
/* Global var */
|
||||
|
||||
static void dm_CheckStatistics(struct adapter *Adapter)
|
||||
{
|
||||
}
|
||||
/* */
|
||||
/* functions */
|
||||
/* */
|
||||
static void Init_ODM_ComInfo_8723b(struct adapter *Adapter)
|
||||
{
|
||||
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
|
||||
struct dm_priv *pdmpriv = &pHalData->dmpriv;
|
||||
u8 cut_ver, fab_ver;
|
||||
|
||||
/* */
|
||||
/* Init Value */
|
||||
/* */
|
||||
memset(pDM_Odm, 0, sizeof(*pDM_Odm));
|
||||
|
||||
pDM_Odm->Adapter = Adapter;
|
||||
#define ODM_CE 0x04
|
||||
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PLATFORM, ODM_CE);
|
||||
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_INTERFACE, RTW_SDIO);
|
||||
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, pHalData->PackageType);
|
||||
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_IC_TYPE, ODM_RTL8723B);
|
||||
|
||||
fab_ver = ODM_TSMC;
|
||||
cut_ver = ODM_CUT_A;
|
||||
|
||||
DBG_871X("%s(): fab_ver =%d cut_ver =%d\n", __func__, fab_ver, cut_ver);
|
||||
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_FAB_VER, fab_ver);
|
||||
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_CUT_VER, cut_ver);
|
||||
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->VersionID));
|
||||
|
||||
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID);
|
||||
/* ODM_CMNINFO_BINHCT_TEST only for MP Team */
|
||||
ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, Adapter->registrypriv.wifi_spec);
|
||||
|
||||
|
||||
if (pHalData->rf_type == RF_1T1R) {
|
||||
ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T1R);
|
||||
} else if (pHalData->rf_type == RF_2T2R) {
|
||||
ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R);
|
||||
} else if (pHalData->rf_type == RF_1T2R) {
|
||||
ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T2R);
|
||||
}
|
||||
|
||||
pdmpriv->InitODMFlag = ODM_RF_CALIBRATION|ODM_RF_TX_PWR_TRACK;
|
||||
|
||||
ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pdmpriv->InitODMFlag);
|
||||
}
|
||||
|
||||
static void Update_ODM_ComInfo_8723b(struct adapter *Adapter)
|
||||
{
|
||||
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
|
||||
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
|
||||
struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
|
||||
struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
|
||||
struct dm_priv *pdmpriv = &pHalData->dmpriv;
|
||||
int i;
|
||||
u8 zero = 0;
|
||||
|
||||
pdmpriv->InitODMFlag = 0
|
||||
| ODM_BB_DIG
|
||||
| ODM_BB_RA_MASK
|
||||
| ODM_BB_DYNAMIC_TXPWR
|
||||
| ODM_BB_FA_CNT
|
||||
| ODM_BB_RSSI_MONITOR
|
||||
| ODM_BB_CCK_PD
|
||||
| ODM_BB_PWR_SAVE
|
||||
| ODM_BB_CFO_TRACKING
|
||||
| ODM_MAC_EDCA_TURBO
|
||||
| ODM_RF_TX_PWR_TRACK
|
||||
| ODM_RF_CALIBRATION
|
||||
#ifdef CONFIG_ODM_ADAPTIVITY
|
||||
| ODM_BB_ADAPTIVITY
|
||||
#endif
|
||||
;
|
||||
|
||||
/* */
|
||||
/* Pointer reference */
|
||||
/* */
|
||||
/* ODM_CMNINFO_MAC_PHY_MODE pHalData->MacPhyMode92D */
|
||||
/* ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_MAC_PHY_MODE,&(pDM_Odm->u8_temp)); */
|
||||
|
||||
ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pdmpriv->InitODMFlag);
|
||||
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes));
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes));
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_WM_MODE, &(pmlmeext->cur_wireless_mode));
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC));
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(Adapter->securitypriv.dot11PrivacyAlgrthm));
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->CurrentChannelBW));
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->CurrentChannel));
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(Adapter->net_closed));
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_MP_MODE, &zero);
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->CurrentBandType));
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb));
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate));
|
||||
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SCAN, &(pmlmepriv->bScanInProcess));
|
||||
ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctrlpriv->bpower_saving));
|
||||
|
||||
|
||||
for (i = 0; i < NUM_STA; i++)
|
||||
ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL);
|
||||
}
|
||||
|
||||
void rtl8723b_InitHalDm(struct adapter *Adapter)
|
||||
{
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
struct dm_priv *pdmpriv = &pHalData->dmpriv;
|
||||
PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
|
||||
|
||||
pdmpriv->DM_Type = DM_Type_ByDriver;
|
||||
pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE;
|
||||
|
||||
pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
|
||||
|
||||
pdmpriv->InitDMFlag = pdmpriv->DMFlag;
|
||||
|
||||
Update_ODM_ComInfo_8723b(Adapter);
|
||||
|
||||
ODM_DMInit(pDM_Odm);
|
||||
}
|
||||
|
||||
void rtl8723b_HalDmWatchDog(struct adapter *Adapter)
|
||||
{
|
||||
bool bFwCurrentInPSMode = false;
|
||||
bool bFwPSAwake = true;
|
||||
u8 hw_init_completed = false;
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
hw_init_completed = Adapter->hw_init_completed;
|
||||
|
||||
if (hw_init_completed == false)
|
||||
goto skip_dm;
|
||||
|
||||
bFwCurrentInPSMode = adapter_to_pwrctl(Adapter)->bFwCurrentInPSMode;
|
||||
rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake));
|
||||
|
||||
if (
|
||||
(hw_init_completed == true) &&
|
||||
((!bFwCurrentInPSMode) && bFwPSAwake)
|
||||
) {
|
||||
/* */
|
||||
/* Calculate Tx/Rx statistics. */
|
||||
/* */
|
||||
dm_CheckStatistics(Adapter);
|
||||
rtw_hal_check_rxfifo_full(Adapter);
|
||||
}
|
||||
|
||||
/* ODM */
|
||||
if (hw_init_completed == true) {
|
||||
u8 bLinked = false;
|
||||
u8 bsta_state = false;
|
||||
u8 bBtDisabled = true;
|
||||
|
||||
if (rtw_linked_check(Adapter)) {
|
||||
bLinked = true;
|
||||
if (check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE))
|
||||
bsta_state = true;
|
||||
}
|
||||
|
||||
ODM_CmnInfoUpdate(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
|
||||
ODM_CmnInfoUpdate(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
|
||||
|
||||
/* ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); */
|
||||
|
||||
bBtDisabled = rtw_btcoex_IsBtDisabled(Adapter);
|
||||
|
||||
ODM_CmnInfoUpdate(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, ((bBtDisabled == true)?false:true));
|
||||
|
||||
ODM_DMWatchdog(&pHalData->odmpriv);
|
||||
}
|
||||
|
||||
skip_dm:
|
||||
return;
|
||||
}
|
||||
|
||||
void rtl8723b_hal_dm_in_lps(struct adapter *padapter)
|
||||
{
|
||||
u32 PWDB_rssi = 0;
|
||||
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
|
||||
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
|
||||
struct sta_priv *pstapriv = &padapter->stapriv;
|
||||
struct sta_info *psta = NULL;
|
||||
|
||||
DBG_871X("%s, RSSI_Min =%d\n", __func__, pDM_Odm->RSSI_Min);
|
||||
|
||||
/* update IGI */
|
||||
ODM_Write_DIG(pDM_Odm, pDM_Odm->RSSI_Min);
|
||||
|
||||
|
||||
/* set rssi to fw */
|
||||
psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
|
||||
if (psta && (psta->rssi_stat.UndecoratedSmoothedPWDB > 0)) {
|
||||
PWDB_rssi = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
|
||||
|
||||
rtl8723b_set_rssi_cmd(padapter, (u8 *)&PWDB_rssi);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void rtl8723b_HalDmWatchDog_in_LPS(struct adapter *Adapter)
|
||||
{
|
||||
u8 bLinked = false;
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
|
||||
struct dm_priv *pdmpriv = &pHalData->dmpriv;
|
||||
PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
|
||||
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
|
||||
struct sta_priv *pstapriv = &Adapter->stapriv;
|
||||
struct sta_info *psta = NULL;
|
||||
|
||||
if (Adapter->hw_init_completed == false)
|
||||
goto skip_lps_dm;
|
||||
|
||||
|
||||
if (rtw_linked_check(Adapter))
|
||||
bLinked = true;
|
||||
|
||||
ODM_CmnInfoUpdate(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked);
|
||||
|
||||
if (bLinked == false)
|
||||
goto skip_lps_dm;
|
||||
|
||||
if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
|
||||
goto skip_lps_dm;
|
||||
|
||||
|
||||
/* ODM_DMWatchdog(&pHalData->odmpriv); */
|
||||
/* Do DIG by RSSI In LPS-32K */
|
||||
|
||||
/* 1 Find MIN-RSSI */
|
||||
psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
|
||||
if (psta == NULL)
|
||||
goto skip_lps_dm;
|
||||
|
||||
pdmpriv->EntryMinUndecoratedSmoothedPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
|
||||
|
||||
DBG_871X("CurIGValue =%d, EntryMinUndecoratedSmoothedPWDB = %d\n", pDM_DigTable->CurIGValue, pdmpriv->EntryMinUndecoratedSmoothedPWDB);
|
||||
|
||||
if (pdmpriv->EntryMinUndecoratedSmoothedPWDB <= 0)
|
||||
goto skip_lps_dm;
|
||||
|
||||
pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
|
||||
|
||||
pDM_Odm->RSSI_Min = pdmpriv->MinUndecoratedPWDBForDM;
|
||||
|
||||
/* if (pDM_DigTable->CurIGValue != pDM_Odm->RSSI_Min) */
|
||||
if (
|
||||
(pDM_DigTable->CurIGValue > pDM_Odm->RSSI_Min + 5) ||
|
||||
(pDM_DigTable->CurIGValue < pDM_Odm->RSSI_Min - 5)
|
||||
)
|
||||
rtw_dm_in_lps_wk_cmd(Adapter);
|
||||
|
||||
|
||||
skip_lps_dm:
|
||||
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
void rtl8723b_init_dm_priv(struct adapter *Adapter)
|
||||
{
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
struct dm_priv *pdmpriv = &pHalData->dmpriv;
|
||||
|
||||
memset(pdmpriv, 0, sizeof(struct dm_priv));
|
||||
Init_ODM_ComInfo_8723b(Adapter);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,224 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
*
|
||||
*
|
||||
* Module: rtl8192c_rf6052.c (Source C File)
|
||||
*
|
||||
* Note: Provide RF 6052 series relative API.
|
||||
*
|
||||
* Function:
|
||||
*
|
||||
* Export:
|
||||
*
|
||||
* Abbrev:
|
||||
*
|
||||
* History:
|
||||
* Data Who Remark
|
||||
*
|
||||
* 09/25/2008 MHC Create initial version.
|
||||
* 11/05/2008 MHC Add API for tw power setting.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <rtl8723b_hal.h>
|
||||
|
||||
/*---------------------------Define Local Constant---------------------------*/
|
||||
/*---------------------------Define Local Constant---------------------------*/
|
||||
|
||||
|
||||
/*------------------------Define global variable-----------------------------*/
|
||||
/*------------------------Define global variable-----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Define local variable------------------------------*/
|
||||
/* 2008/11/20 MH For Debug only, RF */
|
||||
/*------------------------Define local variable------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Function: PHY_RF6052SetBandwidth()
|
||||
*
|
||||
* Overview: This function is called by SetBWModeCallback8190Pci() only
|
||||
*
|
||||
* Input: struct adapter * Adapter
|
||||
* WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M
|
||||
*
|
||||
* Output: NONE
|
||||
*
|
||||
* Return: NONE
|
||||
*
|
||||
* Note: For RF type 0222D
|
||||
*---------------------------------------------------------------------------*/
|
||||
void PHY_RF6052SetBandwidth8723B(
|
||||
struct adapter *Adapter, enum CHANNEL_WIDTH Bandwidth
|
||||
) /* 20M or 40M */
|
||||
{
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
switch (Bandwidth) {
|
||||
case CHANNEL_WIDTH_20:
|
||||
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11);
|
||||
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
|
||||
PHY_SetRFReg(Adapter, ODM_RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
|
||||
break;
|
||||
|
||||
case CHANNEL_WIDTH_40:
|
||||
pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10);
|
||||
PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
|
||||
PHY_SetRFReg(Adapter, ODM_RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n", Bandwidth)); */
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
|
||||
{
|
||||
u32 u4RegValue = 0;
|
||||
u8 eRFPath;
|
||||
struct bb_register_def *pPhyReg;
|
||||
|
||||
int rtStatus = _SUCCESS;
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
|
||||
static char sz8723RadioAFile[] = RTL8723B_PHY_RADIO_A;
|
||||
static char sz8723RadioBFile[] = RTL8723B_PHY_RADIO_B;
|
||||
static s8 sz8723BTxPwrTrackFile[] = RTL8723B_TXPWR_TRACK;
|
||||
char *pszRadioAFile, *pszRadioBFile, *pszTxPwrTrackFile;
|
||||
|
||||
pszRadioAFile = sz8723RadioAFile;
|
||||
pszRadioBFile = sz8723RadioBFile;
|
||||
pszTxPwrTrackFile = sz8723BTxPwrTrackFile;
|
||||
|
||||
/* 3----------------------------------------------------------------- */
|
||||
/* 3 <2> Initialize RF */
|
||||
/* 3----------------------------------------------------------------- */
|
||||
/* for (eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) */
|
||||
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
|
||||
|
||||
pPhyReg = &pHalData->PHYRegDef[eRFPath];
|
||||
|
||||
/*----Store original RFENV control type----*/
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
case RF_PATH_C:
|
||||
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
|
||||
break;
|
||||
case RF_PATH_B:
|
||||
case RF_PATH_D:
|
||||
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
|
||||
break;
|
||||
}
|
||||
|
||||
/*----Set RF_ENV enable----*/
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
|
||||
udelay(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/*----Set RF_ENV output high----*/
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
|
||||
udelay(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/* Set bit number of Address and Data for RF register */
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
|
||||
udelay(1);/* PlatformStallExecution(1); */
|
||||
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
|
||||
udelay(1);/* PlatformStallExecution(1); */
|
||||
|
||||
/*----Initialize RF fom connfiguration file----*/
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, eRFPath) == _FAIL)
|
||||
{
|
||||
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath))
|
||||
rtStatus = _FAIL;
|
||||
}
|
||||
break;
|
||||
case RF_PATH_B:
|
||||
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, eRFPath) == _FAIL)
|
||||
{
|
||||
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath))
|
||||
rtStatus = _FAIL;
|
||||
}
|
||||
break;
|
||||
case RF_PATH_C:
|
||||
break;
|
||||
case RF_PATH_D:
|
||||
break;
|
||||
}
|
||||
|
||||
/*----Restore RFENV control type----*/;
|
||||
switch (eRFPath) {
|
||||
case RF_PATH_A:
|
||||
case RF_PATH_C:
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
|
||||
break;
|
||||
case RF_PATH_B:
|
||||
case RF_PATH_D:
|
||||
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
|
||||
break;
|
||||
}
|
||||
|
||||
if (rtStatus != _SUCCESS) {
|
||||
/* RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */
|
||||
goto phy_RF6052_Config_ParaFile_Fail;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* 3 ----------------------------------------------------------------- */
|
||||
/* 3 Configuration of Tx Power Tracking */
|
||||
/* 3 ----------------------------------------------------------------- */
|
||||
|
||||
if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, pszTxPwrTrackFile) == _FAIL)
|
||||
{
|
||||
ODM_ConfigRFWithTxPwrTrackHeaderFile(&pHalData->odmpriv);
|
||||
}
|
||||
|
||||
/* RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); */
|
||||
return rtStatus;
|
||||
|
||||
phy_RF6052_Config_ParaFile_Fail:
|
||||
return rtStatus;
|
||||
}
|
||||
|
||||
|
||||
int PHY_RF6052_Config8723B(struct adapter *Adapter)
|
||||
{
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
|
||||
int rtStatus = _SUCCESS;
|
||||
|
||||
/* */
|
||||
/* Initialize general global value */
|
||||
/* */
|
||||
/* TODO: Extend RF_PATH_C and RF_PATH_D in the future */
|
||||
if (pHalData->rf_type == RF_1T1R)
|
||||
pHalData->NumTotalRFPath = 1;
|
||||
else
|
||||
pHalData->NumTotalRFPath = 2;
|
||||
|
||||
/* */
|
||||
/* Config BB and RF */
|
||||
/* */
|
||||
rtStatus = phy_RF6052_Config_ParaFile(Adapter);
|
||||
return rtStatus;
|
||||
|
||||
}
|
||||
|
||||
/* End of HalRf6052.c */
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define _RTL8723B_REDESC_C_
|
||||
|
||||
#include <rtl8723b_hal.h>
|
||||
|
||||
static void process_rssi(struct adapter *padapter, union recv_frame *prframe)
|
||||
{
|
||||
struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
|
||||
struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data;
|
||||
|
||||
/* DBG_8192C("process_rssi => pattrib->rssil(%d) signal_strength(%d)\n ", pattrib->RecvSignalPower, pattrib->signal_strength); */
|
||||
/* if (pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) */
|
||||
{
|
||||
if (signal_stat->update_req) {
|
||||
signal_stat->total_num = 0;
|
||||
signal_stat->total_val = 0;
|
||||
signal_stat->update_req = 0;
|
||||
}
|
||||
|
||||
signal_stat->total_num++;
|
||||
signal_stat->total_val += pattrib->phy_info.SignalStrength;
|
||||
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
|
||||
}
|
||||
|
||||
} /* Process_UI_RSSI_8192C */
|
||||
|
||||
static void process_link_qual(struct adapter *padapter, union recv_frame *prframe)
|
||||
{
|
||||
struct rx_pkt_attrib *pattrib;
|
||||
struct signal_stat *signal_stat;
|
||||
|
||||
if (prframe == NULL || padapter == NULL)
|
||||
return;
|
||||
|
||||
pattrib = &prframe->u.hdr.attrib;
|
||||
signal_stat = &padapter->recvpriv.signal_qual_data;
|
||||
|
||||
/* DBG_8192C("process_link_qual => pattrib->signal_qual(%d)\n ", pattrib->signal_qual); */
|
||||
|
||||
if (signal_stat->update_req) {
|
||||
signal_stat->total_num = 0;
|
||||
signal_stat->total_val = 0;
|
||||
signal_stat->update_req = 0;
|
||||
}
|
||||
|
||||
signal_stat->total_num++;
|
||||
signal_stat->total_val += pattrib->phy_info.SignalQuality;
|
||||
signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num;
|
||||
} /* Process_UiLinkQuality8192S */
|
||||
|
||||
|
||||
void rtl8723b_process_phy_info(struct adapter *padapter, void *prframe)
|
||||
{
|
||||
union recv_frame *precvframe = (union recv_frame *)prframe;
|
||||
/* */
|
||||
/* Check RSSI */
|
||||
/* */
|
||||
process_rssi(padapter, precvframe);
|
||||
/* */
|
||||
/* Check PWDB. */
|
||||
/* */
|
||||
/* process_PWDB(padapter, precvframe); */
|
||||
|
||||
/* UpdateRxSignalStatistics8192C(Adapter, pRfd); */
|
||||
/* */
|
||||
/* Check EVM */
|
||||
/* */
|
||||
process_link_qual(padapter, precvframe);
|
||||
#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
|
||||
rtw_store_phy_info(padapter, prframe);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,490 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define _RTL8723BS_RECV_C_
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <rtw_debug.h>
|
||||
#include <rtl8723b_hal.h>
|
||||
|
||||
|
||||
static s32 initrecvbuf(struct recv_buf *precvbuf, struct adapter *padapter)
|
||||
{
|
||||
INIT_LIST_HEAD(&precvbuf->list);
|
||||
spin_lock_init(&precvbuf->recvbuf_lock);
|
||||
|
||||
precvbuf->adapter = padapter;
|
||||
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
static void update_recvframe_attrib(
|
||||
struct adapter *padapter, union recv_frame *precvframe, struct recv_stat *prxstat
|
||||
)
|
||||
{
|
||||
struct rx_pkt_attrib *pattrib;
|
||||
struct recv_stat report;
|
||||
PRXREPORT prxreport = (PRXREPORT)&report;
|
||||
|
||||
report.rxdw0 = prxstat->rxdw0;
|
||||
report.rxdw1 = prxstat->rxdw1;
|
||||
report.rxdw2 = prxstat->rxdw2;
|
||||
report.rxdw3 = prxstat->rxdw3;
|
||||
report.rxdw4 = prxstat->rxdw4;
|
||||
report.rxdw5 = prxstat->rxdw5;
|
||||
|
||||
pattrib = &precvframe->u.hdr.attrib;
|
||||
memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
|
||||
|
||||
/* update rx report to recv_frame attribute */
|
||||
pattrib->pkt_rpt_type = prxreport->c2h_ind?C2H_PACKET:NORMAL_RX;
|
||||
/* DBG_871X("%s: pkt_rpt_type =%d\n", __func__, pattrib->pkt_rpt_type); */
|
||||
|
||||
if (pattrib->pkt_rpt_type == NORMAL_RX) {
|
||||
/* Normal rx packet */
|
||||
/* update rx report to recv_frame attribute */
|
||||
pattrib->pkt_len = (u16)prxreport->pktlen;
|
||||
pattrib->drvinfo_sz = (u8)(prxreport->drvinfosize << 3);
|
||||
pattrib->physt = (u8)prxreport->physt;
|
||||
|
||||
pattrib->crc_err = (u8)prxreport->crc32;
|
||||
pattrib->icv_err = (u8)prxreport->icverr;
|
||||
|
||||
pattrib->bdecrypted = (u8)(prxreport->swdec ? 0 : 1);
|
||||
pattrib->encrypt = (u8)prxreport->security;
|
||||
|
||||
pattrib->qos = (u8)prxreport->qos;
|
||||
pattrib->priority = (u8)prxreport->tid;
|
||||
|
||||
pattrib->amsdu = (u8)prxreport->amsdu;
|
||||
|
||||
pattrib->seq_num = (u16)prxreport->seq;
|
||||
pattrib->frag_num = (u8)prxreport->frag;
|
||||
pattrib->mfrag = (u8)prxreport->mf;
|
||||
pattrib->mdata = (u8)prxreport->md;
|
||||
|
||||
pattrib->data_rate = (u8)prxreport->rx_rate;
|
||||
} else
|
||||
pattrib->pkt_len = (u16)prxreport->pktlen;
|
||||
}
|
||||
|
||||
/*
|
||||
* Notice:
|
||||
*Before calling this function,
|
||||
*precvframe->u.hdr.rx_data should be ready!
|
||||
*/
|
||||
static void update_recvframe_phyinfo(
|
||||
union recv_frame *precvframe, struct phy_stat *pphy_status
|
||||
)
|
||||
{
|
||||
struct adapter *padapter = precvframe->u.hdr.adapter;
|
||||
struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
|
||||
PODM_PHY_INFO_T pPHYInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info);
|
||||
|
||||
u8 *wlanhdr;
|
||||
ODM_PACKET_INFO_T pkt_info;
|
||||
u8 *sa = NULL;
|
||||
/* _irqL irqL; */
|
||||
struct sta_priv *pstapriv;
|
||||
struct sta_info *psta;
|
||||
|
||||
pkt_info.bPacketMatchBSSID = false;
|
||||
pkt_info.bPacketToSelf = false;
|
||||
pkt_info.bPacketBeacon = false;
|
||||
|
||||
|
||||
wlanhdr = get_recvframe_data(precvframe);
|
||||
|
||||
pkt_info.bPacketMatchBSSID = ((!IsFrameTypeCtrl(wlanhdr)) &&
|
||||
!pattrib->icv_err && !pattrib->crc_err &&
|
||||
!memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN));
|
||||
|
||||
pkt_info.bPacketToSelf = pkt_info.bPacketMatchBSSID && (!memcmp(get_ra(wlanhdr), myid(&padapter->eeprompriv), ETH_ALEN));
|
||||
|
||||
pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID && (GetFrameSubType(wlanhdr) == WIFI_BEACON);
|
||||
|
||||
sa = get_ta(wlanhdr);
|
||||
|
||||
pkt_info.StationID = 0xFF;
|
||||
|
||||
pstapriv = &padapter->stapriv;
|
||||
psta = rtw_get_stainfo(pstapriv, sa);
|
||||
if (psta) {
|
||||
pkt_info.StationID = psta->mac_id;
|
||||
/* DBG_8192C("%s ==> StationID(%d)\n", __func__, pkt_info.StationID); */
|
||||
}
|
||||
pkt_info.DataRate = pattrib->data_rate;
|
||||
|
||||
/* rtl8723b_query_rx_phy_status(precvframe, pphy_status); */
|
||||
/* spin_lock_bh(&pHalData->odm_stainfo_lock); */
|
||||
ODM_PhyStatusQuery(&pHalData->odmpriv, pPHYInfo, (u8 *)pphy_status, &(pkt_info));
|
||||
if (psta)
|
||||
psta->rssi = pattrib->phy_info.RecvSignalPower;
|
||||
/* spin_unlock_bh(&pHalData->odm_stainfo_lock); */
|
||||
precvframe->u.hdr.psta = NULL;
|
||||
if (
|
||||
pkt_info.bPacketMatchBSSID &&
|
||||
(check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == true)
|
||||
) {
|
||||
if (psta) {
|
||||
precvframe->u.hdr.psta = psta;
|
||||
rtl8723b_process_phy_info(padapter, precvframe);
|
||||
}
|
||||
} else if (pkt_info.bPacketToSelf || pkt_info.bPacketBeacon) {
|
||||
if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == true)
|
||||
if (psta)
|
||||
precvframe->u.hdr.psta = psta;
|
||||
rtl8723b_process_phy_info(padapter, precvframe);
|
||||
}
|
||||
}
|
||||
|
||||
static void rtl8723bs_c2h_packet_handler(struct adapter *padapter, u8 *pbuf, u16 length)
|
||||
{
|
||||
u8 *tmpBuf = NULL;
|
||||
u8 res = false;
|
||||
|
||||
if (length == 0)
|
||||
return;
|
||||
|
||||
/* DBG_871X("+%s() length =%d\n", __func__, length); */
|
||||
|
||||
tmpBuf = rtw_zmalloc(length);
|
||||
if (tmpBuf == NULL)
|
||||
return;
|
||||
|
||||
memcpy(tmpBuf, pbuf, length);
|
||||
|
||||
res = rtw_c2h_packet_wk_cmd(padapter, tmpBuf, length);
|
||||
|
||||
if (res == false)
|
||||
kfree(tmpBuf);
|
||||
|
||||
/* DBG_871X("-%s res(%d)\n", __func__, res); */
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void rtl8723bs_recv_tasklet(void *priv)
|
||||
{
|
||||
struct adapter *padapter;
|
||||
struct hal_com_data *pHalData;
|
||||
struct recv_priv *precvpriv;
|
||||
struct recv_buf *precvbuf;
|
||||
union recv_frame *precvframe;
|
||||
struct rx_pkt_attrib *pattrib;
|
||||
u8 *ptr;
|
||||
u32 pkt_offset, skb_len, alloc_sz;
|
||||
_pkt *pkt_copy = NULL;
|
||||
u8 shift_sz = 0, rx_report_sz = 0;
|
||||
|
||||
|
||||
padapter = (struct adapter *)priv;
|
||||
pHalData = GET_HAL_DATA(padapter);
|
||||
precvpriv = &padapter->recvpriv;
|
||||
|
||||
do {
|
||||
precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue);
|
||||
if (NULL == precvbuf)
|
||||
break;
|
||||
|
||||
ptr = precvbuf->pdata;
|
||||
|
||||
while (ptr < precvbuf->ptail) {
|
||||
precvframe = rtw_alloc_recvframe(&precvpriv->free_recv_queue);
|
||||
if (precvframe == NULL) {
|
||||
DBG_8192C("%s: no enough recv frame!\n", __func__);
|
||||
rtw_enqueue_recvbuf_to_head(precvbuf, &precvpriv->recv_buf_pending_queue);
|
||||
|
||||
/* The case of can't allocte recvframe should be temporary, */
|
||||
/* schedule again and hope recvframe is available next time. */
|
||||
tasklet_schedule(&precvpriv->recv_tasklet);
|
||||
return;
|
||||
}
|
||||
|
||||
/* rx desc parsing */
|
||||
update_recvframe_attrib(padapter, precvframe, (struct recv_stat *)ptr);
|
||||
|
||||
pattrib = &precvframe->u.hdr.attrib;
|
||||
|
||||
/* fix Hardware RX data error, drop whole recv_buffer */
|
||||
if ((!(pHalData->ReceiveConfig & RCR_ACRC32)) && pattrib->crc_err) {
|
||||
DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __func__, __LINE__);
|
||||
rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
|
||||
break;
|
||||
}
|
||||
|
||||
rx_report_sz = RXDESC_SIZE + pattrib->drvinfo_sz;
|
||||
pkt_offset = rx_report_sz + pattrib->shift_sz + pattrib->pkt_len;
|
||||
|
||||
if ((ptr + pkt_offset) > precvbuf->ptail) {
|
||||
DBG_8192C("%s()-%d: : next pkt len(%p,%d) exceed ptail(%p)!\n", __func__, __LINE__, ptr, pkt_offset, precvbuf->ptail);
|
||||
rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
|
||||
break;
|
||||
}
|
||||
|
||||
if ((pattrib->crc_err) || (pattrib->icv_err)) {
|
||||
{
|
||||
DBG_8192C("%s: crc_err =%d icv_err =%d, skip!\n", __func__, pattrib->crc_err, pattrib->icv_err);
|
||||
}
|
||||
rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
|
||||
} else {
|
||||
/* Modified by Albert 20101213 */
|
||||
/* For 8 bytes IP header alignment. */
|
||||
if (pattrib->qos) /* Qos data, wireless lan header length is 26 */
|
||||
shift_sz = 6;
|
||||
else
|
||||
shift_sz = 0;
|
||||
|
||||
skb_len = pattrib->pkt_len;
|
||||
|
||||
/* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */
|
||||
/* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */
|
||||
if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
|
||||
if (skb_len <= 1650)
|
||||
alloc_sz = 1664;
|
||||
else
|
||||
alloc_sz = skb_len + 14;
|
||||
} else {
|
||||
alloc_sz = skb_len;
|
||||
/* 6 is for IP header 8 bytes alignment in QoS packet case. */
|
||||
/* 8 is for skb->data 4 bytes alignment. */
|
||||
alloc_sz += 14;
|
||||
}
|
||||
|
||||
pkt_copy = rtw_skb_alloc(alloc_sz);
|
||||
|
||||
if (pkt_copy) {
|
||||
pkt_copy->dev = padapter->pnetdev;
|
||||
precvframe->u.hdr.pkt = pkt_copy;
|
||||
skb_reserve(pkt_copy, 8 - ((SIZE_PTR)(pkt_copy->data) & 7));/* force pkt_copy->data at 8-byte alignment address */
|
||||
skb_reserve(pkt_copy, shift_sz);/* force ip_hdr at 8-byte alignment address according to shift_sz. */
|
||||
memcpy(pkt_copy->data, (ptr + rx_report_sz + pattrib->shift_sz), skb_len);
|
||||
precvframe->u.hdr.rx_head = pkt_copy->head;
|
||||
precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data;
|
||||
precvframe->u.hdr.rx_end = skb_end_pointer(pkt_copy);
|
||||
} else {
|
||||
if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) {
|
||||
DBG_8192C("%s: alloc_skb fail, drop frag frame\n", __func__);
|
||||
rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
|
||||
break;
|
||||
}
|
||||
|
||||
precvframe->u.hdr.pkt = rtw_skb_clone(precvbuf->pskb);
|
||||
if (precvframe->u.hdr.pkt) {
|
||||
_pkt *pkt_clone = precvframe->u.hdr.pkt;
|
||||
|
||||
pkt_clone->data = ptr + rx_report_sz + pattrib->shift_sz;
|
||||
skb_reset_tail_pointer(pkt_clone);
|
||||
precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail
|
||||
= pkt_clone->data;
|
||||
precvframe->u.hdr.rx_end = pkt_clone->data + skb_len;
|
||||
} else {
|
||||
DBG_8192C("%s: rtw_skb_clone fail\n", __func__);
|
||||
rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
recvframe_put(precvframe, skb_len);
|
||||
/* recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); */
|
||||
|
||||
if (pHalData->ReceiveConfig & RCR_APPFCS)
|
||||
recvframe_pull_tail(precvframe, IEEE80211_FCS_LEN);
|
||||
|
||||
/* move to drv info position */
|
||||
ptr += RXDESC_SIZE;
|
||||
|
||||
/* update drv info */
|
||||
if (pHalData->ReceiveConfig & RCR_APP_BA_SSN) {
|
||||
/* rtl8723s_update_bassn(padapter, pdrvinfo); */
|
||||
ptr += 4;
|
||||
}
|
||||
|
||||
if (pattrib->pkt_rpt_type == NORMAL_RX) { /* Normal rx packet */
|
||||
if (pattrib->physt)
|
||||
update_recvframe_phyinfo(precvframe, (struct phy_stat *)ptr);
|
||||
|
||||
if (rtw_recv_entry(precvframe) != _SUCCESS) {
|
||||
RT_TRACE(_module_rtl871x_recv_c_, _drv_dump_, ("%s: rtw_recv_entry(precvframe) != _SUCCESS\n", __func__));
|
||||
}
|
||||
} else if (pattrib->pkt_rpt_type == C2H_PACKET) {
|
||||
C2H_EVT_HDR C2hEvent;
|
||||
|
||||
u16 len_c2h = pattrib->pkt_len;
|
||||
u8 *pbuf_c2h = precvframe->u.hdr.rx_data;
|
||||
u8 *pdata_c2h;
|
||||
|
||||
C2hEvent.CmdID = pbuf_c2h[0];
|
||||
C2hEvent.CmdSeq = pbuf_c2h[1];
|
||||
C2hEvent.CmdLen = (len_c2h-2);
|
||||
pdata_c2h = pbuf_c2h+2;
|
||||
|
||||
if (C2hEvent.CmdID == C2H_CCX_TX_RPT)
|
||||
CCX_FwC2HTxRpt_8723b(padapter, pdata_c2h, C2hEvent.CmdLen);
|
||||
else
|
||||
rtl8723bs_c2h_packet_handler(padapter, precvframe->u.hdr.rx_data, pattrib->pkt_len);
|
||||
|
||||
rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
pkt_offset = _RND8(pkt_offset);
|
||||
precvbuf->pdata += pkt_offset;
|
||||
ptr = precvbuf->pdata;
|
||||
precvframe = NULL;
|
||||
pkt_copy = NULL;
|
||||
}
|
||||
|
||||
rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue);
|
||||
} while (1);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize recv private variable for hardware dependent
|
||||
* 1. recv buf
|
||||
* 2. recv tasklet
|
||||
*
|
||||
*/
|
||||
s32 rtl8723bs_init_recv_priv(struct adapter *padapter)
|
||||
{
|
||||
s32 res;
|
||||
u32 i, n;
|
||||
struct recv_priv *precvpriv;
|
||||
struct recv_buf *precvbuf;
|
||||
|
||||
|
||||
res = _SUCCESS;
|
||||
precvpriv = &padapter->recvpriv;
|
||||
|
||||
/* 3 1. init recv buffer */
|
||||
_rtw_init_queue(&precvpriv->free_recv_buf_queue);
|
||||
_rtw_init_queue(&precvpriv->recv_buf_pending_queue);
|
||||
|
||||
n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
|
||||
precvpriv->pallocated_recv_buf = rtw_zmalloc(n);
|
||||
if (precvpriv->pallocated_recv_buf == NULL) {
|
||||
res = _FAIL;
|
||||
RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("alloc recv_buf fail!\n"));
|
||||
goto exit;
|
||||
}
|
||||
|
||||
precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4);
|
||||
|
||||
/* init each recv buffer */
|
||||
precvbuf = (struct recv_buf *)precvpriv->precv_buf;
|
||||
for (i = 0; i < NR_RECVBUFF; i++) {
|
||||
res = initrecvbuf(precvbuf, padapter);
|
||||
if (res == _FAIL)
|
||||
break;
|
||||
|
||||
if (precvbuf->pskb == NULL) {
|
||||
SIZE_PTR tmpaddr = 0;
|
||||
SIZE_PTR alignment = 0;
|
||||
|
||||
precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ);
|
||||
|
||||
if (precvbuf->pskb) {
|
||||
precvbuf->pskb->dev = padapter->pnetdev;
|
||||
|
||||
tmpaddr = (SIZE_PTR)precvbuf->pskb->data;
|
||||
alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1);
|
||||
skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment));
|
||||
}
|
||||
|
||||
if (precvbuf->pskb == NULL) {
|
||||
DBG_871X("%s: alloc_skb fail!\n", __func__);
|
||||
}
|
||||
}
|
||||
|
||||
list_add_tail(&precvbuf->list, &precvpriv->free_recv_buf_queue.queue);
|
||||
|
||||
precvbuf++;
|
||||
}
|
||||
precvpriv->free_recv_buf_queue_cnt = i;
|
||||
|
||||
if (res == _FAIL)
|
||||
goto initbuferror;
|
||||
|
||||
/* 3 2. init tasklet */
|
||||
tasklet_init(
|
||||
&precvpriv->recv_tasklet,
|
||||
(void(*)(unsigned long))rtl8723bs_recv_tasklet,
|
||||
(unsigned long)padapter
|
||||
);
|
||||
|
||||
goto exit;
|
||||
|
||||
initbuferror:
|
||||
precvbuf = (struct recv_buf *)precvpriv->precv_buf;
|
||||
if (precvbuf) {
|
||||
n = precvpriv->free_recv_buf_queue_cnt;
|
||||
precvpriv->free_recv_buf_queue_cnt = 0;
|
||||
for (i = 0; i < n ; i++) {
|
||||
list_del_init(&precvbuf->list);
|
||||
rtw_os_recvbuf_resource_free(padapter, precvbuf);
|
||||
precvbuf++;
|
||||
}
|
||||
precvpriv->precv_buf = NULL;
|
||||
}
|
||||
|
||||
if (precvpriv->pallocated_recv_buf) {
|
||||
n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
|
||||
kfree(precvpriv->pallocated_recv_buf);
|
||||
precvpriv->pallocated_recv_buf = NULL;
|
||||
}
|
||||
|
||||
exit:
|
||||
return res;
|
||||
}
|
||||
|
||||
/*
|
||||
* Free recv private variable of hardware dependent
|
||||
* 1. recv buf
|
||||
* 2. recv tasklet
|
||||
*
|
||||
*/
|
||||
void rtl8723bs_free_recv_priv(struct adapter *padapter)
|
||||
{
|
||||
u32 i, n;
|
||||
struct recv_priv *precvpriv;
|
||||
struct recv_buf *precvbuf;
|
||||
|
||||
|
||||
precvpriv = &padapter->recvpriv;
|
||||
|
||||
/* 3 1. kill tasklet */
|
||||
tasklet_kill(&precvpriv->recv_tasklet);
|
||||
|
||||
/* 3 2. free all recv buffers */
|
||||
precvbuf = (struct recv_buf *)precvpriv->precv_buf;
|
||||
if (precvbuf) {
|
||||
n = NR_RECVBUFF;
|
||||
precvpriv->free_recv_buf_queue_cnt = 0;
|
||||
for (i = 0; i < n ; i++) {
|
||||
list_del_init(&precvbuf->list);
|
||||
rtw_os_recvbuf_resource_free(padapter, precvbuf);
|
||||
precvbuf++;
|
||||
}
|
||||
precvpriv->precv_buf = NULL;
|
||||
}
|
||||
|
||||
if (precvpriv->pallocated_recv_buf) {
|
||||
n = NR_RECVBUFF * sizeof(struct recv_buf) + 4;
|
||||
kfree(precvpriv->pallocated_recv_buf);
|
||||
precvpriv->pallocated_recv_buf = NULL;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,686 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define _RTL8723BS_XMIT_C_
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <rtw_debug.h>
|
||||
#include <rtl8723b_hal.h>
|
||||
|
||||
static u8 rtw_sdio_wait_enough_TxOQT_space(struct adapter *padapter, u8 agg_num)
|
||||
{
|
||||
u32 n = 0;
|
||||
struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
|
||||
|
||||
while (pHalData->SdioTxOQTFreeSpace < agg_num)
|
||||
{
|
||||
if (
|
||||
(padapter->bSurpriseRemoved == true) ||
|
||||
(padapter->bDriverStopped == true)
|
||||
) {
|
||||
DBG_871X("%s: bSurpriseRemoved or bDriverStopped (wait TxOQT)\n", __func__);
|
||||
return false;
|
||||
}
|
||||
|
||||
HalQueryTxOQTBufferStatus8723BSdio(padapter);
|
||||
|
||||
if ((++n % 60) == 0) {
|
||||
if ((n % 300) == 0) {
|
||||
DBG_871X("%s(%d): QOT free space(%d), agg_num: %d\n",
|
||||
__func__, n, pHalData->SdioTxOQTFreeSpace, agg_num);
|
||||
}
|
||||
msleep(1);
|
||||
/* yield(); */
|
||||
}
|
||||
}
|
||||
|
||||
pHalData->SdioTxOQTFreeSpace -= agg_num;
|
||||
|
||||
/* if (n > 1) */
|
||||
/* ++priv->pshare->nr_out_of_txoqt_space; */
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static s32 rtl8723_dequeue_writeport(struct adapter *padapter)
|
||||
{
|
||||
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
|
||||
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
|
||||
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
|
||||
struct xmit_buf *pxmitbuf;
|
||||
struct adapter * pri_padapter = padapter;
|
||||
s32 ret = 0;
|
||||
u8 PageIdx = 0;
|
||||
u32 deviceId;
|
||||
u8 bUpdatePageNum = false;
|
||||
|
||||
ret = ret || check_fwstate(pmlmepriv, _FW_UNDER_SURVEY);
|
||||
|
||||
if (true == ret)
|
||||
pxmitbuf = dequeue_pending_xmitbuf_under_survey(pxmitpriv);
|
||||
else
|
||||
pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv);
|
||||
|
||||
if (pxmitbuf == NULL)
|
||||
return true;
|
||||
|
||||
deviceId = ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr);
|
||||
|
||||
/* translate fifo addr to queue index */
|
||||
switch (deviceId) {
|
||||
case WLAN_TX_HIQ_DEVICE_ID:
|
||||
PageIdx = HI_QUEUE_IDX;
|
||||
break;
|
||||
|
||||
case WLAN_TX_MIQ_DEVICE_ID:
|
||||
PageIdx = MID_QUEUE_IDX;
|
||||
break;
|
||||
|
||||
case WLAN_TX_LOQ_DEVICE_ID:
|
||||
PageIdx = LOW_QUEUE_IDX;
|
||||
break;
|
||||
}
|
||||
|
||||
query_free_page:
|
||||
/* check if hardware tx fifo page is enough */
|
||||
if (false == rtw_hal_sdio_query_tx_freepage(pri_padapter, PageIdx, pxmitbuf->pg_num)) {
|
||||
if (!bUpdatePageNum) {
|
||||
/* Total number of page is NOT available, so update current FIFO status */
|
||||
HalQueryTxBufferStatus8723BSdio(padapter);
|
||||
bUpdatePageNum = true;
|
||||
goto query_free_page;
|
||||
} else {
|
||||
bUpdatePageNum = false;
|
||||
enqueue_pending_xmitbuf_to_head(pxmitpriv, pxmitbuf);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
if (
|
||||
(padapter->bSurpriseRemoved == true) ||
|
||||
(padapter->bDriverStopped == true)
|
||||
) {
|
||||
RT_TRACE(
|
||||
_module_hal_xmit_c_,
|
||||
_drv_notice_,
|
||||
("%s: bSurpriseRemoved(wirte port)\n", __func__)
|
||||
);
|
||||
goto free_xmitbuf;
|
||||
}
|
||||
|
||||
if (rtw_sdio_wait_enough_TxOQT_space(padapter, pxmitbuf->agg_num) == false)
|
||||
goto free_xmitbuf;
|
||||
|
||||
traffic_check_for_leave_lps(padapter, true, pxmitbuf->agg_num);
|
||||
|
||||
rtw_write_port(padapter, deviceId, pxmitbuf->len, (u8 *)pxmitbuf);
|
||||
|
||||
rtw_hal_sdio_update_tx_freepage(pri_padapter, PageIdx, pxmitbuf->pg_num);
|
||||
|
||||
free_xmitbuf:
|
||||
/* rtw_free_xmitframe(pxmitpriv, pframe); */
|
||||
/* pxmitbuf->priv_data = NULL; */
|
||||
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
|
||||
|
||||
#ifdef CONFIG_SDIO_TX_TASKLET
|
||||
tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
|
||||
#endif
|
||||
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Description
|
||||
*Transmit xmitbuf to hardware tx fifo
|
||||
*
|
||||
* Return
|
||||
*_SUCCESS ok
|
||||
*_FAIL something error
|
||||
*/
|
||||
s32 rtl8723bs_xmit_buf_handler(struct adapter *padapter)
|
||||
{
|
||||
struct xmit_priv *pxmitpriv;
|
||||
u8 queue_empty, queue_pending;
|
||||
s32 ret;
|
||||
|
||||
|
||||
pxmitpriv = &padapter->xmitpriv;
|
||||
|
||||
if (down_interruptible(&pxmitpriv->xmit_sema)) {
|
||||
DBG_871X_LEVEL(_drv_emerg_, "%s: down SdioXmitBufSema fail!\n", __func__);
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
ret = (padapter->bDriverStopped == true) || (padapter->bSurpriseRemoved == true);
|
||||
if (ret) {
|
||||
RT_TRACE(
|
||||
_module_hal_xmit_c_,
|
||||
_drv_err_,
|
||||
(
|
||||
"%s: bDriverStopped(%d) bSurpriseRemoved(%d)!\n",
|
||||
__func__,
|
||||
padapter->bDriverStopped,
|
||||
padapter->bSurpriseRemoved
|
||||
)
|
||||
);
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
queue_pending = check_pending_xmitbuf(pxmitpriv);
|
||||
|
||||
if (queue_pending == false)
|
||||
return _SUCCESS;
|
||||
|
||||
ret = rtw_register_tx_alive(padapter);
|
||||
if (ret != _SUCCESS) {
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
do {
|
||||
queue_empty = rtl8723_dequeue_writeport(padapter);
|
||||
/* dump secondary adapter xmitbuf */
|
||||
} while (!queue_empty);
|
||||
|
||||
rtw_unregister_tx_alive(padapter);
|
||||
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
*Aggregation packets and send to hardware
|
||||
*
|
||||
* Return:
|
||||
*0 Success
|
||||
*-1 Hardware resource(TX FIFO) not ready
|
||||
*-2 Software resource(xmitbuf) not ready
|
||||
*/
|
||||
static s32 xmit_xmitframes(struct adapter *padapter, struct xmit_priv *pxmitpriv)
|
||||
{
|
||||
s32 err, ret;
|
||||
u32 k = 0;
|
||||
struct hw_xmit *hwxmits, *phwxmit;
|
||||
u8 no_res, idx, hwentry;
|
||||
struct tx_servq *ptxservq;
|
||||
struct list_head *sta_plist, *sta_phead, *frame_plist, *frame_phead;
|
||||
struct xmit_frame *pxmitframe;
|
||||
struct __queue *pframe_queue;
|
||||
struct xmit_buf *pxmitbuf;
|
||||
u32 txlen, max_xmit_len;
|
||||
u8 txdesc_size = TXDESC_SIZE;
|
||||
int inx[4];
|
||||
|
||||
err = 0;
|
||||
no_res = false;
|
||||
hwxmits = pxmitpriv->hwxmits;
|
||||
hwentry = pxmitpriv->hwxmit_entry;
|
||||
ptxservq = NULL;
|
||||
pxmitframe = NULL;
|
||||
pframe_queue = NULL;
|
||||
pxmitbuf = NULL;
|
||||
|
||||
if (padapter->registrypriv.wifi_spec == 1) {
|
||||
for (idx = 0; idx<4; idx++)
|
||||
inx[idx] = pxmitpriv->wmm_para_seq[idx];
|
||||
} else {
|
||||
inx[0] = 0;
|
||||
inx[1] = 1;
|
||||
inx[2] = 2;
|
||||
inx[3] = 3;
|
||||
}
|
||||
|
||||
/* 0(VO), 1(VI), 2(BE), 3(BK) */
|
||||
for (idx = 0; idx < hwentry; idx++) {
|
||||
phwxmit = hwxmits + inx[idx];
|
||||
|
||||
if (
|
||||
(check_pending_xmitbuf(pxmitpriv) == true) &&
|
||||
(padapter->mlmepriv.LinkDetectInfo.bHigherBusyTxTraffic == true)
|
||||
) {
|
||||
if ((phwxmit->accnt > 0) && (phwxmit->accnt < 5)) {
|
||||
err = -2;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
max_xmit_len = rtw_hal_get_sdio_tx_max_length(padapter, inx[idx]);
|
||||
|
||||
spin_lock_bh(&pxmitpriv->lock);
|
||||
|
||||
sta_phead = get_list_head(phwxmit->sta_queue);
|
||||
sta_plist = get_next(sta_phead);
|
||||
/* because stop_sta_xmit may delete sta_plist at any time */
|
||||
/* so we should add lock here, or while loop can not exit */
|
||||
while (sta_phead != sta_plist) {
|
||||
ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending);
|
||||
sta_plist = get_next(sta_plist);
|
||||
|
||||
#ifdef DBG_XMIT_BUF
|
||||
DBG_871X(
|
||||
"%s idx:%d hwxmit_pkt_num:%d ptxservq_pkt_num:%d\n",
|
||||
__func__,
|
||||
idx,
|
||||
phwxmit->accnt,
|
||||
ptxservq->qcnt
|
||||
);
|
||||
DBG_871X(
|
||||
"%s free_xmit_extbuf_cnt =%d free_xmitbuf_cnt =%d free_xmitframe_cnt =%d\n",
|
||||
__func__,
|
||||
pxmitpriv->free_xmit_extbuf_cnt,
|
||||
pxmitpriv->free_xmitbuf_cnt,
|
||||
pxmitpriv->free_xmitframe_cnt
|
||||
);
|
||||
#endif
|
||||
pframe_queue = &ptxservq->sta_pending;
|
||||
|
||||
frame_phead = get_list_head(pframe_queue);
|
||||
|
||||
while (list_empty(frame_phead) == false) {
|
||||
frame_plist = get_next(frame_phead);
|
||||
pxmitframe = LIST_CONTAINOR(frame_plist, struct xmit_frame, list);
|
||||
|
||||
/* check xmit_buf size enough or not */
|
||||
txlen = txdesc_size + rtw_wlan_pkt_size(pxmitframe);
|
||||
if (
|
||||
(NULL == pxmitbuf) ||
|
||||
((_RND(pxmitbuf->len, 8) + txlen) > max_xmit_len) ||
|
||||
(k >= (rtw_hal_sdio_max_txoqt_free_space(padapter)-1))
|
||||
) {
|
||||
if (pxmitbuf) {
|
||||
/* pxmitbuf->priv_data will be NULL, and will crash here */
|
||||
if (pxmitbuf->len > 0 && pxmitbuf->priv_data) {
|
||||
struct xmit_frame *pframe;
|
||||
pframe = (struct xmit_frame*)pxmitbuf->priv_data;
|
||||
pframe->agg_num = k;
|
||||
pxmitbuf->agg_num = k;
|
||||
rtl8723b_update_txdesc(pframe, pframe->buf_addr);
|
||||
rtw_free_xmitframe(pxmitpriv, pframe);
|
||||
pxmitbuf->priv_data = NULL;
|
||||
enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
|
||||
/* can not yield under lock */
|
||||
/* yield(); */
|
||||
} else
|
||||
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
|
||||
}
|
||||
|
||||
pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
|
||||
if (pxmitbuf == NULL) {
|
||||
#ifdef DBG_XMIT_BUF
|
||||
DBG_871X_LEVEL(_drv_err_, "%s: xmit_buf is not enough!\n", __func__);
|
||||
#endif
|
||||
err = -2;
|
||||
up(&(pxmitpriv->xmit_sema));
|
||||
break;
|
||||
}
|
||||
k = 0;
|
||||
}
|
||||
|
||||
/* ok to send, remove frame from queue */
|
||||
if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == true) {
|
||||
if (
|
||||
(pxmitframe->attrib.psta->state & WIFI_SLEEP_STATE) &&
|
||||
(pxmitframe->attrib.triggered == 0)
|
||||
) {
|
||||
DBG_871X(
|
||||
"%s: one not triggered pkt in queue when this STA sleep,"
|
||||
" break and goto next sta\n",
|
||||
__func__
|
||||
);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
list_del_init(&pxmitframe->list);
|
||||
ptxservq->qcnt--;
|
||||
phwxmit->accnt--;
|
||||
|
||||
if (k == 0) {
|
||||
pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
|
||||
pxmitbuf->priv_data = (u8 *)pxmitframe;
|
||||
}
|
||||
|
||||
/* coalesce the xmitframe to xmitbuf */
|
||||
pxmitframe->pxmitbuf = pxmitbuf;
|
||||
pxmitframe->buf_addr = pxmitbuf->ptail;
|
||||
|
||||
ret = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
|
||||
if (ret == _FAIL) {
|
||||
DBG_871X_LEVEL(_drv_err_, "%s: coalesce FAIL!", __func__);
|
||||
/* Todo: error handler */
|
||||
} else {
|
||||
k++;
|
||||
if (k != 1)
|
||||
rtl8723b_update_txdesc(pxmitframe, pxmitframe->buf_addr);
|
||||
rtw_count_tx_stats(padapter, pxmitframe, pxmitframe->attrib.last_txcmdsz);
|
||||
|
||||
txlen = txdesc_size + pxmitframe->attrib.last_txcmdsz;
|
||||
pxmitframe->pg_num = (txlen + 127)/128;
|
||||
pxmitbuf->pg_num += (txlen + 127)/128;
|
||||
/* if (k != 1) */
|
||||
/* ((struct xmit_frame*)pxmitbuf->priv_data)->pg_num += pxmitframe->pg_num; */
|
||||
pxmitbuf->ptail += _RND(txlen, 8); /* round to 8 bytes alignment */
|
||||
pxmitbuf->len = _RND(pxmitbuf->len, 8) + txlen;
|
||||
}
|
||||
|
||||
if (k != 1)
|
||||
rtw_free_xmitframe(pxmitpriv, pxmitframe);
|
||||
pxmitframe = NULL;
|
||||
}
|
||||
|
||||
if (list_empty(&pframe_queue->queue))
|
||||
list_del_init(&ptxservq->tx_pending);
|
||||
|
||||
if (err)
|
||||
break;
|
||||
}
|
||||
spin_unlock_bh(&pxmitpriv->lock);
|
||||
|
||||
/* dump xmit_buf to hw tx fifo */
|
||||
if (pxmitbuf) {
|
||||
RT_TRACE(_module_hal_xmit_c_, _drv_info_, ("pxmitbuf->len =%d enqueue\n", pxmitbuf->len));
|
||||
|
||||
if (pxmitbuf->len > 0) {
|
||||
struct xmit_frame *pframe;
|
||||
pframe = (struct xmit_frame*)pxmitbuf->priv_data;
|
||||
pframe->agg_num = k;
|
||||
pxmitbuf->agg_num = k;
|
||||
rtl8723b_update_txdesc(pframe, pframe->buf_addr);
|
||||
rtw_free_xmitframe(pxmitpriv, pframe);
|
||||
pxmitbuf->priv_data = NULL;
|
||||
enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
|
||||
yield();
|
||||
}
|
||||
else
|
||||
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
|
||||
pxmitbuf = NULL;
|
||||
}
|
||||
|
||||
if (err)
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Description
|
||||
*Transmit xmitframe from queue
|
||||
*
|
||||
* Return
|
||||
*_SUCCESS ok
|
||||
*_FAIL something error
|
||||
*/
|
||||
static s32 rtl8723bs_xmit_handler(struct adapter *padapter)
|
||||
{
|
||||
struct xmit_priv *pxmitpriv;
|
||||
s32 ret;
|
||||
|
||||
|
||||
pxmitpriv = &padapter->xmitpriv;
|
||||
|
||||
if (down_interruptible(&pxmitpriv->SdioXmitSema)) {
|
||||
DBG_871X_LEVEL(_drv_emerg_, "%s: down sema fail!\n", __func__);
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
next:
|
||||
if (
|
||||
(padapter->bDriverStopped == true) ||
|
||||
(padapter->bSurpriseRemoved == true)
|
||||
) {
|
||||
RT_TRACE(
|
||||
_module_hal_xmit_c_,
|
||||
_drv_notice_,
|
||||
(
|
||||
"%s: bDriverStopped(%d) bSurpriseRemoved(%d)\n",
|
||||
__func__,
|
||||
padapter->bDriverStopped,
|
||||
padapter->bSurpriseRemoved
|
||||
)
|
||||
);
|
||||
return _FAIL;
|
||||
}
|
||||
|
||||
spin_lock_bh(&pxmitpriv->lock);
|
||||
ret = rtw_txframes_pending(padapter);
|
||||
spin_unlock_bh(&pxmitpriv->lock);
|
||||
if (ret == 0) {
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
/* dequeue frame and write to hardware */
|
||||
|
||||
ret = xmit_xmitframes(padapter, pxmitpriv);
|
||||
if (ret == -2) {
|
||||
/* here sleep 1ms will cause big TP loss of TX */
|
||||
/* from 50+ to 40+ */
|
||||
if (padapter->registrypriv.wifi_spec)
|
||||
msleep(1);
|
||||
else
|
||||
yield();
|
||||
goto next;
|
||||
}
|
||||
|
||||
spin_lock_bh(&pxmitpriv->lock);
|
||||
ret = rtw_txframes_pending(padapter);
|
||||
spin_unlock_bh(&pxmitpriv->lock);
|
||||
if (ret == 1) {
|
||||
goto next;
|
||||
}
|
||||
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
int rtl8723bs_xmit_thread(void *context)
|
||||
{
|
||||
s32 ret;
|
||||
struct adapter *padapter;
|
||||
struct xmit_priv *pxmitpriv;
|
||||
u8 thread_name[20] = "RTWHALXT";
|
||||
|
||||
|
||||
ret = _SUCCESS;
|
||||
padapter = (struct adapter *)context;
|
||||
pxmitpriv = &padapter->xmitpriv;
|
||||
|
||||
rtw_sprintf(thread_name, 20, "%s-"ADPT_FMT, thread_name, ADPT_ARG(padapter));
|
||||
thread_enter(thread_name);
|
||||
|
||||
DBG_871X("start "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
|
||||
|
||||
/* For now, no one would down sema to check thread is running, */
|
||||
/* so mark this temporary, Lucas@20130820 */
|
||||
/* up(&pxmitpriv->SdioXmitTerminateSema); */
|
||||
|
||||
do {
|
||||
ret = rtl8723bs_xmit_handler(padapter);
|
||||
if (signal_pending(current)) {
|
||||
flush_signals(current);
|
||||
}
|
||||
} while (_SUCCESS == ret);
|
||||
|
||||
up(&pxmitpriv->SdioXmitTerminateSema);
|
||||
|
||||
RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("-%s\n", __func__));
|
||||
|
||||
thread_exit();
|
||||
}
|
||||
|
||||
s32 rtl8723bs_mgnt_xmit(
|
||||
struct adapter *padapter, struct xmit_frame *pmgntframe
|
||||
)
|
||||
{
|
||||
s32 ret = _SUCCESS;
|
||||
struct pkt_attrib *pattrib;
|
||||
struct xmit_buf *pxmitbuf;
|
||||
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
|
||||
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
|
||||
u8 *pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
|
||||
u8 txdesc_size = TXDESC_SIZE;
|
||||
|
||||
RT_TRACE(_module_hal_xmit_c_, _drv_info_, ("+%s\n", __func__));
|
||||
|
||||
pattrib = &pmgntframe->attrib;
|
||||
pxmitbuf = pmgntframe->pxmitbuf;
|
||||
|
||||
rtl8723b_update_txdesc(pmgntframe, pmgntframe->buf_addr);
|
||||
|
||||
pxmitbuf->len = txdesc_size + pattrib->last_txcmdsz;
|
||||
pxmitbuf->pg_num = (pxmitbuf->len + 127)/128; /* 128 is tx page size */
|
||||
pxmitbuf->ptail = pmgntframe->buf_addr + pxmitbuf->len;
|
||||
pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pmgntframe);
|
||||
|
||||
rtw_count_tx_stats(padapter, pmgntframe, pattrib->last_txcmdsz);
|
||||
|
||||
rtw_free_xmitframe(pxmitpriv, pmgntframe);
|
||||
|
||||
pxmitbuf->priv_data = NULL;
|
||||
|
||||
if (GetFrameSubType(pframe) == WIFI_BEACON) { /* dump beacon directly */
|
||||
ret = rtw_write_port(padapter, pdvobjpriv->Queue2Pipe[pxmitbuf->ff_hwaddr], pxmitbuf->len, (u8 *)pxmitbuf);
|
||||
if (ret != _SUCCESS)
|
||||
rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_WRITE_PORT_ERR);
|
||||
|
||||
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
|
||||
} else
|
||||
enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Description:
|
||||
*Handle xmitframe(packet) come from rtw_xmit()
|
||||
*
|
||||
* Return:
|
||||
*true dump packet directly ok
|
||||
*false enqueue, temporary can't transmit packets to hardware
|
||||
*/
|
||||
s32 rtl8723bs_hal_xmit(
|
||||
struct adapter *padapter, struct xmit_frame *pxmitframe
|
||||
)
|
||||
{
|
||||
struct xmit_priv *pxmitpriv;
|
||||
s32 err;
|
||||
|
||||
|
||||
pxmitframe->attrib.qsel = pxmitframe->attrib.priority;
|
||||
pxmitpriv = &padapter->xmitpriv;
|
||||
|
||||
if (
|
||||
(pxmitframe->frame_tag == DATA_FRAMETAG) &&
|
||||
(pxmitframe->attrib.ether_type != 0x0806) &&
|
||||
(pxmitframe->attrib.ether_type != 0x888e) &&
|
||||
(pxmitframe->attrib.dhcp_pkt != 1)
|
||||
) {
|
||||
if (padapter->mlmepriv.LinkDetectInfo.bBusyTraffic == true)
|
||||
rtw_issue_addbareq_cmd(padapter, pxmitframe);
|
||||
}
|
||||
|
||||
spin_lock_bh(&pxmitpriv->lock);
|
||||
err = rtw_xmitframe_enqueue(padapter, pxmitframe);
|
||||
spin_unlock_bh(&pxmitpriv->lock);
|
||||
if (err != _SUCCESS) {
|
||||
RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("rtl8723bs_hal_xmit: enqueue xmitframe fail\n"));
|
||||
rtw_free_xmitframe(pxmitpriv, pxmitframe);
|
||||
|
||||
pxmitpriv->tx_drop++;
|
||||
return true;
|
||||
}
|
||||
|
||||
up(&pxmitpriv->SdioXmitSema);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
s32 rtl8723bs_hal_xmitframe_enqueue(
|
||||
struct adapter *padapter, struct xmit_frame *pxmitframe
|
||||
)
|
||||
{
|
||||
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
|
||||
s32 err;
|
||||
|
||||
if ((err = rtw_xmitframe_enqueue(padapter, pxmitframe)) != _SUCCESS) {
|
||||
rtw_free_xmitframe(pxmitpriv, pxmitframe);
|
||||
|
||||
pxmitpriv->tx_drop++;
|
||||
} else {
|
||||
#ifdef CONFIG_SDIO_TX_TASKLET
|
||||
tasklet_hi_schedule(&pxmitpriv->xmit_tasklet);
|
||||
#else
|
||||
up(&pxmitpriv->SdioXmitSema);
|
||||
#endif
|
||||
}
|
||||
|
||||
return err;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Return
|
||||
*_SUCCESS start thread ok
|
||||
*_FAIL start thread fail
|
||||
*
|
||||
*/
|
||||
s32 rtl8723bs_init_xmit_priv(struct adapter *padapter)
|
||||
{
|
||||
struct xmit_priv *xmitpriv = &padapter->xmitpriv;
|
||||
struct hal_com_data *phal;
|
||||
|
||||
|
||||
phal = GET_HAL_DATA(padapter);
|
||||
|
||||
spin_lock_init(&phal->SdioTxFIFOFreePageLock);
|
||||
sema_init(&xmitpriv->SdioXmitSema, 0);
|
||||
sema_init(&xmitpriv->SdioXmitTerminateSema, 0);
|
||||
|
||||
return _SUCCESS;
|
||||
}
|
||||
|
||||
void rtl8723bs_free_xmit_priv(struct adapter *padapter)
|
||||
{
|
||||
struct hal_com_data *phal;
|
||||
struct xmit_priv *pxmitpriv;
|
||||
struct xmit_buf *pxmitbuf;
|
||||
struct __queue *pqueue;
|
||||
struct list_head *plist, *phead;
|
||||
struct list_head tmplist;
|
||||
|
||||
|
||||
phal = GET_HAL_DATA(padapter);
|
||||
pxmitpriv = &padapter->xmitpriv;
|
||||
pqueue = &pxmitpriv->pending_xmitbuf_queue;
|
||||
phead = get_list_head(pqueue);
|
||||
INIT_LIST_HEAD(&tmplist);
|
||||
|
||||
spin_lock_bh(&pqueue->lock);
|
||||
if (!list_empty(&pqueue->queue)) {
|
||||
/* Insert tmplist to end of queue, and delete phead */
|
||||
/* then tmplist become head of queue. */
|
||||
list_add_tail(&tmplist, phead);
|
||||
list_del_init(phead);
|
||||
}
|
||||
spin_unlock_bh(&pqueue->lock);
|
||||
|
||||
phead = &tmplist;
|
||||
while (list_empty(phead) == false) {
|
||||
plist = get_next(phead);
|
||||
list_del_init(plist);
|
||||
|
||||
pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list);
|
||||
rtw_free_xmitframe(pxmitpriv, (struct xmit_frame *)pxmitbuf->priv_data);
|
||||
pxmitbuf->priv_data = NULL;
|
||||
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,128 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __INC_HAL8723BPHYCFG_H__
|
||||
#define __INC_HAL8723BPHYCFG_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50 /* us */
|
||||
#define AntennaDiversityValue 0x80 /* Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) */
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
#define MAX_AGGR_NUM 0x07
|
||||
|
||||
|
||||
/*--------------------------Define Parameters End-------------------------------*/
|
||||
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
/*------------------------------Define structure End----------------------------*/
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
u32
|
||||
PHY_QueryBBReg_8723B(
|
||||
struct adapter *Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetBBReg_8723B(
|
||||
struct adapter *Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
u32
|
||||
PHY_QueryRFReg_8723B(
|
||||
struct adapter * Adapter,
|
||||
u8 eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetRFReg_8723B(
|
||||
struct adapter * Adapter,
|
||||
u8 eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
/* MAC/BB/RF HAL config */
|
||||
int PHY_BBConfig8723B(struct adapter *Adapter );
|
||||
|
||||
int PHY_RFConfig8723B(struct adapter *Adapter );
|
||||
|
||||
s32 PHY_MACConfig8723B(struct adapter *padapter);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex_8723B(
|
||||
struct adapter * Adapter,
|
||||
u32 PowerIndex,
|
||||
u8 RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
u8
|
||||
PHY_GetTxPowerIndex_8723B(
|
||||
struct adapter * padapter,
|
||||
u8 RFPath,
|
||||
u8 Rate,
|
||||
enum CHANNEL_WIDTH BandWidth,
|
||||
u8 Channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_GetTxPowerLevel8723B(
|
||||
struct adapter * Adapter,
|
||||
s32* powerlevel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerLevel8723B(
|
||||
struct adapter * Adapter,
|
||||
u8 channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetBWMode8723B(
|
||||
struct adapter * Adapter,
|
||||
enum CHANNEL_WIDTH Bandwidth, /* 20M or 40M */
|
||||
unsigned char Offset /* Upper, Lower, or Don't care */
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SwChnl8723B(/* Call after initialization */
|
||||
struct adapter *Adapter,
|
||||
u8 channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetSwChnlBWMode8723B(
|
||||
struct adapter * Adapter,
|
||||
u8 channel,
|
||||
enum CHANNEL_WIDTH Bandwidth,
|
||||
u8 Offset40,
|
||||
u8 Offset80
|
||||
);
|
||||
|
||||
/*--------------------------Exported Function prototype End---------------------*/
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __INC_HAL8723BPHYREG_H__
|
||||
#define __INC_HAL8723BPHYREG_H__
|
||||
|
||||
#include <Hal8192CPhyReg.h>
|
||||
|
||||
/* BB Register Definition */
|
||||
/* */
|
||||
/* 4. Page9(0x900) */
|
||||
/* */
|
||||
#define rDPDT_control 0x92c
|
||||
#define rfe_ctrl_anta_src 0x930
|
||||
#define rS0S1_PathSwitch 0x948
|
||||
#define AGC_table_select 0xb2c
|
||||
|
||||
/* */
|
||||
/* PageB(0xB00) */
|
||||
/* */
|
||||
#define rPdp_AntA 0xb00
|
||||
#define rPdp_AntA_4 0xb04
|
||||
#define rPdp_AntA_8 0xb08
|
||||
#define rPdp_AntA_C 0xb0c
|
||||
#define rPdp_AntA_10 0xb10
|
||||
#define rPdp_AntA_14 0xb14
|
||||
#define rPdp_AntA_18 0xb18
|
||||
#define rPdp_AntA_1C 0xb1c
|
||||
#define rPdp_AntA_20 0xb20
|
||||
#define rPdp_AntA_24 0xb24
|
||||
|
||||
#define rConfig_Pmpd_AntA 0xb28
|
||||
#define rConfig_ram64x16 0xb2c
|
||||
|
||||
#define rBndA 0xb30
|
||||
#define rHssiPar 0xb34
|
||||
|
||||
#define rConfig_AntA 0xb68
|
||||
#define rConfig_AntB 0xb6c
|
||||
|
||||
#define rPdp_AntB 0xb70
|
||||
#define rPdp_AntB_4 0xb74
|
||||
#define rPdp_AntB_8 0xb78
|
||||
#define rPdp_AntB_C 0xb7c
|
||||
#define rPdp_AntB_10 0xb80
|
||||
#define rPdp_AntB_14 0xb84
|
||||
#define rPdp_AntB_18 0xb88
|
||||
#define rPdp_AntB_1C 0xb8c
|
||||
#define rPdp_AntB_20 0xb90
|
||||
#define rPdp_AntB_24 0xb94
|
||||
|
||||
#define rConfig_Pmpd_AntB 0xb98
|
||||
|
||||
#define rBndB 0xba0
|
||||
|
||||
#define rAPK 0xbd8
|
||||
#define rPm_Rx0_AntA 0xbdc
|
||||
#define rPm_Rx1_AntA 0xbe0
|
||||
#define rPm_Rx2_AntA 0xbe4
|
||||
#define rPm_Rx3_AntA 0xbe8
|
||||
#define rPm_Rx0_AntB 0xbec
|
||||
#define rPm_Rx1_AntB 0xbf0
|
||||
#define rPm_Rx2_AntB 0xbf4
|
||||
#define rPm_Rx3_AntB 0xbf8
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,232 @@
|
|||
#ifndef REALTEK_POWER_SEQUENCE_8723B
|
||||
#define REALTEK_POWER_SEQUENCE_8723B
|
||||
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 26
|
||||
#define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15
|
||||
#define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723B_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8723B_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8723B_TRANS_ACT_TO_SWLPS_STEPS 22
|
||||
#define RTL8723B_TRANS_SWLPS_TO_ACT_STEPS 15
|
||||
#define RTL8723B_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
|
||||
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital , 1:isolation*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]= 0 and WLSUS_EN 0x04[11]= 0*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]= 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
|
||||
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
|
||||
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
|
||||
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
|
||||
{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
|
||||
{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital , 1:isolation*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8723B_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, omments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8723B_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8723B_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]= 0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_ACT_TO_SWLPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/ \
|
||||
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
|
||||
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/ \
|
||||
{0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */ \
|
||||
{0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */ \
|
||||
{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\
|
||||
{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\
|
||||
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/ \
|
||||
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_SWLPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*. reset MAC rx state machine*/\
|
||||
{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*. reset MAC rx state machine*/\
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \
|
||||
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \
|
||||
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8723B_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS+RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_enter_swlps_flow[RTL8723B_TRANS_ACT_TO_SWLPS_STEPS+RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_leave_swlps_flow[RTL8723B_TRANS_SWLPS_TO_ACT_STEPS+RTL8723B_TRANS_END_STEPS];
|
||||
#endif
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __HALPWRSEQCMD_H__
|
||||
#define __HALPWRSEQCMD_H__
|
||||
|
||||
#include <drv_types.h>
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of cmd: 4 bits */
|
||||
/*---------------------------------------------*/
|
||||
#define PWR_CMD_READ 0x00
|
||||
/* offset: the read register offset */
|
||||
/* msk: the mask of the read value */
|
||||
/* value: N/A, left by 0 */
|
||||
/* note: dirver shall implement this function by read & msk */
|
||||
|
||||
#define PWR_CMD_WRITE 0x01
|
||||
/* offset: the read register offset */
|
||||
/* msk: the mask of the write bits */
|
||||
/* value: write value */
|
||||
/* note: driver shall implement this cmd by read & msk after write */
|
||||
|
||||
#define PWR_CMD_POLLING 0x02
|
||||
/* offset: the read register offset */
|
||||
/* msk: the mask of the polled value */
|
||||
/* value: the value to be polled, masked by the msd field. */
|
||||
/* note: driver shall implement this cmd by */
|
||||
/* do{ */
|
||||
/* if ((Read(offset) & msk) == (value & msk)) */
|
||||
/* break; */
|
||||
/* } while (not timeout); */
|
||||
|
||||
#define PWR_CMD_DELAY 0x03
|
||||
/* offset: the value to delay */
|
||||
/* msk: N/A */
|
||||
/* value: the unit of delay, 0: us, 1: ms */
|
||||
|
||||
#define PWR_CMD_END 0x04
|
||||
/* offset: N/A */
|
||||
/* msk: N/A */
|
||||
/* value: N/A */
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of base: 4 bits */
|
||||
/*---------------------------------------------*/
|
||||
/* define the base address of each block */
|
||||
#define PWR_BASEADDR_MAC 0x00
|
||||
#define PWR_BASEADDR_USB 0x01
|
||||
#define PWR_BASEADDR_PCIE 0x02
|
||||
#define PWR_BASEADDR_SDIO 0x03
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of interface_msk: 4 bits */
|
||||
/*---------------------------------------------*/
|
||||
#define PWR_INTF_SDIO_MSK BIT(0)
|
||||
#define PWR_INTF_USB_MSK BIT(1)
|
||||
#define PWR_INTF_PCI_MSK BIT(2)
|
||||
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of fab_msk: 4 bits */
|
||||
/*---------------------------------------------*/
|
||||
#define PWR_FAB_TSMC_MSK BIT(0)
|
||||
#define PWR_FAB_UMC_MSK BIT(1)
|
||||
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of cut_msk: 8 bits */
|
||||
/*---------------------------------------------*/
|
||||
#define PWR_CUT_TESTCHIP_MSK BIT(0)
|
||||
#define PWR_CUT_A_MSK BIT(1)
|
||||
#define PWR_CUT_B_MSK BIT(2)
|
||||
#define PWR_CUT_C_MSK BIT(3)
|
||||
#define PWR_CUT_D_MSK BIT(4)
|
||||
#define PWR_CUT_E_MSK BIT(5)
|
||||
#define PWR_CUT_F_MSK BIT(6)
|
||||
#define PWR_CUT_G_MSK BIT(7)
|
||||
#define PWR_CUT_ALL_MSK 0xFF
|
||||
|
||||
|
||||
typedef enum _PWRSEQ_CMD_DELAY_UNIT_
|
||||
{
|
||||
PWRSEQ_DELAY_US,
|
||||
PWRSEQ_DELAY_MS,
|
||||
} PWRSEQ_DELAY_UNIT;
|
||||
|
||||
typedef struct _WL_PWR_CFG_
|
||||
{
|
||||
u16 offset;
|
||||
u8 cut_msk;
|
||||
u8 fab_msk:4;
|
||||
u8 interface_msk:4;
|
||||
u8 base:4;
|
||||
u8 cmd:4;
|
||||
u8 msk;
|
||||
u8 value;
|
||||
} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
|
||||
|
||||
|
||||
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
|
||||
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
|
||||
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
|
||||
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
|
||||
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
|
||||
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
|
||||
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
|
||||
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
|
||||
|
||||
|
||||
/* */
|
||||
/* Prototype of protected function. */
|
||||
/* */
|
||||
u8 HalPwrSeqCmdParsing(
|
||||
struct adapter * padapter,
|
||||
u8 CutVersion,
|
||||
u8 FabVersion,
|
||||
u8 InterfaceType,
|
||||
WLAN_PWR_CFG PwrCfgCmd[]);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __HAL_VERSION_DEF_H__
|
||||
#define __HAL_VERSION_DEF_H__
|
||||
|
||||
/* HAL_IC_TYPE_E */
|
||||
typedef enum tag_HAL_IC_Type_Definition
|
||||
{
|
||||
CHIP_8192S = 0,
|
||||
CHIP_8188C = 1,
|
||||
CHIP_8192C = 2,
|
||||
CHIP_8192D = 3,
|
||||
CHIP_8723A = 4,
|
||||
CHIP_8188E = 5,
|
||||
CHIP_8812 = 6,
|
||||
CHIP_8821 = 7,
|
||||
CHIP_8723B = 8,
|
||||
CHIP_8192E = 9,
|
||||
}HAL_IC_TYPE_E;
|
||||
|
||||
/* HAL_CHIP_TYPE_E */
|
||||
typedef enum tag_HAL_CHIP_Type_Definition
|
||||
{
|
||||
TEST_CHIP = 0,
|
||||
NORMAL_CHIP = 1,
|
||||
FPGA = 2,
|
||||
}HAL_CHIP_TYPE_E;
|
||||
|
||||
/* HAL_CUT_VERSION_E */
|
||||
typedef enum tag_HAL_Cut_Version_Definition
|
||||
{
|
||||
A_CUT_VERSION = 0,
|
||||
B_CUT_VERSION = 1,
|
||||
C_CUT_VERSION = 2,
|
||||
D_CUT_VERSION = 3,
|
||||
E_CUT_VERSION = 4,
|
||||
F_CUT_VERSION = 5,
|
||||
G_CUT_VERSION = 6,
|
||||
H_CUT_VERSION = 7,
|
||||
I_CUT_VERSION = 8,
|
||||
J_CUT_VERSION = 9,
|
||||
K_CUT_VERSION = 10,
|
||||
}HAL_CUT_VERSION_E;
|
||||
|
||||
/* HAL_Manufacturer */
|
||||
typedef enum tag_HAL_Manufacturer_Version_Definition
|
||||
{
|
||||
CHIP_VENDOR_TSMC = 0,
|
||||
CHIP_VENDOR_UMC = 1,
|
||||
CHIP_VENDOR_SMIC = 2,
|
||||
}HAL_VENDOR_E;
|
||||
|
||||
typedef enum tag_HAL_RF_Type_Definition
|
||||
{
|
||||
RF_TYPE_1T1R = 0,
|
||||
RF_TYPE_1T2R = 1,
|
||||
RF_TYPE_2T2R = 2,
|
||||
RF_TYPE_2T3R = 3,
|
||||
RF_TYPE_2T4R = 4,
|
||||
RF_TYPE_3T3R = 5,
|
||||
RF_TYPE_3T4R = 6,
|
||||
RF_TYPE_4T4R = 7,
|
||||
}HAL_RF_TYPE_E;
|
||||
|
||||
typedef struct tag_HAL_VERSION
|
||||
{
|
||||
HAL_IC_TYPE_E ICType;
|
||||
HAL_CHIP_TYPE_E ChipType;
|
||||
HAL_CUT_VERSION_E CUTVersion;
|
||||
HAL_VENDOR_E VendorType;
|
||||
HAL_RF_TYPE_E RFType;
|
||||
u8 ROMVer;
|
||||
}HAL_VERSION,*PHAL_VERSION;
|
||||
|
||||
/* VERSION_8192C VersionID; */
|
||||
/* HAL_VERSION VersionID; */
|
||||
|
||||
/* Get element */
|
||||
#define GET_CVID_IC_TYPE(version) ((HAL_IC_TYPE_E)((version).ICType) )
|
||||
#define GET_CVID_CHIP_TYPE(version) ((HAL_CHIP_TYPE_E)((version).ChipType) )
|
||||
#define GET_CVID_RF_TYPE(version) ((HAL_RF_TYPE_E)((version).RFType))
|
||||
#define GET_CVID_MANUFACTUER(version) ((HAL_VENDOR_E)((version).VendorType))
|
||||
#define GET_CVID_CUT_VERSION(version) ((HAL_CUT_VERSION_E)((version).CUTVersion))
|
||||
#define GET_CVID_ROM_VERSION(version) (((version).ROMVer) & ROM_VERSION_MASK)
|
||||
|
||||
/* */
|
||||
/* Common Macro. -- */
|
||||
/* */
|
||||
/* HAL_VERSION VersionID */
|
||||
|
||||
/* HAL_CHIP_TYPE_E */
|
||||
#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version) ==TEST_CHIP)? true: false)
|
||||
#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version) ==NORMAL_CHIP)? true: false)
|
||||
|
||||
/* HAL_CUT_VERSION_E */
|
||||
#define IS_A_CUT(version) ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? true : false)
|
||||
#define IS_B_CUT(version) ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true : false)
|
||||
#define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? true : false)
|
||||
#define IS_D_CUT(version) ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? true : false)
|
||||
#define IS_E_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? true : false)
|
||||
#define IS_I_CUT(version) ((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? true : false)
|
||||
#define IS_J_CUT(version) ((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? true : false)
|
||||
#define IS_K_CUT(version) ((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? true : false)
|
||||
|
||||
/* HAL_VENDOR_E */
|
||||
#define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC)? true: false)
|
||||
#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC)? true: false)
|
||||
#define IS_CHIP_VENDOR_SMIC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC)? true: false)
|
||||
|
||||
/* HAL_RF_TYPE_E */
|
||||
#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R)? true : false)
|
||||
#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? true : false)
|
||||
#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? true : false)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* Automatically generated C config: don't edit
|
||||
*/
|
||||
|
||||
/*
|
||||
* Functions Config
|
||||
*/
|
||||
/* define CONFIG_DEBUG_CFG80211 */
|
||||
|
||||
#ifndef CONFIG_WIRELESS_EXT
|
||||
#error CONFIG_WIRELESS_EXT needs to be enabled for this driver to work
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Auto Config Section
|
||||
*/
|
||||
#define LPS_RPWM_WAIT_MS 300
|
||||
#ifndef DISABLE_BB_RF
|
||||
#define DISABLE_BB_RF 0
|
||||
#endif
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
#define HAL_MAC_ENABLE 0
|
||||
#define HAL_BB_ENABLE 0
|
||||
#define HAL_RF_ENABLE 0
|
||||
#else
|
||||
#define HAL_MAC_ENABLE 1
|
||||
#define HAL_BB_ENABLE 1
|
||||
#define HAL_RF_ENABLE 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Platform dependent
|
||||
*/
|
||||
#define WAKEUP_GPIO_IDX 12 /* WIFI Chip Side */
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define CONFIG_GTK_OL
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
/*
|
||||
* Debug Related Config
|
||||
*/
|
||||
#undef CONFIG_DEBUG
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
#define DBG 1 /* for ODM & BTCOEX debug */
|
||||
/*#define CONFIG_DEBUG_RTL871X */
|
||||
#else /* !CONFIG_DEBUG */
|
||||
#define DBG 0 /* for ODM & BTCOEX debug */
|
||||
#endif /* !CONFIG_DEBUG */
|
||||
|
||||
#define CONFIG_PROC_DEBUG
|
||||
|
||||
/* define DBG_XMIT_BUF */
|
||||
/* define DBG_XMIT_BUF_EXT */
|
||||
|
|
@ -0,0 +1,209 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __BASIC_TYPES_H__
|
||||
#define __BASIC_TYPES_H__
|
||||
|
||||
|
||||
#define SUCCESS 0
|
||||
#define FAIL (-1)
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
typedef signed int sint;
|
||||
|
||||
#define FIELD_OFFSET(s, field) ((__kernel_ssize_t)&((s*)(0))->field)
|
||||
|
||||
#define SIZE_PTR __kernel_size_t
|
||||
#define SSIZE_PTR __kernel_ssize_t
|
||||
|
||||
/* port from fw by thomas */
|
||||
/* TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness */
|
||||
|
||||
/*
|
||||
*Call endian free function when
|
||||
* 1. Read/write packet content.
|
||||
* 2. Before write integer to IO.
|
||||
* 3. After read integer from IO.
|
||||
*/
|
||||
|
||||
/* */
|
||||
/* Byte Swapping routine. */
|
||||
/* */
|
||||
#define EF1Byte (u8)
|
||||
#define EF2Byte le16_to_cpu
|
||||
#define EF4Byte le32_to_cpu
|
||||
|
||||
/* Convert little data endian to host ordering */
|
||||
#define EF1BYTE(_val) \
|
||||
((u8)(_val))
|
||||
#define EF2BYTE(_val) \
|
||||
(le16_to_cpu(_val))
|
||||
#define EF4BYTE(_val) \
|
||||
(le32_to_cpu(_val))
|
||||
|
||||
/* Read data from memory */
|
||||
#define READEF1BYTE(_ptr) \
|
||||
EF1BYTE(*((u8 *)(_ptr)))
|
||||
/* Read le16 data from memory and convert to host ordering */
|
||||
#define READEF2BYTE(_ptr) \
|
||||
EF2BYTE(*(_ptr))
|
||||
#define READEF4BYTE(_ptr) \
|
||||
EF4BYTE(*(_ptr))
|
||||
|
||||
/* Write data to memory */
|
||||
#define WRITEEF1BYTE(_ptr, _val) \
|
||||
do { \
|
||||
(*((u8 *)(_ptr))) = EF1BYTE(_val); \
|
||||
} while (0)
|
||||
/* Write le data to memory in host ordering */
|
||||
#define WRITEEF2BYTE(_ptr, _val) \
|
||||
do { \
|
||||
(*((u16 *)(_ptr))) = EF2BYTE(_val); \
|
||||
} while (0)
|
||||
|
||||
#define WRITEEF4BYTE(_ptr, _val) \
|
||||
do { \
|
||||
(*((u32 *)(_ptr))) = EF2BYTE(_val); \
|
||||
} while (0)
|
||||
|
||||
/* Create a bit mask
|
||||
* Examples:
|
||||
* BIT_LEN_MASK_32(0) => 0x00000000
|
||||
* BIT_LEN_MASK_32(1) => 0x00000001
|
||||
* BIT_LEN_MASK_32(2) => 0x00000003
|
||||
* BIT_LEN_MASK_32(32) => 0xFFFFFFFF
|
||||
*/
|
||||
#define BIT_LEN_MASK_32(__bitlen) \
|
||||
(0xFFFFFFFF >> (32 - (__bitlen)))
|
||||
#define BIT_LEN_MASK_16(__bitlen) \
|
||||
(0xFFFF >> (16 - (__bitlen)))
|
||||
#define BIT_LEN_MASK_8(__bitlen) \
|
||||
(0xFF >> (8 - (__bitlen)))
|
||||
|
||||
/* Create an offset bit mask
|
||||
* Examples:
|
||||
* BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
|
||||
* BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
|
||||
*/
|
||||
#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
|
||||
(BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
|
||||
#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
|
||||
(BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
|
||||
#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
|
||||
(BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
|
||||
|
||||
/*Description:
|
||||
* Return 4-byte value in host byte ordering from
|
||||
* 4-byte pointer in little-endian system.
|
||||
*/
|
||||
#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
|
||||
(EF4BYTE(*((__le32 *)(__pstart))))
|
||||
#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
|
||||
(EF2BYTE(*((__le16 *)(__pstart))))
|
||||
#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
|
||||
(EF1BYTE(*((u8 *)(__pstart))))
|
||||
|
||||
/* */
|
||||
/* Description: */
|
||||
/* Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to */
|
||||
/* 4-byte value in host byte ordering. */
|
||||
/* */
|
||||
#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
|
||||
(\
|
||||
(LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
|
||||
BIT_LEN_MASK_32(__bitlen) \
|
||||
)
|
||||
#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
|
||||
(\
|
||||
(LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
|
||||
BIT_LEN_MASK_16(__bitlen) \
|
||||
)
|
||||
#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
|
||||
(\
|
||||
(LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
|
||||
BIT_LEN_MASK_8(__bitlen) \
|
||||
)
|
||||
|
||||
/* */
|
||||
/* Description: */
|
||||
/* Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering */
|
||||
/* and return the result in 4-byte value in host byte ordering. */
|
||||
/* */
|
||||
#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
|
||||
(\
|
||||
LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
|
||||
(~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
|
||||
)
|
||||
#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
|
||||
(\
|
||||
LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
|
||||
(~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
|
||||
)
|
||||
#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
|
||||
(\
|
||||
LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
|
||||
(~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
|
||||
)
|
||||
|
||||
/* */
|
||||
/* Description: */
|
||||
/* Set subfield of little-endian 4-byte value to specified value. */
|
||||
/* */
|
||||
#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
|
||||
*((u32 *)(__pstart)) = \
|
||||
( \
|
||||
LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
|
||||
((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
|
||||
)
|
||||
|
||||
#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
|
||||
*((u16 *)(__pstart)) = \
|
||||
( \
|
||||
LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
|
||||
((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
|
||||
);
|
||||
|
||||
#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
|
||||
*((u8 *)(__pstart)) = EF1BYTE \
|
||||
( \
|
||||
LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
|
||||
((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
|
||||
)
|
||||
|
||||
#define LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
|
||||
(\
|
||||
LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
|
||||
)
|
||||
|
||||
#define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \
|
||||
{ \
|
||||
*((u8 *)(__pStart)) = \
|
||||
EF1Byte(\
|
||||
LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
|
||||
| \
|
||||
((u8)__Value) \
|
||||
); \
|
||||
}
|
||||
|
||||
/* Get the N-bytes aligment offset from the current length */
|
||||
#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
|
||||
|
||||
#define TEST_FLAG(__Flag, __testFlag) (((__Flag) & (__testFlag)) != 0)
|
||||
#define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag)
|
||||
#define CLEAR_FLAG(__Flag, __clearFlag) ((__Flag) &= ~(__clearFlag))
|
||||
#define CLEAR_FLAGS(__Flag) ((__Flag) = 0)
|
||||
#define TEST_FLAGS(__Flag, __testFlags) (((__Flag) & (__testFlags)) == (__testFlags))
|
||||
|
||||
#endif /* __BASIC_TYPES_H__ */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __CMD_OSDEP_H_
|
||||
#define __CMD_OSDEP_H_
|
||||
|
||||
|
||||
extern sint _rtw_init_cmd_priv (struct cmd_priv *pcmdpriv);
|
||||
extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv);
|
||||
extern void _rtw_free_evt_priv (struct evt_priv *pevtpriv);
|
||||
extern void _rtw_free_cmd_priv (struct cmd_priv *pcmdpriv);
|
||||
extern sint _rtw_enqueue_cmd(struct __queue *queue, struct cmd_obj *obj);
|
||||
extern struct cmd_obj *_rtw_dequeue_cmd(struct __queue *queue);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __DRV_CONF_H__
|
||||
#define __DRV_CONF_H__
|
||||
#include "autoconf.h"
|
||||
|
||||
//About USB VENDOR REQ
|
||||
#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
|
||||
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
|
||||
#define CONFIG_USB_VENDOR_REQ_MUTEX
|
||||
#endif
|
||||
#if defined(CONFIG_VENDOR_REQ_RETRY) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
|
||||
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically"
|
||||
#define CONFIG_USB_VENDOR_REQ_MUTEX
|
||||
#endif
|
||||
|
||||
#define DYNAMIC_CAMID_ALLOC
|
||||
|
||||
#ifndef CONFIG_RTW_HIQ_FILTER
|
||||
#define CONFIG_RTW_HIQ_FILTER 1
|
||||
#endif
|
||||
|
||||
//#include <rtl871x_byteorder.h>
|
||||
|
||||
#endif // __DRV_CONF_H__
|
||||
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Reference in New Issue