Merge branch 'late/kirkwood' into late/soc
Merge in the late Kirkwood branch with the OMAP late branch for upstream submission. Final contents described in shared tag. Fixup remove/change conflicts in arch/arm/mach-omap2/devices.c and drivers/spi/spi-omap2-mcspi.c. Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
54d69df584
|
|
@ -0,0 +1,232 @@
|
|||
ARM Marvell SoCs
|
||||
================
|
||||
|
||||
This document lists all the ARM Marvell SoCs that are currently
|
||||
supported in mainline by the Linux kernel. As the Marvell families of
|
||||
SoCs are large and complex, it is hard to understand where the support
|
||||
for a particular SoC is available in the Linux kernel. This document
|
||||
tries to help in understanding where those SoCs are supported, and to
|
||||
match them with their corresponding public datasheet, when available.
|
||||
|
||||
Orion family
|
||||
------------
|
||||
|
||||
Flavors:
|
||||
88F5082
|
||||
88F5181
|
||||
88F5181L
|
||||
88F5182
|
||||
Datasheet : http://www.embeddedarm.com/documentation/third-party/MV88F5182-datasheet.pdf
|
||||
Programmer's User Guide : http://www.embeddedarm.com/documentation/third-party/MV88F5182-opensource-manual.pdf
|
||||
User Manual : http://www.embeddedarm.com/documentation/third-party/MV88F5182-usermanual.pdf
|
||||
88F5281
|
||||
Datasheet : http://www.ocmodshop.com/images/reviews/networking/qnap_ts409u/marvel_88f5281_data_sheet.pdf
|
||||
88F6183
|
||||
Core: Feroceon ARMv5 compatible
|
||||
Linux kernel mach directory: arch/arm/mach-orion5x
|
||||
Linux kernel plat directory: arch/arm/plat-orion
|
||||
|
||||
Kirkwood family
|
||||
---------------
|
||||
|
||||
Flavors:
|
||||
88F6282 a.k.a Armada 300
|
||||
Product Brief : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
|
||||
88F6283 a.k.a Armada 310
|
||||
Product Brief : http://www.marvell.com/embedded-processors/armada-300/assets/armada_310.pdf
|
||||
88F6190
|
||||
Product Brief : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6190-003_WEB.pdf
|
||||
Hardware Spec : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F619x_OpenSource.pdf
|
||||
Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
|
||||
88F6192
|
||||
Product Brief : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6192-003_ver1.pdf
|
||||
Hardware Spec : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F619x_OpenSource.pdf
|
||||
Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
|
||||
88F6182
|
||||
88F6180
|
||||
Product Brief : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6180-003_ver1.pdf
|
||||
Hardware Spec : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6180_OpenSource.pdf
|
||||
Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
|
||||
88F6281
|
||||
Product Brief : http://www.marvell.com/embedded-processors/kirkwood/assets/88F6281-004_ver1.pdf
|
||||
Hardware Spec : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf
|
||||
Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
|
||||
Homepage: http://www.marvell.com/embedded-processors/kirkwood/
|
||||
Core: Feroceon ARMv5 compatible
|
||||
Linux kernel mach directory: arch/arm/mach-kirkwood
|
||||
Linux kernel plat directory: arch/arm/plat-orion
|
||||
|
||||
Discovery family
|
||||
----------------
|
||||
|
||||
Flavors:
|
||||
MV78100
|
||||
Product Brief : http://www.marvell.com/embedded-processors/discovery-innovation/assets/MV78100-003_WEB.pdf
|
||||
Hardware Spec : http://www.marvell.com/embedded-processors/discovery-innovation/assets/HW_MV78100_OpenSource.pdf
|
||||
Functional Spec: http://www.marvell.com/embedded-processors/discovery-innovation/assets/FS_MV76100_78100_78200_OpenSource.pdf
|
||||
MV78200
|
||||
Product Brief : http://www.marvell.com/embedded-processors/discovery-innovation/assets/MV78200-002_WEB.pdf
|
||||
Hardware Spec : http://www.marvell.com/embedded-processors/discovery-innovation/assets/HW_MV78200_OpenSource.pdf
|
||||
Functional Spec: http://www.marvell.com/embedded-processors/discovery-innovation/assets/FS_MV76100_78100_78200_OpenSource.pdf
|
||||
MV76100
|
||||
Not supported by the Linux kernel.
|
||||
|
||||
Core: Feroceon ARMv5 compatible
|
||||
|
||||
Linux kernel mach directory: arch/arm/mach-mv78xx0
|
||||
Linux kernel plat directory: arch/arm/plat-orion
|
||||
|
||||
EBU Armada family
|
||||
-----------------
|
||||
|
||||
Armada 370 Flavors:
|
||||
88F6710
|
||||
88F6707
|
||||
88F6W11
|
||||
|
||||
Armada XP Flavors:
|
||||
MV78230
|
||||
MV78260
|
||||
MV78460
|
||||
|
||||
Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
|
||||
No public datasheet available.
|
||||
|
||||
Core: Sheeva ARMv7 compatible
|
||||
|
||||
Linux kernel mach directory: arch/arm/mach-mvebu
|
||||
Linux kernel plat directory: none
|
||||
|
||||
Avanta family
|
||||
-------------
|
||||
|
||||
Flavors:
|
||||
88F6510
|
||||
88F6530P
|
||||
88F6550
|
||||
88F6560
|
||||
Homepage : http://www.marvell.com/broadband/
|
||||
Product Brief: http://www.marvell.com/broadband/assets/Marvell_Avanta_88F6510_305_060-001_product_brief.pdf
|
||||
No public datasheet available.
|
||||
|
||||
Core: ARMv5 compatible
|
||||
|
||||
Linux kernel mach directory: no code in mainline yet, planned for the future
|
||||
Linux kernel plat directory: no code in mainline yet, planned for the future
|
||||
|
||||
Dove family (application processor)
|
||||
-----------------------------------
|
||||
|
||||
Flavors:
|
||||
88AP510 a.k.a Armada 510
|
||||
Product Brief : http://www.marvell.com/application-processors/armada-500/assets/Marvell_Armada510_SoC.pdf
|
||||
Hardware Spec : http://www.marvell.com/application-processors/armada-500/assets/Armada-510-Hardware-Spec.pdf
|
||||
Functional Spec : http://www.marvell.com/application-processors/armada-500/assets/Armada-510-Functional-Spec.pdf
|
||||
Homepage: http://www.marvell.com/application-processors/armada-500/
|
||||
Core: ARMv7 compatible
|
||||
Directory: arch/arm/mach-dove
|
||||
|
||||
PXA 2xx/3xx/93x/95x family
|
||||
--------------------------
|
||||
|
||||
Flavors:
|
||||
PXA21x, PXA25x, PXA26x
|
||||
Application processor only
|
||||
Core: ARMv5 XScale core
|
||||
PXA270, PXA271, PXA272
|
||||
Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_pb.pdf
|
||||
Design guide : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_design_guide.pdf
|
||||
Developers manual : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_dev_man.pdf
|
||||
Specification : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_emts.pdf
|
||||
Specification update : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec_update.pdf
|
||||
Application processor only
|
||||
Core: ARMv5 XScale core
|
||||
PXA300, PXA310, PXA320
|
||||
PXA 300 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA300_PB_R4.pdf
|
||||
PXA 310 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA310_PB_R4.pdf
|
||||
PXA 320 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA320_PB_R4.pdf
|
||||
Design guide : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Design_Guide.pdf
|
||||
Developers manual : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Developers_Manual.zip
|
||||
Specifications : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_EMTS.pdf
|
||||
Specification Update : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Spec_Update.zip
|
||||
Reference Manual : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_TavorP_BootROM_Ref_Manual.pdf
|
||||
Application processor only
|
||||
Core: ARMv5 XScale core
|
||||
PXA930, PXA935
|
||||
Application processor with Communication processor
|
||||
Core: ARMv5 XScale core
|
||||
PXA955
|
||||
Application processor with Communication processor
|
||||
Core: ARMv7 compatible Sheeva PJ4 core
|
||||
|
||||
Comments:
|
||||
|
||||
* This line of SoCs originates from the XScale family developed by
|
||||
Intel and acquired by Marvell in ~2006. The PXA21x, PXA25x,
|
||||
PXA26x, PXA27x, PXA3xx and PXA93x were developed by Intel, while
|
||||
the later PXA95x were developed by Marvell.
|
||||
|
||||
* Due to their XScale origin, these SoCs have virtually nothing in
|
||||
common with the other (Kirkwood, Dove, etc.) families of Marvell
|
||||
SoCs, except with the MMP/MMP2 family of SoCs.
|
||||
|
||||
Linux kernel mach directory: arch/arm/mach-pxa
|
||||
Linux kernel plat directory: arch/arm/plat-pxa
|
||||
|
||||
MMP/MMP2 family (communication processor)
|
||||
-----------------------------------------
|
||||
|
||||
Flavors:
|
||||
PXA168, a.k.a Armada 168
|
||||
Homepage : http://www.marvell.com/application-processors/armada-100/armada-168.jsp
|
||||
Product brief : http://www.marvell.com/application-processors/armada-100/assets/pxa_168_pb.pdf
|
||||
Hardware manual : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_datasheet.pdf
|
||||
Software manual : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_software_manual.pdf
|
||||
Specification update : http://www.marvell.com/application-processors/armada-100/assets/ARMADA16x_Spec_update.pdf
|
||||
Boot ROM manual : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_ref_manual.pdf
|
||||
App node package : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_app_note_package.pdf
|
||||
Application processor only
|
||||
Core: ARMv5 compatible Marvell PJ1 (Mohawk)
|
||||
PXA910
|
||||
Homepage : http://www.marvell.com/communication-processors/pxa910/
|
||||
Product Brief : http://www.marvell.com/communication-processors/pxa910/assets/Marvell_PXA910_Platform-001_PB_final.pdf
|
||||
Application processor with Communication processor
|
||||
Core: ARMv5 compatible Marvell PJ1 (Mohawk)
|
||||
MMP2, a.k.a Armada 610
|
||||
Product Brief : http://www.marvell.com/application-processors/armada-600/assets/armada610_pb.pdf
|
||||
Application processor only
|
||||
Core: ARMv7 compatible Sheeva PJ4 core
|
||||
|
||||
Comments:
|
||||
|
||||
* This line of SoCs originates from the XScale family developed by
|
||||
Intel and acquired by Marvell in ~2006. All the processors of
|
||||
this MMP/MMP2 family were developed by Marvell.
|
||||
|
||||
* Due to their XScale origin, these SoCs have virtually nothing in
|
||||
common with the other (Kirkwood, Dove, etc.) families of Marvell
|
||||
SoCs, except with the PXA family of SoCs listed above.
|
||||
|
||||
Linux kernel mach directory: arch/arm/mach-mmp
|
||||
Linux kernel plat directory: arch/arm/plat-pxa
|
||||
|
||||
Long-term plans
|
||||
---------------
|
||||
|
||||
* Unify the mach-dove/, mach-mv78xx0/, mach-orion5x/ and
|
||||
mach-kirkwood/ into the mach-mvebu/ to support all SoCs from the
|
||||
Marvell EBU (Engineering Business Unit) in a single mach-<foo>
|
||||
directory. The plat-orion/ would therefore disappear.
|
||||
|
||||
* Unify the mach-mmp/ and mach-pxa/ into the same mach-pxa
|
||||
directory. The plat-pxa/ would therefore disappear.
|
||||
|
||||
Credits
|
||||
-------
|
||||
|
||||
Maen Suleiman <maen@marvell.com>
|
||||
Lior Amsalem <alior@marvell.com>
|
||||
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
Andrew Lunn <andrew@lunn.ch>
|
||||
Nicolas Pitre <nico@fluxnic.net>
|
||||
Eric Miao <eric.y.miao@gmail.com>
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
S3C2410 GPIO Control
|
||||
S3C24XX GPIO Control
|
||||
====================
|
||||
|
||||
Introduction
|
||||
|
|
@ -12,7 +12,7 @@ Introduction
|
|||
of the s3c2410 GPIO system, please read the Samsung provided
|
||||
data-sheet/users manual to find out the complete list.
|
||||
|
||||
See Documentation/arm/Samsung/GPIO.txt for the core implemetation.
|
||||
See Documentation/arm/Samsung/GPIO.txt for the core implementation.
|
||||
|
||||
|
||||
GPIOLIB
|
||||
|
|
@ -41,8 +41,8 @@ GPIOLIB
|
|||
GPIOLIB conversion
|
||||
------------------
|
||||
|
||||
If you need to convert your board or driver to use gpiolib from the exiting
|
||||
s3c2410 api, then here are some notes on the process.
|
||||
If you need to convert your board or driver to use gpiolib from the phased
|
||||
out s3c2410 API, then here are some notes on the process.
|
||||
|
||||
1) If your board is exclusively using an GPIO, say to control peripheral
|
||||
power, then it will require to claim the gpio with gpio_request() before
|
||||
|
|
@ -55,7 +55,7 @@ s3c2410 api, then here are some notes on the process.
|
|||
as they have the same arguments, and can either take the pin specific
|
||||
values, or the more generic special-function-number arguments.
|
||||
|
||||
3) s3c2410_gpio_pullup() changs have the problem that whilst the
|
||||
3) s3c2410_gpio_pullup() changes have the problem that whilst the
|
||||
s3c2410_gpio_pullup(x, 1) can be easily translated to the
|
||||
s3c_gpio_setpull(x, S3C_GPIO_PULL_NONE), the s3c2410_gpio_pullup(x, 0)
|
||||
are not so easy.
|
||||
|
|
@ -74,7 +74,7 @@ s3c2410 api, then here are some notes on the process.
|
|||
when using gpio_get_value() on an output pin (s3c2410_gpio_getpin
|
||||
would return the value the pin is supposed to be outputting).
|
||||
|
||||
6) s3c2410_gpio_getirq() should be directly replacable with the
|
||||
6) s3c2410_gpio_getirq() should be directly replaceable with the
|
||||
gpio_to_irq() call.
|
||||
|
||||
The s3c2410_gpio and gpio_ calls have always operated on the same gpio
|
||||
|
|
@ -105,7 +105,7 @@ PIN Numbers
|
|||
-----------
|
||||
|
||||
Each pin has an unique number associated with it in regs-gpio.h,
|
||||
eg S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell
|
||||
e.g. S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell
|
||||
the GPIO functions which pin is to be used.
|
||||
|
||||
With the conversion to gpiolib, there is no longer a direct conversion
|
||||
|
|
@ -120,31 +120,27 @@ Configuring a pin
|
|||
The following function allows the configuration of a given pin to
|
||||
be changed.
|
||||
|
||||
void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
|
||||
void s3c_gpio_cfgpin(unsigned int pin, unsigned int function);
|
||||
|
||||
Eg:
|
||||
e.g.:
|
||||
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
|
||||
s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
|
||||
s3c_gpio_cfgpin(S3C2410_GPA(0), S3C_GPIO_SFN(1));
|
||||
s3c_gpio_cfgpin(S3C2410_GPE(8), S3C_GPIO_SFN(2));
|
||||
|
||||
which would turn GPA(0) into the lowest Address line A0, and set
|
||||
GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line.
|
||||
|
||||
The s3c_gpio_cfgpin() call is a functional replacement for this call.
|
||||
|
||||
|
||||
Reading the current configuration
|
||||
---------------------------------
|
||||
|
||||
The current configuration of a pin can be read by using:
|
||||
The current configuration of a pin can be read by using standard
|
||||
gpiolib function:
|
||||
|
||||
s3c2410_gpio_getcfg(unsigned int pin);
|
||||
s3c_gpio_getcfg(unsigned int pin);
|
||||
|
||||
The return value will be from the same set of values which can be
|
||||
passed to s3c2410_gpio_cfgpin().
|
||||
|
||||
The s3c_gpio_getcfg() call should be a functional replacement for
|
||||
this call.
|
||||
passed to s3c_gpio_cfgpin().
|
||||
|
||||
|
||||
Configuring a pull-up resistor
|
||||
|
|
@ -154,61 +150,33 @@ Configuring a pull-up resistor
|
|||
pull-up resistors enabled. This can be configured by the following
|
||||
function:
|
||||
|
||||
void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
|
||||
void s3c_gpio_setpull(unsigned int pin, unsigned int to);
|
||||
|
||||
Where the to value is zero to set the pull-up off, and 1 to enable
|
||||
the specified pull-up. Any other values are currently undefined.
|
||||
|
||||
The s3c_gpio_setpull() offers similar functionality, but with the
|
||||
ability to encode whether the pull is up or down. Currently there
|
||||
is no 'just on' state, so up or down must be selected.
|
||||
Where the to value is S3C_GPIO_PULL_NONE to set the pull-up off,
|
||||
and S3C_GPIO_PULL_UP to enable the specified pull-up. Any other
|
||||
values are currently undefined.
|
||||
|
||||
|
||||
Getting the state of a PIN
|
||||
--------------------------
|
||||
Getting and setting the state of a PIN
|
||||
--------------------------------------
|
||||
|
||||
The state of a pin can be read by using the function:
|
||||
|
||||
unsigned int s3c2410_gpio_getpin(unsigned int pin);
|
||||
|
||||
This will return either zero or non-zero. Do not count on this
|
||||
function returning 1 if the pin is set.
|
||||
|
||||
This call is now implemented by the relevant gpiolib calls, convert
|
||||
your board or driver to use gpiolib.
|
||||
|
||||
|
||||
Setting the state of a PIN
|
||||
--------------------------
|
||||
|
||||
The value an pin is outputing can be modified by using the following:
|
||||
|
||||
void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
|
||||
|
||||
Which sets the given pin to the value. Use 0 to write 0, and 1 to
|
||||
set the output to 1.
|
||||
|
||||
This call is now implemented by the relevant gpiolib calls, convert
|
||||
These calls are now implemented by the relevant gpiolib calls, convert
|
||||
your board or driver to use gpiolib.
|
||||
|
||||
|
||||
Getting the IRQ number associated with a PIN
|
||||
--------------------------------------------
|
||||
|
||||
The following function can map the given pin number to an IRQ
|
||||
A standard gpiolib function can map the given pin number to an IRQ
|
||||
number to pass to the IRQ system.
|
||||
|
||||
int s3c2410_gpio_getirq(unsigned int pin);
|
||||
int gpio_to_irq(unsigned int pin);
|
||||
|
||||
Note, not all pins have an IRQ.
|
||||
|
||||
This call is now implemented by the relevant gpiolib calls, convert
|
||||
your board or driver to use gpiolib.
|
||||
|
||||
|
||||
Authour
|
||||
Author
|
||||
-------
|
||||
|
||||
|
||||
Ben Dooks, 03 October 2004
|
||||
Copyright 2004 Ben Dooks, Simtec Electronics
|
||||
|
|
|
|||
|
|
@ -5,14 +5,14 @@ Introduction
|
|||
------------
|
||||
|
||||
This outlines the Samsung GPIO implementation and the architecture
|
||||
specific calls provided alongisde the drivers/gpio core.
|
||||
specific calls provided alongside the drivers/gpio core.
|
||||
|
||||
|
||||
S3C24XX (Legacy)
|
||||
----------------
|
||||
|
||||
See Documentation/arm/Samsung-S3C24XX/GPIO.txt for more information
|
||||
about these devices. Their implementation is being brought into line
|
||||
about these devices. Their implementation has been brought into line
|
||||
with the core samsung implementation described in this document.
|
||||
|
||||
|
||||
|
|
@ -29,7 +29,7 @@ GPIO numbering is synchronised between the Samsung and gpiolib system.
|
|||
PIN configuration
|
||||
-----------------
|
||||
|
||||
Pin configuration is specific to the Samsung architecutre, with each SoC
|
||||
Pin configuration is specific to the Samsung architecture, with each SoC
|
||||
registering the necessary information for the core gpio configuration
|
||||
implementation to configure pins as necessary.
|
||||
|
||||
|
|
@ -38,5 +38,3 @@ driver or machine to change gpio configuration.
|
|||
|
||||
See arch/arm/plat-samsung/include/plat/gpio-cfg.h for more information
|
||||
on these functions.
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -51,6 +51,9 @@ ffc00000 ffefffff DMA memory mapping region. Memory returned
|
|||
ff000000 ffbfffff Reserved for future expansion of DMA
|
||||
mapping region.
|
||||
|
||||
fee00000 feffffff Mapping of PCI I/O space. This is a static
|
||||
mapping within the vmalloc space.
|
||||
|
||||
VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
|
||||
Memory returned by vmalloc/ioremap will
|
||||
be dynamically placed in this region.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,8 @@
|
|||
Broadcom BCM2835 device tree bindings
|
||||
-------------------------------------------
|
||||
|
||||
Boards with the BCM2835 SoC shall have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
compatible = "brcm,bcm2835";
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
* Marvell Tauros2 Cache
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "marvell,tauros2-cache".
|
||||
- marvell,tauros2-cache-features : Specify the features supported for the
|
||||
tauros2 cache.
|
||||
The features including
|
||||
CACHE_TAUROS2_PREFETCH_ON (1 << 0)
|
||||
CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
|
||||
The definition can be found at
|
||||
arch/arm/include/asm/hardware/cache-tauros2.h
|
||||
|
||||
Example:
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,tauros2-cache";
|
||||
marvell,tauros2-cache-features = <0x3>;
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
* MSM Timer
|
||||
|
||||
Properties:
|
||||
|
||||
- compatible : Should at least contain "qcom,msm-timer". More specific
|
||||
properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
|
||||
purpose timer and a debug timer respectively.
|
||||
|
||||
- interrupts : Interrupt indicating a match event.
|
||||
|
||||
- reg : Specifies the base address of the timer registers. The second region
|
||||
specifies an optional register used to configure the clock divider.
|
||||
|
||||
- clock-frequency : The frequency of the timer in Hz.
|
||||
|
||||
Optional:
|
||||
|
||||
- cpu-offset : per-cpu offset used when the timer is accessed without the
|
||||
CPU remapping facilities. The offset is cpu-offset * cpu-nr.
|
||||
|
||||
Example:
|
||||
|
||||
timer@200a004 {
|
||||
compatible = "qcom,msm-gpt", "qcom,msm-timer";
|
||||
interrupts = <1 2 0x301>;
|
||||
reg = <0x0200a004 0x10>;
|
||||
clock-frequency = <32768>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
|
||||
timer@200a024 {
|
||||
compatible = "qcom,msm-dgt", "qcom,msm-timer";
|
||||
interrupts = <1 3 0x301>;
|
||||
reg = <0x0200a024 0x10>,
|
||||
<0x0200a034 0x4>;
|
||||
clock-frequency = <6750000>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
|
|
@ -36,6 +36,9 @@ Boards:
|
|||
- OMAP3 BeagleBoard : Low cost community board
|
||||
compatible = "ti,omap3-beagle", "ti,omap3"
|
||||
|
||||
- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
|
||||
compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
|
||||
|
||||
- OMAP4 SDP : Software Developement Board
|
||||
compatible = "ti,omap4-sdp", "ti,omap4430"
|
||||
|
||||
|
|
|
|||
|
|
@ -7,8 +7,12 @@ representation in the device tree should be done as under:-
|
|||
Required properties:
|
||||
|
||||
- compatible : should be one of
|
||||
"arm,cortex-a15-pmu"
|
||||
"arm,cortex-a9-pmu"
|
||||
"arm,cortex-a8-pmu"
|
||||
"arm,cortex-a7-pmu"
|
||||
"arm,cortex-a5-pmu"
|
||||
"arm,arm11mpcore-pmu"
|
||||
"arm,arm1176-pmu"
|
||||
"arm,arm1136-pmu"
|
||||
- interrupts : 1 combined interrupt or 1 per core.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,76 @@
|
|||
* Clock bindings for Freescale i.MX23
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx23-clkctrl"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX23
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
------------------
|
||||
ref_xtal 0
|
||||
pll 1
|
||||
ref_cpu 2
|
||||
ref_emi 3
|
||||
ref_pix 4
|
||||
ref_io 5
|
||||
saif_sel 6
|
||||
lcdif_sel 7
|
||||
gpmi_sel 8
|
||||
ssp_sel 9
|
||||
emi_sel 10
|
||||
cpu 11
|
||||
etm_sel 12
|
||||
cpu_pll 13
|
||||
cpu_xtal 14
|
||||
hbus 15
|
||||
xbus 16
|
||||
lcdif_div 17
|
||||
ssp_div 18
|
||||
gpmi_div 19
|
||||
emi_pll 20
|
||||
emi_xtal 21
|
||||
etm_div 22
|
||||
saif_div 23
|
||||
clk32k_div 24
|
||||
rtc 25
|
||||
adc 26
|
||||
spdif_div 27
|
||||
clk32k 28
|
||||
dri 29
|
||||
pwm 30
|
||||
filt 31
|
||||
uart 32
|
||||
ssp 33
|
||||
gpmi 34
|
||||
spdif 35
|
||||
emi 36
|
||||
saif 37
|
||||
lcdif 38
|
||||
etm 39
|
||||
usb 40
|
||||
usb_pwr 41
|
||||
|
||||
Examples:
|
||||
|
||||
clks: clkctrl@80040000 {
|
||||
compatible = "fsl,imx23-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names =
|
||||
...
|
||||
"uart", /* 32 */
|
||||
...
|
||||
"end_of_list";
|
||||
};
|
||||
|
||||
auart0: serial@8006c000 {
|
||||
compatible = "fsl,imx23-auart";
|
||||
reg = <0x8006c000 0x2000>;
|
||||
interrupts = <24 25 23>;
|
||||
clocks = <&clks 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
* Clock bindings for Freescale i.MX28
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx28-clkctrl"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX28
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
------------------
|
||||
ref_xtal 0
|
||||
pll0 1
|
||||
pll1 2
|
||||
pll2 3
|
||||
ref_cpu 4
|
||||
ref_emi 5
|
||||
ref_io0 6
|
||||
ref_io1 7
|
||||
ref_pix 8
|
||||
ref_hsadc 9
|
||||
ref_gpmi 10
|
||||
saif0_sel 11
|
||||
saif1_sel 12
|
||||
gpmi_sel 13
|
||||
ssp0_sel 14
|
||||
ssp1_sel 15
|
||||
ssp2_sel 16
|
||||
ssp3_sel 17
|
||||
emi_sel 18
|
||||
etm_sel 19
|
||||
lcdif_sel 20
|
||||
cpu 21
|
||||
ptp_sel 22
|
||||
cpu_pll 23
|
||||
cpu_xtal 24
|
||||
hbus 25
|
||||
xbus 26
|
||||
ssp0_div 27
|
||||
ssp1_div 28
|
||||
ssp2_div 29
|
||||
ssp3_div 30
|
||||
gpmi_div 31
|
||||
emi_pll 32
|
||||
emi_xtal 33
|
||||
lcdif_div 34
|
||||
etm_div 35
|
||||
ptp 36
|
||||
saif0_div 37
|
||||
saif1_div 38
|
||||
clk32k_div 39
|
||||
rtc 40
|
||||
lradc 41
|
||||
spdif_div 42
|
||||
clk32k 43
|
||||
pwm 44
|
||||
uart 45
|
||||
ssp0 46
|
||||
ssp1 47
|
||||
ssp2 48
|
||||
ssp3 49
|
||||
gpmi 50
|
||||
spdif 51
|
||||
emi 52
|
||||
saif0 53
|
||||
saif1 54
|
||||
lcdif 55
|
||||
etm 56
|
||||
fec 57
|
||||
can0 58
|
||||
can1 59
|
||||
usb0 60
|
||||
usb1 61
|
||||
usb0_pwr 62
|
||||
usb1_pwr 63
|
||||
enet_out 64
|
||||
|
||||
Examples:
|
||||
|
||||
clks: clkctrl@80040000 {
|
||||
compatible = "fsl,imx28-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names =
|
||||
...
|
||||
"uart", /* 45 */
|
||||
...
|
||||
"end_of_list";
|
||||
};
|
||||
|
||||
auart0: serial@8006a000 {
|
||||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x8006a000 0x2000>;
|
||||
interrupts = <112 70 71>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,222 @@
|
|||
* Clock bindings for Freescale i.MX6 Quad
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6q-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain CCM interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
dummy 0
|
||||
ckil 1
|
||||
ckih 2
|
||||
osc 3
|
||||
pll2_pfd0_352m 4
|
||||
pll2_pfd1_594m 5
|
||||
pll2_pfd2_396m 6
|
||||
pll3_pfd0_720m 7
|
||||
pll3_pfd1_540m 8
|
||||
pll3_pfd2_508m 9
|
||||
pll3_pfd3_454m 10
|
||||
pll2_198m 11
|
||||
pll3_120m 12
|
||||
pll3_80m 13
|
||||
pll3_60m 14
|
||||
twd 15
|
||||
step 16
|
||||
pll1_sw 17
|
||||
periph_pre 18
|
||||
periph2_pre 19
|
||||
periph_clk2_sel 20
|
||||
periph2_clk2_sel 21
|
||||
axi_sel 22
|
||||
esai_sel 23
|
||||
asrc_sel 24
|
||||
spdif_sel 25
|
||||
gpu2d_axi 26
|
||||
gpu3d_axi 27
|
||||
gpu2d_core_sel 28
|
||||
gpu3d_core_sel 29
|
||||
gpu3d_shader_sel 30
|
||||
ipu1_sel 31
|
||||
ipu2_sel 32
|
||||
ldb_di0_sel 33
|
||||
ldb_di1_sel 34
|
||||
ipu1_di0_pre_sel 35
|
||||
ipu1_di1_pre_sel 36
|
||||
ipu2_di0_pre_sel 37
|
||||
ipu2_di1_pre_sel 38
|
||||
ipu1_di0_sel 39
|
||||
ipu1_di1_sel 40
|
||||
ipu2_di0_sel 41
|
||||
ipu2_di1_sel 42
|
||||
hsi_tx_sel 43
|
||||
pcie_axi_sel 44
|
||||
ssi1_sel 45
|
||||
ssi2_sel 46
|
||||
ssi3_sel 47
|
||||
usdhc1_sel 48
|
||||
usdhc2_sel 49
|
||||
usdhc3_sel 50
|
||||
usdhc4_sel 51
|
||||
enfc_sel 52
|
||||
emi_sel 53
|
||||
emi_slow_sel 54
|
||||
vdo_axi_sel 55
|
||||
vpu_axi_sel 56
|
||||
cko1_sel 57
|
||||
periph 58
|
||||
periph2 59
|
||||
periph_clk2 60
|
||||
periph2_clk2 61
|
||||
ipg 62
|
||||
ipg_per 63
|
||||
esai_pred 64
|
||||
esai_podf 65
|
||||
asrc_pred 66
|
||||
asrc_podf 67
|
||||
spdif_pred 68
|
||||
spdif_podf 69
|
||||
can_root 70
|
||||
ecspi_root 71
|
||||
gpu2d_core_podf 72
|
||||
gpu3d_core_podf 73
|
||||
gpu3d_shader 74
|
||||
ipu1_podf 75
|
||||
ipu2_podf 76
|
||||
ldb_di0_podf 77
|
||||
ldb_di1_podf 78
|
||||
ipu1_di0_pre 79
|
||||
ipu1_di1_pre 80
|
||||
ipu2_di0_pre 81
|
||||
ipu2_di1_pre 82
|
||||
hsi_tx_podf 83
|
||||
ssi1_pred 84
|
||||
ssi1_podf 85
|
||||
ssi2_pred 86
|
||||
ssi2_podf 87
|
||||
ssi3_pred 88
|
||||
ssi3_podf 89
|
||||
uart_serial_podf 90
|
||||
usdhc1_podf 91
|
||||
usdhc2_podf 92
|
||||
usdhc3_podf 93
|
||||
usdhc4_podf 94
|
||||
enfc_pred 95
|
||||
enfc_podf 96
|
||||
emi_podf 97
|
||||
emi_slow_podf 98
|
||||
vpu_axi_podf 99
|
||||
cko1_podf 100
|
||||
axi 101
|
||||
mmdc_ch0_axi_podf 102
|
||||
mmdc_ch1_axi_podf 103
|
||||
arm 104
|
||||
ahb 105
|
||||
apbh_dma 106
|
||||
asrc 107
|
||||
can1_ipg 108
|
||||
can1_serial 109
|
||||
can2_ipg 110
|
||||
can2_serial 111
|
||||
ecspi1 112
|
||||
ecspi2 113
|
||||
ecspi3 114
|
||||
ecspi4 115
|
||||
ecspi5 116
|
||||
enet 117
|
||||
esai 118
|
||||
gpt_ipg 119
|
||||
gpt_ipg_per 120
|
||||
gpu2d_core 121
|
||||
gpu3d_core 122
|
||||
hdmi_iahb 123
|
||||
hdmi_isfr 124
|
||||
i2c1 125
|
||||
i2c2 126
|
||||
i2c3 127
|
||||
iim 128
|
||||
enfc 129
|
||||
ipu1 130
|
||||
ipu1_di0 131
|
||||
ipu1_di1 132
|
||||
ipu2 133
|
||||
ipu2_di0 134
|
||||
ldb_di0 135
|
||||
ldb_di1 136
|
||||
ipu2_di1 137
|
||||
hsi_tx 138
|
||||
mlb 139
|
||||
mmdc_ch0_axi 140
|
||||
mmdc_ch1_axi 141
|
||||
ocram 142
|
||||
openvg_axi 143
|
||||
pcie_axi 144
|
||||
pwm1 145
|
||||
pwm2 146
|
||||
pwm3 147
|
||||
pwm4 148
|
||||
per1_bch 149
|
||||
gpmi_bch_apb 150
|
||||
gpmi_bch 151
|
||||
gpmi_io 152
|
||||
gpmi_apb 153
|
||||
sata 154
|
||||
sdma 155
|
||||
spba 156
|
||||
ssi1 157
|
||||
ssi2 158
|
||||
ssi3 159
|
||||
uart_ipg 160
|
||||
uart_serial 161
|
||||
usboh3 162
|
||||
usdhc1 163
|
||||
usdhc2 164
|
||||
usdhc3 165
|
||||
usdhc4 166
|
||||
vdo_axi 167
|
||||
vpu_axi 168
|
||||
cko1 169
|
||||
pll1_sys 170
|
||||
pll2_bus 171
|
||||
pll3_usb_otg 172
|
||||
pll4_audio 173
|
||||
pll5_video 174
|
||||
pll6_mlb 175
|
||||
pll7_usb_host 176
|
||||
pll8_enet 177
|
||||
ssi1_ipg 178
|
||||
ssi2_ipg 179
|
||||
ssi3_ipg 180
|
||||
rom 181
|
||||
usbphy1 182
|
||||
usbphy2 183
|
||||
ldb_di0_div_3_5 184
|
||||
ldb_di1_div_3_5 185
|
||||
|
||||
Examples:
|
||||
|
||||
clks: ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 0x04 0 88 0x04>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = ...
|
||||
"uart_ipg",
|
||||
"uart_serial",
|
||||
...;
|
||||
};
|
||||
|
||||
uart1: serial@02020000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
Marvell Cryptographic Engines And Security Accelerator
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "marvell,orion-crypto"
|
||||
- reg : base physical address of the engine and length of memory mapped
|
||||
region, followed by base physical address of sram and its memory
|
||||
length
|
||||
- reg-names : "regs" , "sram";
|
||||
- interrupts : interrupt number
|
||||
|
||||
Examples:
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "marvell,orion-crypto";
|
||||
reg = <0x30000 0x10000>,
|
||||
<0x4000000 0x800>;
|
||||
reg-names = "regs" , "sram";
|
||||
interrupts = <22>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
Bindings for fan connected to GPIO lines
|
||||
|
||||
Required properties:
|
||||
- compatible : "gpio-fan"
|
||||
- gpios: Specifies the pins that map to bits in the control value,
|
||||
ordered MSB-->LSB.
|
||||
- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the
|
||||
control value that should be set to achieve them. This array
|
||||
must have the RPM values in ascending order.
|
||||
|
||||
Optional properties:
|
||||
- alarm-gpios: This pin going active indicates something is wrong with
|
||||
the fan, and a udev event will be fired.
|
||||
|
||||
Examples:
|
||||
|
||||
gpio_fan {
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&gpio1 14 1
|
||||
&gpio1 13 1>;
|
||||
gpio-fan,speed-map = <0 0
|
||||
3000 1
|
||||
6000 2>;
|
||||
alarm-gpios = <&gpio1 15 1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
* Marvell EBU GPIO controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
|
||||
or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
|
||||
Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
|
||||
370. "marvell,mv78200-gpio" should be used for the Discovery
|
||||
MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
|
||||
SoCs (MV78230, MV78260, MV78460).
|
||||
|
||||
- reg: Address and length of the register set for the device. Only one
|
||||
entry is expected, except for the "marvell,armadaxp-gpio" variant
|
||||
for which two entries are expected: one for the general registers,
|
||||
one for the per-cpu registers.
|
||||
|
||||
- interrupts: The list of interrupts that are used for all the pins
|
||||
managed by this GPIO bank. There can be more than one interrupt
|
||||
(example: 1 interrupt per 8 pins on Armada XP, which means 4
|
||||
interrupts per bank of 32 GPIOs).
|
||||
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. Should be two.
|
||||
The first cell is the GPIO number.
|
||||
The second cell is used to specify flags:
|
||||
bits[3:0] trigger type and level flags:
|
||||
1 = low-to-high edge triggered.
|
||||
2 = high-to-low edge triggered.
|
||||
4 = active high level-sensitive.
|
||||
8 = active low level-sensitive.
|
||||
|
||||
- gpio-controller: marks the device node as a gpio controller
|
||||
|
||||
- ngpios: number of GPIOs this controller has
|
||||
|
||||
- #gpio-cells: Should be two. The first cell is the pin number. The
|
||||
second cell is reserved for flags, unused at the moment.
|
||||
|
||||
Example:
|
||||
|
||||
gpio0: gpio@d0018100 {
|
||||
compatible = "marvell,armadaxp-gpio";
|
||||
reg = <0xd0018100 0x40>,
|
||||
<0xd0018800 0x30>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <16>, <17>, <18>, <19>;
|
||||
};
|
||||
|
|
@ -39,3 +39,46 @@ Example:
|
|||
#gpio-cells = <4>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
|
||||
Samsung S3C24XX GPIO Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Compatible property value should be "samsung,s3c24xx-gpio".
|
||||
|
||||
- reg: Physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
|
||||
should be the following with values derived from the SoC user manual.
|
||||
<[phandle of the gpio controller node]
|
||||
[pin number within the gpio controller]
|
||||
[mux function]
|
||||
[flags and pull up/down]
|
||||
|
||||
Values for gpio specifier:
|
||||
- Pin number: depending on the controller a number from 0 up to 15.
|
||||
- Mux function: Depending on the SoC and the gpio bank the gpio can be set
|
||||
as input, output or a special function
|
||||
- Flags and Pull Up/Down: the values to use differ for the individual SoCs
|
||||
example S3C2416/S3C2450:
|
||||
0 - Pull Up/Down Disabled.
|
||||
1 - Pull Down Enabled.
|
||||
2 - Pull Up Enabled.
|
||||
Bit 16 (0x00010000) - Input is active low.
|
||||
Consult the user manual for the correct values of Mux and Pull Up/Down.
|
||||
|
||||
- gpio-controller: Specifies that the node is a gpio controller.
|
||||
- #address-cells: should be 1.
|
||||
- #size-cells: should be 1.
|
||||
|
||||
Example:
|
||||
|
||||
gpa: gpio-controller@56000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "samsung,s3c24xx-gpio";
|
||||
reg = <0x56000000 0x10>;
|
||||
#gpio-cells = <3>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,6 +11,11 @@ Required properties:
|
|||
- interrupt-controller: Mark the device node as an interrupt controller
|
||||
The first cell is the GPIO number.
|
||||
The second cell is not used.
|
||||
- ti,use-leds : Enables LEDA and LEDB outputs if set
|
||||
- ti,debounce : if n-th bit is set, debounces GPIO-n
|
||||
- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1)
|
||||
- ti,pullups : if n-th bit is set, set a pullup on GPIO-n
|
||||
- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -20,4 +25,5 @@ twl_gpio: gpio {
|
|||
gpio-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
ti,use-leds;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -56,3 +56,4 @@ stm,m41t00 Serial Access TIMEKEEPER
|
|||
stm,m41t62 Serial real-time clock (RTC) with alarm
|
||||
stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
|
||||
ti,tsc2003 I2C Touch-Screen Controller
|
||||
ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
|
||||
|
|
|
|||
|
|
@ -0,0 +1,110 @@
|
|||
BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
|
||||
|
||||
The BCM2835 contains a custom top-level interrupt controller, which supports
|
||||
72 interrupt sources using a 2-level register scheme. The interrupt
|
||||
controller, or the HW block containing it, is referred to occasionally
|
||||
as "armctrl" in the SoC documentation, hence naming of this binding.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "brcm,bcm2835-armctrl-ic.txt"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 2.
|
||||
|
||||
The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
|
||||
pending" register, or 1/2 respectively for interrupts in the "IRQ pending
|
||||
1/2" register.
|
||||
|
||||
The 2nd cell contains the interrupt number within the bank. Valid values
|
||||
are 0..7 for bank 0, and 0..31 for bank 1.
|
||||
|
||||
The interrupt sources are as follows:
|
||||
|
||||
Bank 0:
|
||||
0: ARM_TIMER
|
||||
1: ARM_MAILBOX
|
||||
2: ARM_DOORBELL_0
|
||||
3: ARM_DOORBELL_1
|
||||
4: VPU0_HALTED
|
||||
5: VPU1_HALTED
|
||||
6: ILLEGAL_TYPE0
|
||||
7: ILLEGAL_TYPE1
|
||||
|
||||
Bank 1:
|
||||
0: TIMER0
|
||||
1: TIMER1
|
||||
2: TIMER2
|
||||
3: TIMER3
|
||||
4: CODEC0
|
||||
5: CODEC1
|
||||
6: CODEC2
|
||||
7: VC_JPEG
|
||||
8: ISP
|
||||
9: VC_USB
|
||||
10: VC_3D
|
||||
11: TRANSPOSER
|
||||
12: MULTICORESYNC0
|
||||
13: MULTICORESYNC1
|
||||
14: MULTICORESYNC2
|
||||
15: MULTICORESYNC3
|
||||
16: DMA0
|
||||
17: DMA1
|
||||
18: VC_DMA2
|
||||
19: VC_DMA3
|
||||
20: DMA4
|
||||
21: DMA5
|
||||
22: DMA6
|
||||
23: DMA7
|
||||
24: DMA8
|
||||
25: DMA9
|
||||
26: DMA10
|
||||
27: DMA11
|
||||
28: DMA12
|
||||
29: AUX
|
||||
30: ARM
|
||||
31: VPUDMA
|
||||
|
||||
Bank 2:
|
||||
0: HOSTPORT
|
||||
1: VIDEOSCALER
|
||||
2: CCP2TX
|
||||
3: SDC
|
||||
4: DSI0
|
||||
5: AVE
|
||||
6: CAM0
|
||||
7: CAM1
|
||||
8: HDMI0
|
||||
9: HDMI1
|
||||
10: PIXELVALVE1
|
||||
11: I2CSPISLV
|
||||
12: DSI1
|
||||
13: PWA0
|
||||
14: PWA1
|
||||
15: CPR
|
||||
16: SMI
|
||||
17: GPIO0
|
||||
18: GPIO1
|
||||
19: GPIO2
|
||||
20: GPIO3
|
||||
21: VC_I2C
|
||||
22: VC_SPI
|
||||
23: VC_I2SPCM
|
||||
24: VC_SDIO
|
||||
25: VC_UART
|
||||
26: SLIMBUS
|
||||
27: VEC
|
||||
28: CPG
|
||||
29: RNG
|
||||
30: VC_ARASANSDIO
|
||||
31: AVSPMON
|
||||
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "brcm,bcm2835-armctrl-ic";
|
||||
reg = <0x7e00b200 0x200>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "jedec,lpddr2-timings"
|
||||
- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
|
||||
- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
|
||||
|
||||
Optional properties:
|
||||
|
||||
The following properties represent AC timing parameters from the memory
|
||||
data-sheet of the device for a given speed-bin. All these properties are
|
||||
of type <u32> and the default unit is ps (pico seconds). Parameters with
|
||||
a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
|
||||
- tRCD
|
||||
- tWR
|
||||
- tRAS-min
|
||||
- tRRD
|
||||
- tWTR
|
||||
- tXP
|
||||
- tRTP
|
||||
- tDQSCK-max
|
||||
- tFAW
|
||||
- tZQCS
|
||||
- tZQinit
|
||||
- tRPab
|
||||
- tZQCL
|
||||
- tCKESR
|
||||
- tRAS-max-ns
|
||||
- tDQSCK-max-derated
|
||||
|
||||
Example:
|
||||
|
||||
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <400000000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tWR = <15000>;
|
||||
tRAS-min = <42000>;
|
||||
tRRD = <10000>;
|
||||
tWTR = <7500>;
|
||||
tXP = <7500>;
|
||||
tRTP = <7500>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tZQCS = <90000>;
|
||||
tZQCL = <360000>;
|
||||
tZQinit = <1000000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
|
||||
"jedec,lpddr2-s4"
|
||||
|
||||
"ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
|
||||
|
||||
"ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
|
||||
|
||||
"ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
|
||||
|
||||
- density : <u32> representing density in Mb (Mega bits)
|
||||
|
||||
- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
|
||||
|
||||
Optional properties:
|
||||
|
||||
The following optional properties represent the minimum value of some AC
|
||||
timing parameters of the DDR device in terms of number of clock cycles.
|
||||
These values shall be obtained from the device data-sheet.
|
||||
- tRRD-min-tck
|
||||
- tWTR-min-tck
|
||||
- tXP-min-tck
|
||||
- tRTP-min-tck
|
||||
- tCKE-min-tck
|
||||
- tRPab-min-tck
|
||||
- tRCD-min-tck
|
||||
- tWR-min-tck
|
||||
- tRASmin-min-tck
|
||||
- tCKESR-min-tck
|
||||
- tFAW-min-tck
|
||||
|
||||
Child nodes:
|
||||
- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
|
||||
"lpddr2-timings" provides AC timing parameters of the device for
|
||||
a given speed-bin. The user may provide the timings for as many
|
||||
speed-bins as is required. Please see Documentation/devicetree/
|
||||
bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
|
||||
|
||||
Example:
|
||||
|
||||
elpida_ECB240ABACN : lpddr2 {
|
||||
compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
|
||||
density = <2048>;
|
||||
io-width = <32>;
|
||||
|
||||
tRPab-min-tck = <3>;
|
||||
tRCD-min-tck = <3>;
|
||||
tWR-min-tck = <3>;
|
||||
tRASmin-min-tck = <3>;
|
||||
tRRD-min-tck = <2>;
|
||||
tWTR-min-tck = <2>;
|
||||
tXP-min-tck = <2>;
|
||||
tRTP-min-tck = <2>;
|
||||
tCKE-min-tck = <3>;
|
||||
tCKESR-min-tck = <3>;
|
||||
tFAW-min-tck = <8>;
|
||||
|
||||
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <400000000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tWR = <15000>;
|
||||
tRAS-min = <42000>;
|
||||
tRRD = <10000>;
|
||||
tWTR = <7500>;
|
||||
tXP = <7500>;
|
||||
tRTP = <7500>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tZQCS = <90000>;
|
||||
tZQCL = <360000>;
|
||||
tZQinit = <1000000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
};
|
||||
|
||||
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <200000000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tWR = <15000>;
|
||||
tRAS-min = <42000>;
|
||||
tRRD = <10000>;
|
||||
tWTR = <10000>;
|
||||
tXP = <7500>;
|
||||
tRTP = <7500>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tZQCS = <90000>;
|
||||
tZQCL = <360000>;
|
||||
tZQinit = <1000000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
};
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
* EMIF family of TI SDRAM controllers
|
||||
|
||||
EMIF - External Memory Interface - is an SDRAM controller used in
|
||||
TI SoCs. EMIF supports, based on the IP revision, one or more of
|
||||
DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
|
||||
of the EMIF IP and memory parts attached to it.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
|
||||
is the IP revision of the specific EMIF instance.
|
||||
|
||||
- phy-type : <u32> indicating the DDR phy type. Following are the
|
||||
allowed values
|
||||
<1> : Attila PHY
|
||||
<2> : Intelli PHY
|
||||
|
||||
- device-handle : phandle to a "lpddr2" node representing the memory part
|
||||
|
||||
- ti,hwmods : For TI hwmods processing and omap device creation
|
||||
the value shall be "emif<n>" where <n> is the number of the EMIF
|
||||
instance with base 1.
|
||||
|
||||
Optional properties:
|
||||
- cs1-used : Have this property if CS1 of this EMIF
|
||||
instance has a memory part attached to it. If there is a memory
|
||||
part attached to CS1, it should be the same type as the one on CS0,
|
||||
so there is no need to give the details of this memory part.
|
||||
|
||||
- cal-resistor-per-cs : Have this property if the board has one
|
||||
calibration resistor per chip-select.
|
||||
|
||||
- hw-caps-read-idle-ctrl: Have this property if the controller
|
||||
supports read idle window programming
|
||||
|
||||
- hw-caps-dll-calib-ctrl: Have this property if the controller
|
||||
supports dll calibration control
|
||||
|
||||
- hw-caps-ll-interface : Have this property if the controller
|
||||
has a low latency interface and corresponding interrupt events
|
||||
|
||||
- hw-caps-temp-alert : Have this property if the controller
|
||||
has capability for generating SDRAM temperature alerts
|
||||
|
||||
Example:
|
||||
|
||||
emif1: emif@0x4c000000 {
|
||||
compatible = "ti,emif-4d";
|
||||
ti,hwmods = "emif2";
|
||||
phy-type = <1>;
|
||||
device-handle = <&elpida_ECB240ABACN>;
|
||||
cs1-used;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
};
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
PXA3xx NAND DT bindings
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "marvell,pxa3xx-nand"
|
||||
- reg: The register base for the controller
|
||||
- interrupts: The interrupt to map
|
||||
- #address-cells: Set to <1> if the node includes partitions
|
||||
|
||||
Optional properties:
|
||||
|
||||
- marvell,nand-enable-arbiter: Set to enable the bus arbiter
|
||||
- marvell,nand-keep-config: Set to keep the NAND controller config as set
|
||||
by the bootloader
|
||||
- num-cs: Number of chipselect lines to usw
|
||||
|
||||
Example:
|
||||
|
||||
nand0: nand@43100000 {
|
||||
compatible = "marvell,pxa3xx-nand";
|
||||
reg = <0x43100000 90>;
|
||||
interrupts = <45>;
|
||||
#address-cells = <1>;
|
||||
|
||||
marvell,nand-enable-arbiter;
|
||||
marvell,nand-keep-config;
|
||||
num-cs = <1>;
|
||||
|
||||
/* partitions (optional) */
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
* Marvell Armada 370 SoC pinctrl driver for mpp
|
||||
|
||||
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
|
||||
part and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "marvell,88f6710-pinctrl"
|
||||
|
||||
Available mpp pins/groups and functions:
|
||||
Note: brackets (x) are not part of the mpp name for marvell,function and given
|
||||
only for more detailed description in this document.
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, uart0(rxd)
|
||||
mpp1 1 gpo, uart0(txd)
|
||||
mpp2 2 gpio, i2c0(sck), uart0(txd)
|
||||
mpp3 3 gpio, i2c0(sda), uart0(rxd)
|
||||
mpp4 4 gpio, cpu_pd(vdd)
|
||||
mpp5 5 gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
|
||||
mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
|
||||
mpp7 7 gpo, ge0(txd1), tdm(tdx), audio(lrclk)
|
||||
mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
|
||||
mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
|
||||
mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
|
||||
mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
|
||||
sata1(prsnt), spi1(cs1)
|
||||
mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
|
||||
audio(spdifi)
|
||||
mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
|
||||
audio(rmclk)
|
||||
mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
|
||||
spi0(cs2)
|
||||
mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
|
||||
spi0(cs3)
|
||||
mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
|
||||
mpp17 17 gpo, ge(mdc)
|
||||
mpp18 18 gpio, ge(mdio)
|
||||
mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
|
||||
mpp20 20 gpo, ge0(txd4), ge1(txd0)
|
||||
mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd)
|
||||
mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts)
|
||||
mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
|
||||
mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
|
||||
mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
|
||||
mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
|
||||
mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
|
||||
mpp28 28 gpio, ge0(rxd5), ge1(rxd3)
|
||||
mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
|
||||
mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
|
||||
mpp31 31 gpio, tclk, ge0(txerr)
|
||||
mpp32 32 gpio, spi0(cs0)
|
||||
mpp33 33 gpio, dev(bootcs), spi0(cs0)
|
||||
mpp34 34 gpo, dev(wen0), spi0(mosi)
|
||||
mpp35 35 gpo, dev(oen), spi0(sck)
|
||||
mpp36 36 gpo, dev(a1), spi0(miso)
|
||||
mpp37 37 gpo, dev(a0), sata0(prsnt)
|
||||
mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
|
||||
mpp39 39 gpo, dev(ad0), audio(spdifo)
|
||||
mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts)
|
||||
mpp41 41 gpio, dev(ad2), uart1(rxd)
|
||||
mpp42 42 gpo, dev(ad3), uart1(txd)
|
||||
mpp43 43 gpo, dev(ad4), audio(bclk)
|
||||
mpp44 44 gpo, dev(ad5), audio(mclk)
|
||||
mpp45 45 gpo, dev(ad6), audio(lrclk)
|
||||
mpp46 46 gpo, dev(ad7), audio(sdo)
|
||||
mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo)
|
||||
mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
|
||||
spi0(cs1)
|
||||
mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
|
||||
audio(spdifi)
|
||||
mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
|
||||
audio(rmclk)
|
||||
mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
|
||||
mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
|
||||
mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
|
||||
pcie(clkreq1)
|
||||
mpp54 54 gpo, dev(ad15), tdm(dtx)
|
||||
mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
|
||||
sata0(prsnt)
|
||||
mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
|
||||
pcie(clkreq0), spi1(cs1)
|
||||
mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
|
||||
audio(sdo)
|
||||
mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
|
||||
uart0(rts)
|
||||
mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
|
||||
mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
|
||||
audio(sdi)
|
||||
mpp61 61 gpo, dev(wen1), uart1(txd), audio(rclk)
|
||||
mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
|
||||
audio(mclk), uart0(cts)
|
||||
mpp63 63 gpo, spi0(sck), tclk
|
||||
mpp64 64 gpio, spi0(miso), spi0-1(cs1)
|
||||
mpp65 65 gpio, spi0(mosi), spi0-1(cs2)
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
* Marvell Armada XP SoC pinctrl driver for mpp
|
||||
|
||||
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
|
||||
part and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
|
||||
"marvell,mv78460-pinctrl"
|
||||
|
||||
This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
|
||||
|
||||
Available mpp pins/groups and functions:
|
||||
Note: brackets (x) are not part of the mpp name for marvell,function and given
|
||||
only for more detailed description in this document.
|
||||
|
||||
* Marvell Armada XP (all variants)
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, ge0(txclko), lcd(d0)
|
||||
mpp1 1 gpio, ge0(txd0), lcd(d1)
|
||||
mpp2 2 gpio, ge0(txd1), lcd(d2)
|
||||
mpp3 3 gpio, ge0(txd2), lcd(d3)
|
||||
mpp4 4 gpio, ge0(txd3), lcd(d4)
|
||||
mpp5 5 gpio, ge0(txctl), lcd(d5)
|
||||
mpp6 6 gpio, ge0(rxd0), lcd(d6)
|
||||
mpp7 7 gpio, ge0(rxd1), lcd(d7)
|
||||
mpp8 8 gpio, ge0(rxd2), lcd(d8)
|
||||
mpp9 9 gpio, ge0(rxd3), lcd(d9)
|
||||
mpp10 10 gpio, ge0(rxctl), lcd(d10)
|
||||
mpp11 11 gpio, ge0(rxclk), lcd(d11)
|
||||
mpp12 12 gpio, ge0(txd4), ge1(txd0), lcd(d12)
|
||||
mpp13 13 gpio, ge0(txd5), ge1(txd1), lcd(d13)
|
||||
mpp14 14 gpio, ge0(txd6), ge1(txd2), lcd(d15)
|
||||
mpp15 15 gpio, ge0(txd7), ge1(txd3), lcd(d16)
|
||||
mpp16 16 gpio, ge0(txd7), ge1(txd3), lcd(d16)
|
||||
mpp17 17 gpio, ge0(col), ge1(txctl), lcd(d17)
|
||||
mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
|
||||
mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
|
||||
mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
|
||||
mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
|
||||
mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
|
||||
mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
|
||||
mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
|
||||
mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
|
||||
mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
|
||||
mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig)
|
||||
mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq)
|
||||
mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
|
||||
mpp30 30 gpio, tdm(int1), sd0(clk)
|
||||
mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
|
||||
mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
|
||||
mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat)
|
||||
mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt)
|
||||
mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt)
|
||||
mpp36 36 gpio, spi(mosi)
|
||||
mpp37 37 gpio, spi(miso)
|
||||
mpp38 38 gpio, spi(sck)
|
||||
mpp39 39 gpio, spi(cs0)
|
||||
mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
|
||||
pcie(clkreq0)
|
||||
mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
|
||||
pcie(clkreq1)
|
||||
mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
|
||||
vdd(cpu0-pd)
|
||||
mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
|
||||
vdd(cpu2-3-pd){1}
|
||||
mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
|
||||
mem(bat)
|
||||
mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
|
||||
mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
|
||||
mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
|
||||
ref(clkout)
|
||||
mpp48 48 gpio, tclk, dev(burst/last)
|
||||
|
||||
* Marvell Armada XP (mv78260 and mv78460 only)
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp49 49 gpio, dev(we3)
|
||||
mpp50 50 gpio, dev(we2)
|
||||
mpp51 51 gpio, dev(ad16)
|
||||
mpp52 52 gpio, dev(ad17)
|
||||
mpp53 53 gpio, dev(ad18)
|
||||
mpp54 54 gpio, dev(ad19)
|
||||
mpp55 55 gpio, dev(ad20), vdd(cpu0-pd)
|
||||
mpp56 56 gpio, dev(ad21), vdd(cpu1-pd)
|
||||
mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1}
|
||||
mpp58 58 gpio, dev(ad23)
|
||||
mpp59 59 gpio, dev(ad24)
|
||||
mpp60 60 gpio, dev(ad25)
|
||||
mpp61 61 gpio, dev(ad26)
|
||||
mpp62 62 gpio, dev(ad27)
|
||||
mpp63 63 gpio, dev(ad28)
|
||||
mpp64 64 gpio, dev(ad29)
|
||||
mpp65 65 gpio, dev(ad30)
|
||||
mpp66 66 gpio, dev(ad31)
|
||||
|
||||
Notes:
|
||||
* {1} vdd(cpu2-3-pd) only available on mv78460.
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
* Marvell Dove SoC pinctrl driver for mpp
|
||||
|
||||
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
|
||||
part and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "marvell,dove-pinctrl"
|
||||
- clocks: (optional) phandle of pdma clock
|
||||
|
||||
Available mpp pins/groups and functions:
|
||||
Note: brackets (x) are not part of the mpp name for marvell,function and given
|
||||
only for more detailed description in this document.
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
|
||||
mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
|
||||
mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
|
||||
uart1(rts)
|
||||
mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
|
||||
uart1(cts), lcd-spi(cs1)
|
||||
mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
|
||||
mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
|
||||
mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
|
||||
mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
|
||||
mpp8 8 gpio, pmu, watchdog(rstout)
|
||||
mpp9 9 gpio, pmu, pex1(clkreq)
|
||||
mpp10 10 gpio, pmu, ssp(sclk)
|
||||
mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
|
||||
sdio1(ledctrl), pex0(clkreq)
|
||||
mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
|
||||
mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
|
||||
ssp(extclk)
|
||||
mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
|
||||
mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
|
||||
mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
|
||||
mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
|
||||
ac97-1(sysclko)
|
||||
mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
|
||||
mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
|
||||
mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
|
||||
ac97(sysclko)
|
||||
mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
|
||||
uart1(cts), ssp(sfrm)
|
||||
mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
|
||||
lcd-spi(mosi), uart1(cts), ssp(txd)
|
||||
mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
|
||||
lcd-spi(sck), ssp(sclk)
|
||||
mpp_camera 24-39 gpio, camera
|
||||
mpp_sdio0 40-45 gpio, sdio0
|
||||
mpp_sdio1 46-51 gpio, sdio1
|
||||
mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
|
||||
ssp/twsi
|
||||
mpp_spi0 58-61 gpio, spi0
|
||||
mpp_uart1 62-63 gpio, uart1
|
||||
mpp_nand 64-71 gpo, nand
|
||||
audio0 - i2s, ac97
|
||||
twsi - none, opt1, opt2, opt3
|
||||
|
||||
Notes:
|
||||
* group "mpp_audio1" allows the following functions and gpio pins:
|
||||
- gpio : gpio on pins 52-57
|
||||
- i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
|
||||
- i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57
|
||||
- spdifo : spdifo on pin 57, gpio on pins 52-55
|
||||
- twsi : twsi on pins 56,57, gpio on pins 52-55
|
||||
- ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios
|
||||
- ssp : ssp on pins 52-55, gpio on pins 56,57
|
||||
- ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios
|
||||
* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
|
||||
audio0 pins.
|
||||
* group "twsi" internally muxes twsi controller to the dedicated or option pins.
|
||||
|
|
@ -0,0 +1,279 @@
|
|||
* Marvell Kirkwood SoC pinctrl driver for mpp
|
||||
|
||||
Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
|
||||
part and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "marvell,88f6180-pinctrl",
|
||||
"marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
|
||||
"marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
|
||||
|
||||
This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
|
||||
|
||||
Available mpp pins/groups and functions:
|
||||
Note: brackets (x) are not part of the mpp name for marvell,function and given
|
||||
only for more detailed description in this document.
|
||||
|
||||
* Marvell Kirkwood 88f6180
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, nand(io2), spi(cs)
|
||||
mpp1 1 gpo, nand(io3), spi(mosi)
|
||||
mpp2 2 gpo, nand(io4), spi(sck)
|
||||
mpp3 3 gpo, nand(io5), spi(miso)
|
||||
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
|
||||
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
|
||||
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
|
||||
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
|
||||
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
|
||||
mii(col)
|
||||
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
|
||||
mii(crs)
|
||||
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
|
||||
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
|
||||
ptp-2(trig)
|
||||
mpp12 12 gpo, sdio(clk)
|
||||
mpp13 13 gpio, sdio(cmd), uart1(txd)
|
||||
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
|
||||
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd)
|
||||
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
|
||||
mpp17 17 gpio, sdio(d3)
|
||||
mpp18 18 gpo, nand(io0)
|
||||
mpp19 19 gpo, nand(io1)
|
||||
mpp20 20 gpio, mii(rxerr)
|
||||
mpp21 21 gpio, audio(spdifi)
|
||||
mpp22 22 gpio, audio(spdifo)
|
||||
mpp23 23 gpio, audio(rmclk)
|
||||
mpp24 24 gpio, audio(bclk)
|
||||
mpp25 25 gpio, audio(sdo)
|
||||
mpp26 26 gpio, audio(lrclk)
|
||||
mpp27 27 gpio, audio(mclk)
|
||||
mpp28 28 gpio, audio(sdi)
|
||||
mpp29 29 gpio, audio(extclk)
|
||||
|
||||
* Marvell Kirkwood 88f6190
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, nand(io2), spi(cs)
|
||||
mpp1 1 gpo, nand(io3), spi(mosi)
|
||||
mpp2 2 gpo, nand(io4), spi(sck)
|
||||
mpp3 3 gpo, nand(io5), spi(miso)
|
||||
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
|
||||
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
|
||||
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
|
||||
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
|
||||
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
|
||||
mii(col), mii-1(rxerr)
|
||||
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
|
||||
mii(crs), sata0(prsnt)
|
||||
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig)
|
||||
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
|
||||
ptp-2(trig), sata0(act)
|
||||
mpp12 12 gpo, sdio(clk)
|
||||
mpp13 13 gpio, sdio(cmd), uart1(txd)
|
||||
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
|
||||
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
|
||||
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
|
||||
mpp17 17 gpio, sdio(d3), sata0(prsnt)
|
||||
mpp18 18 gpo, nand(io0)
|
||||
mpp19 19 gpo, nand(io1)
|
||||
mpp20 20 gpio, ge1(txd0)
|
||||
mpp21 21 gpio, ge1(txd1), sata0(act)
|
||||
mpp22 22 gpio, ge1(txd2)
|
||||
mpp23 23 gpio, ge1(txd3), sata0(prsnt)
|
||||
mpp24 24 gpio, ge1(rxd0)
|
||||
mpp25 25 gpio, ge1(rxd1)
|
||||
mpp26 26 gpio, ge1(rxd2)
|
||||
mpp27 27 gpio, ge1(rxd3)
|
||||
mpp28 28 gpio, ge1(col)
|
||||
mpp29 29 gpio, ge1(txclk)
|
||||
mpp30 30 gpio, ge1(rxclk)
|
||||
mpp31 31 gpio, ge1(rxclk)
|
||||
mpp32 32 gpio, ge1(txclko)
|
||||
mpp33 33 gpo, ge1(txclk)
|
||||
mpp34 34 gpio, ge1(txen)
|
||||
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr)
|
||||
|
||||
* Marvell Kirkwood 88f6192
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, nand(io2), spi(cs)
|
||||
mpp1 1 gpo, nand(io3), spi(mosi)
|
||||
mpp2 2 gpo, nand(io4), spi(sck)
|
||||
mpp3 3 gpo, nand(io5), spi(miso)
|
||||
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
|
||||
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
|
||||
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
|
||||
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
|
||||
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
|
||||
mii(col), mii-1(rxerr), sata1(prsnt)
|
||||
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
|
||||
mii(crs), sata0(prsnt)
|
||||
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
|
||||
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
|
||||
ptp-2(trig), sata0(act)
|
||||
mpp12 12 gpo, sdio(clk)
|
||||
mpp13 13 gpio, sdio(cmd), uart1(txd)
|
||||
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
|
||||
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
|
||||
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
|
||||
sata1(act)
|
||||
mpp17 17 gpio, sdio(d3), sata0(prsnt)
|
||||
mpp18 18 gpo, nand(io0)
|
||||
mpp19 19 gpo, nand(io1)
|
||||
mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
|
||||
sata1(act)
|
||||
mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
|
||||
audio(spdifo)
|
||||
mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
|
||||
sata1(prsnt)
|
||||
mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
|
||||
audio(bclk)
|
||||
mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
|
||||
mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
|
||||
mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
|
||||
mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
|
||||
mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
|
||||
mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
|
||||
mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
|
||||
mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
|
||||
mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
|
||||
mpp33 33 gpo, ge1(txclk), tdm(drx)
|
||||
mpp34 34 gpio, ge1(txen), tdm(spi-cs1)
|
||||
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
|
||||
|
||||
* Marvell Kirkwood 88f6281
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, nand(io2), spi(cs)
|
||||
mpp1 1 gpo, nand(io3), spi(mosi)
|
||||
mpp2 2 gpo, nand(io4), spi(sck)
|
||||
mpp3 3 gpo, nand(io5), spi(miso)
|
||||
mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
|
||||
mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
|
||||
mpp6 6 sysrst(out), spi(mosi), ptp(trig)
|
||||
mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
|
||||
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
|
||||
mii(col), mii-1(rxerr), sata1(prsnt)
|
||||
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
|
||||
mii(crs), sata0(prsnt)
|
||||
mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
|
||||
mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
|
||||
ptp-2(trig), sata0(act)
|
||||
mpp12 12 gpio, sdio(clk)
|
||||
mpp13 13 gpio, sdio(cmd), uart1(txd)
|
||||
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
|
||||
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
|
||||
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
|
||||
sata1(act)
|
||||
mpp17 17 gpio, sdio(d3), sata0(prsnt)
|
||||
mpp18 18 gpo, nand(io0)
|
||||
mpp19 19 gpo, nand(io1)
|
||||
mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
|
||||
sata1(act)
|
||||
mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
|
||||
audio(spdifo)
|
||||
mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
|
||||
sata1(prsnt)
|
||||
mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
|
||||
audio(bclk)
|
||||
mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
|
||||
mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
|
||||
mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
|
||||
mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
|
||||
mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
|
||||
mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst)
|
||||
mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk)
|
||||
mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs)
|
||||
mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx)
|
||||
mpp33 33 gpo, ge1(txclk), tdm(drx)
|
||||
mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act)
|
||||
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
|
||||
mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
|
||||
mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
|
||||
mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
|
||||
mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
|
||||
mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo)
|
||||
mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
|
||||
mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
|
||||
mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi)
|
||||
mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk)
|
||||
mpp45 45 gpio, ts(mp9), tdm(pclk)
|
||||
mpp46 46 gpio, ts(mp10), tdm(fs)
|
||||
mpp47 47 gpio, ts(mp11), tdm(drx)
|
||||
mpp48 48 gpio, ts(mp12), tdm(dtx)
|
||||
mpp49 49 gpio, ts(mp9), tdm(rx0ql), ptp(clk)
|
||||
|
||||
* Marvell Kirkwood 88f6282
|
||||
|
||||
name pins functions
|
||||
================================================================================
|
||||
mpp0 0 gpio, nand(io2), spi(cs)
|
||||
mpp1 1 gpo, nand(io3), spi(mosi)
|
||||
mpp2 2 gpo, nand(io4), spi(sck)
|
||||
mpp3 3 gpo, nand(io5), spi(miso)
|
||||
mpp4 4 gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
|
||||
mpp5 5 gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
|
||||
mpp6 6 sysrst(out), spi(mosi)
|
||||
mpp7 7 gpo, spi(cs), lcd(pwm)
|
||||
mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
|
||||
mii-1(rxerr), sata1(prsnt)
|
||||
mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
|
||||
sata0(prsnt)
|
||||
mpp10 10 gpo, spi(sck), uart0(txd), sata1(act)
|
||||
mpp11 11 gpio, spi(miso), uart0(rxd), sata0(act)
|
||||
mpp12 12 gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
|
||||
mpp13 13 gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
|
||||
mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
|
||||
audio(spdifi), audio-1(sdi)
|
||||
mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
|
||||
spi(cs)
|
||||
mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
|
||||
sata1(act), lcd(extclk)
|
||||
mpp17 17 gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
|
||||
mpp18 18 gpo, nand(io0), pex(clkreq)
|
||||
mpp19 19 gpo, nand(io1)
|
||||
mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
|
||||
sata1(act), lcd(d0)
|
||||
mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
|
||||
audio(spdifo), lcd(d1)
|
||||
mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
|
||||
sata1(prsnt), lcd(d2)
|
||||
mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
|
||||
audio(bclk), lcd(d3)
|
||||
mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
|
||||
lcd(d4)
|
||||
mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
|
||||
lcd(d5)
|
||||
mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
|
||||
lcd(d6)
|
||||
mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
|
||||
lcd(d7)
|
||||
mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
|
||||
lcd(d8)
|
||||
mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
|
||||
mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
|
||||
mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
|
||||
mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
|
||||
mpp33 33 gpo, ge1(txclk), tdm(drx), lcd(d13)
|
||||
mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
|
||||
mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
|
||||
lcd(d15)
|
||||
mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
|
||||
mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
|
||||
mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
|
||||
mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
|
||||
mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
|
||||
mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
|
||||
mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
|
||||
mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
|
||||
mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
|
||||
mpp45 45 gpio, ts(mp9), tdm(pclk), lcd(e)
|
||||
mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync)
|
||||
mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync)
|
||||
mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16)
|
||||
mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
* Marvell SoC pinctrl core driver for mpp
|
||||
|
||||
The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
|
||||
(mpp) to a specific function. For each SoC family there is a SoC specific
|
||||
driver using this core driver.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
A Marvell SoC pin configuration node is a node of a group of pins which can
|
||||
be used for a specific device or function. Each node requires one or more
|
||||
mpp pins or group of pins and a mpp function common to all pins.
|
||||
|
||||
Required properties for pinctrl driver:
|
||||
- compatible: "marvell,<soc>-pinctrl"
|
||||
Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
|
||||
|
||||
Required properties for pin configuration node:
|
||||
- marvell,pins: string array of mpp pins or group of pins to be muxed.
|
||||
- marvell,function: string representing a function to mux to for all
|
||||
marvell,pins given in this pin configuration node. The function has to be
|
||||
common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
|
||||
valid pin/pin group names and available function names for each SoC.
|
||||
|
||||
Examples:
|
||||
|
||||
uart1: serial@12100 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <7>;
|
||||
|
||||
pinctrl-0 = <&pmx_uart1_sw>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@d0200 {
|
||||
compatible = "marvell,dove-pinctrl";
|
||||
reg = <0xd0200 0x20>;
|
||||
|
||||
pmx_uart1_sw: pmx-uart1-sw {
|
||||
marvell,pins = "mpp_uart1";
|
||||
marvell,function = "uart1";
|
||||
};
|
||||
};
|
||||
|
|
@ -8,7 +8,8 @@ Required properties:
|
|||
- gpio-controller: mark the device as a GPIO controller
|
||||
- regulators: list of regulators provided by this controller, must have
|
||||
property "regulator-compatible" to match their hardware counterparts:
|
||||
sm[0-2], ldo[0-9] and ldo_rtc
|
||||
sys, sm[0-2], ldo[0-9] and ldo_rtc
|
||||
- sys-supply: The input supply for SYS.
|
||||
- vin-sm0-supply: The input supply for the SM0.
|
||||
- vin-sm1-supply: The input supply for the SM1.
|
||||
- vin-sm2-supply: The input supply for the SM2.
|
||||
|
|
@ -20,6 +21,9 @@ Required properties:
|
|||
|
||||
Each regulator is defined using the standard binding for regulators.
|
||||
|
||||
Note: LDO5 and LDO_RTC is supplied by SYS regulator internally and driver
|
||||
take care of making proper parent child relationship.
|
||||
|
||||
Example:
|
||||
|
||||
pmu: tps6586x@34 {
|
||||
|
|
@ -30,6 +34,7 @@ Example:
|
|||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
|
||||
sys-supply = <&some_reg>;
|
||||
vin-sm0-supply = <&some_reg>;
|
||||
vin-sm1-supply = <&some_reg>;
|
||||
vin-sm2-supply = <&some_reg>;
|
||||
|
|
@ -43,8 +48,16 @@ Example:
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sm0_reg: regulator@0 {
|
||||
sys_reg: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-compatible = "sys";
|
||||
regulator-name = "vdd_sys";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm0_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-compatible = "sm0";
|
||||
regulator-min-microvolt = < 725000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
|
|
@ -52,8 +65,8 @@ Example:
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm1_reg: regulator@1 {
|
||||
reg = <1>;
|
||||
sm1_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-compatible = "sm1";
|
||||
regulator-min-microvolt = < 725000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
|
|
@ -61,8 +74,8 @@ Example:
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
sm2_reg: regulator@2 {
|
||||
reg = <2>;
|
||||
sm2_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
regulator-compatible = "sm2";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <4550000>;
|
||||
|
|
@ -70,72 +83,72 @@ Example:
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo0_reg: regulator@3 {
|
||||
reg = <3>;
|
||||
ldo0_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
regulator-compatible = "ldo0";
|
||||
regulator-name = "PCIE CLK";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@4 {
|
||||
reg = <4>;
|
||||
ldo1_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
regulator-compatible = "ldo1";
|
||||
regulator-min-microvolt = < 725000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@5 {
|
||||
reg = <5>;
|
||||
ldo2_reg: regulator@6 {
|
||||
reg = <6>;
|
||||
regulator-compatible = "ldo2";
|
||||
regulator-min-microvolt = < 725000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@6 {
|
||||
reg = <6>;
|
||||
ldo3_reg: regulator@7 {
|
||||
reg = <7>;
|
||||
regulator-compatible = "ldo3";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@7 {
|
||||
reg = <7>;
|
||||
ldo4_reg: regulator@8 {
|
||||
reg = <8>;
|
||||
regulator-compatible = "ldo4";
|
||||
regulator-min-microvolt = <1700000>;
|
||||
regulator-max-microvolt = <2475000>;
|
||||
};
|
||||
|
||||
ldo5_reg: regulator@8 {
|
||||
reg = <8>;
|
||||
ldo5_reg: regulator@9 {
|
||||
reg = <9>;
|
||||
regulator-compatible = "ldo5";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo6_reg: regulator@9 {
|
||||
reg = <9>;
|
||||
ldo6_reg: regulator@10 {
|
||||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo7_reg: regulator@10 {
|
||||
reg = <10>;
|
||||
ldo7_reg: regulator@11 {
|
||||
reg = <11>;
|
||||
regulator-compatible = "ldo7";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo8_reg: regulator@11 {
|
||||
reg = <11>;
|
||||
ldo8_reg: regulator@12 {
|
||||
reg = <12>;
|
||||
regulator-compatible = "ldo8";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo9_reg: regulator@12 {
|
||||
reg = <12>;
|
||||
ldo9_reg: regulator@13 {
|
||||
reg = <13>;
|
||||
regulator-compatible = "ldo9";
|
||||
regulator-min-microvolt = <1250000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
* PXA RTC
|
||||
|
||||
PXA specific RTC driver.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "marvell,pxa-rtc"
|
||||
|
||||
Examples:
|
||||
|
||||
rtc@40900000 {
|
||||
compatible = "marvell,pxa-rtc";
|
||||
reg = <0x40900000 0x3c>;
|
||||
interrupts = <30 31>;
|
||||
};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
BCM2835 System Timer
|
||||
|
||||
The System Timer peripheral provides four 32-bit timer channels and a
|
||||
single 64-bit free running counter. Each channel has an output compare
|
||||
register, which is compared against the 32 least significant bits of the
|
||||
free running counter values, and generates an interrupt.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "brcm,bcm2835-system-timer.txt"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : A list of 4 interrupt sinks; one per timer channel.
|
||||
- clock-frequency : The frequency of the clock that drives the counter, in Hz.
|
||||
|
||||
Example:
|
||||
|
||||
timer {
|
||||
compatible = "brcm,bcm2835-system-timer";
|
||||
reg = <0x7e003000 0x1000>;
|
||||
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
|
|
@ -10,6 +10,7 @@ apm Applied Micro Circuits Corporation (APM)
|
|||
arm ARM Ltd.
|
||||
atmel Atmel Corporation
|
||||
bosch Bosch Sensortec GmbH
|
||||
brcm Broadcom Corporation
|
||||
cavium Cavium, Inc.
|
||||
chrp Common Hardware Reference Platform
|
||||
cortina Cortina Systems, Inc.
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ arch/arm/mach-ep93xx/ts72xx.c:
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
#include <mach/ep93xx_spi.h>
|
||||
#include <linux/platform_data/spi-ep93xx.h>
|
||||
|
||||
/* this is our GPIO line used for chip select */
|
||||
#define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO9
|
||||
|
|
|
|||
11
MAINTAINERS
11
MAINTAINERS
|
|
@ -595,7 +595,6 @@ M: Will Deacon <will.deacon@arm.com>
|
|||
S: Maintained
|
||||
F: arch/arm/kernel/perf_event*
|
||||
F: arch/arm/oprofile/common.c
|
||||
F: arch/arm/kernel/pmu.c
|
||||
F: arch/arm/include/asm/pmu.h
|
||||
F: arch/arm/kernel/hw_breakpoint.c
|
||||
F: arch/arm/include/asm/hw_breakpoint.h
|
||||
|
|
@ -1613,6 +1612,16 @@ L: netdev@vger.kernel.org
|
|||
S: Supported
|
||||
F: drivers/net/ethernet/broadcom/bnx2x/
|
||||
|
||||
BROADCOM BCM2835 ARM ARCHICTURE
|
||||
M: Stephen Warren <swarren@wwwdotorg.org>
|
||||
L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi.git
|
||||
S: Maintained
|
||||
F: arch/arm/mach-bcm2835/
|
||||
F: arch/arm/boot/dts/bcm2835*
|
||||
F: arch/arm/configs/bcm2835_defconfig
|
||||
F: drivers/*/*bcm2835*
|
||||
|
||||
BROADCOM TG3 GIGABIT ETHERNET DRIVER
|
||||
M: Matt Carlson <mcarlson@broadcom.com>
|
||||
M: Michael Chan <mchan@broadcom.com>
|
||||
|
|
|
|||
246
arch/arm/Kconfig
246
arch/arm/Kconfig
|
|
@ -202,6 +202,13 @@ config ARM_PATCH_PHYS_VIRT
|
|||
this feature (eg, building a kernel for a single machine) and
|
||||
you need to shrink the kernel to the minimal size.
|
||||
|
||||
config NEED_MACH_GPIO_H
|
||||
bool
|
||||
help
|
||||
Select this when mach/gpio.h is required to provide special
|
||||
definitions for this platform. The need for mach/gpio.h should
|
||||
be avoided when possible.
|
||||
|
||||
config NEED_MACH_IO_H
|
||||
bool
|
||||
help
|
||||
|
|
@ -247,39 +254,29 @@ config MMU
|
|||
#
|
||||
choice
|
||||
prompt "ARM system type"
|
||||
default ARCH_VERSATILE
|
||||
default ARCH_MULTIPLATFORM
|
||||
|
||||
config ARCH_SOCFPGA
|
||||
bool "Altera SOCFPGA family"
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_GIC
|
||||
select CACHE_L2X0
|
||||
select CLKDEV_LOOKUP
|
||||
config ARCH_MULTIPLATFORM
|
||||
bool "Allow multiple platforms to be selected"
|
||||
select ARM_PATCH_PHYS_VIRT
|
||||
select AUTO_ZRELADDR
|
||||
select COMMON_CLK
|
||||
select CPU_V7
|
||||
select DW_APB_TIMER
|
||||
select DW_APB_TIMER_OF
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GPIO_PL061 if GPIOLIB
|
||||
select HAVE_ARM_SCU
|
||||
select MULTI_IRQ_HANDLER
|
||||
select SPARSE_IRQ
|
||||
select USE_OF
|
||||
help
|
||||
This enables support for Altera SOCFPGA Cyclone V platform
|
||||
depends on MMU
|
||||
|
||||
config ARCH_INTEGRATOR
|
||||
bool "ARM Ltd. Integrator family"
|
||||
select ARM_AMBA
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select COMMON_CLK
|
||||
select CLK_VERSATILE
|
||||
select COMMON_CLK_VERSATILE
|
||||
select HAVE_TCM
|
||||
select ICST
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select PLAT_VERSATILE
|
||||
select PLAT_VERSATILE_FPGA_IRQ
|
||||
select NEED_MACH_IO_H
|
||||
select NEED_MACH_MEMORY_H
|
||||
select SPARSE_IRQ
|
||||
select MULTI_IRQ_HANDLER
|
||||
|
|
@ -289,13 +286,12 @@ config ARCH_INTEGRATOR
|
|||
config ARCH_REALVIEW
|
||||
bool "ARM Ltd. RealView family"
|
||||
select ARM_AMBA
|
||||
select CLKDEV_LOOKUP
|
||||
select HAVE_MACH_CLKDEV
|
||||
select COMMON_CLK
|
||||
select COMMON_CLK_VERSATILE
|
||||
select ICST
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select PLAT_VERSATILE
|
||||
select PLAT_VERSATILE_CLOCK
|
||||
select PLAT_VERSATILE_CLCD
|
||||
select ARM_TIMER_SP804
|
||||
select GPIO_PL061 if GPIOLIB
|
||||
|
|
@ -312,7 +308,6 @@ config ARCH_VERSATILE
|
|||
select ICST
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select NEED_MACH_IO_H if PCI
|
||||
select PLAT_VERSATILE
|
||||
select PLAT_VERSATILE_CLOCK
|
||||
select PLAT_VERSATILE_CLCD
|
||||
|
|
@ -321,35 +316,35 @@ config ARCH_VERSATILE
|
|||
help
|
||||
This enables support for ARM Ltd Versatile board.
|
||||
|
||||
config ARCH_VEXPRESS
|
||||
bool "ARM Ltd. Versatile Express family"
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_TIMER_SP804
|
||||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_CLK
|
||||
select HAVE_PATA_PLATFORM
|
||||
select ICST
|
||||
select NO_IOPORT
|
||||
select PLAT_VERSATILE
|
||||
select PLAT_VERSATILE_CLCD
|
||||
select REGULATOR_FIXED_VOLTAGE if REGULATOR
|
||||
help
|
||||
This enables support for the ARM Ltd Versatile Express boards.
|
||||
|
||||
config ARCH_AT91
|
||||
bool "Atmel AT91"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select HAVE_CLK
|
||||
select CLKDEV_LOOKUP
|
||||
select IRQ_DOMAIN
|
||||
select NEED_MACH_GPIO_H
|
||||
select NEED_MACH_IO_H if PCCARD
|
||||
help
|
||||
This enables support for systems based on Atmel
|
||||
AT91RM9200 and AT91SAM9* processors.
|
||||
|
||||
config ARCH_BCM2835
|
||||
bool "Broadcom BCM2835 family"
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_ERRATA_411920
|
||||
select ARM_TIMER_SP804
|
||||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select CPU_V6
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MULTI_IRQ_HANDLER
|
||||
select SPARSE_IRQ
|
||||
select USE_OF
|
||||
help
|
||||
This enables support for the Broadcom BCM2835 SoC. This SoC is
|
||||
use in the Raspberry Pi, and Roku 2 devices.
|
||||
|
||||
config ARCH_BCMRING
|
||||
bool "Broadcom BCMRING"
|
||||
depends on MMU
|
||||
|
|
@ -362,24 +357,6 @@ config ARCH_BCMRING
|
|||
help
|
||||
Support for Broadcom's BCMRing platform.
|
||||
|
||||
config ARCH_HIGHBANK
|
||||
bool "Calxeda Highbank-based"
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select ARM_AMBA
|
||||
select ARM_GIC
|
||||
select ARM_TIMER_SP804
|
||||
select CACHE_L2X0
|
||||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_ARM_SCU
|
||||
select HAVE_SMP
|
||||
select SPARSE_IRQ
|
||||
select USE_OF
|
||||
help
|
||||
Support for the Calxeda Highbank SoC based boards.
|
||||
|
||||
config ARCH_CLPS711X
|
||||
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
|
||||
select CPU_ARM720T
|
||||
|
|
@ -407,21 +384,19 @@ config ARCH_GEMINI
|
|||
help
|
||||
Support for the Cortina Systems Gemini family SoCs
|
||||
|
||||
config ARCH_PRIMA2
|
||||
bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
|
||||
select CPU_V7
|
||||
config ARCH_SIRF
|
||||
bool "CSR SiRF"
|
||||
select NO_IOPORT
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select GENERIC_IRQ_CHIP
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select PINCTRL
|
||||
select PINCTRL_SIRF
|
||||
select USE_OF
|
||||
select ZONE_DMA
|
||||
help
|
||||
Support for CSR SiRFSoC ARM Cortex A9 Platform
|
||||
Support for CSR SiRFprimaII/Marco/Polo platforms
|
||||
|
||||
config ARCH_EBSA110
|
||||
bool "EBSA-110"
|
||||
|
|
@ -456,7 +431,7 @@ config ARCH_FOOTBRIDGE
|
|||
select FOOTBRIDGE
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_IDE
|
||||
select NEED_MACH_IO_H
|
||||
select NEED_MACH_IO_H if !MMU
|
||||
select NEED_MACH_MEMORY_H
|
||||
help
|
||||
Support for systems based on the DC21285 companion chip
|
||||
|
|
@ -513,7 +488,6 @@ config ARCH_IOP13XX
|
|||
select PCI
|
||||
select ARCH_SUPPORTS_MSI
|
||||
select VMSPLIT_1G
|
||||
select NEED_MACH_IO_H
|
||||
select NEED_MACH_MEMORY_H
|
||||
select NEED_RET_TO_USER
|
||||
help
|
||||
|
|
@ -523,6 +497,7 @@ config ARCH_IOP32X
|
|||
bool "IOP32x-based"
|
||||
depends on MMU
|
||||
select CPU_XSCALE
|
||||
select NEED_MACH_GPIO_H
|
||||
select NEED_MACH_IO_H
|
||||
select NEED_RET_TO_USER
|
||||
select PLAT_IOP
|
||||
|
|
@ -536,6 +511,7 @@ config ARCH_IOP33X
|
|||
bool "IOP33x-based"
|
||||
depends on MMU
|
||||
select CPU_XSCALE
|
||||
select NEED_MACH_GPIO_H
|
||||
select NEED_MACH_IO_H
|
||||
select NEED_RET_TO_USER
|
||||
select PLAT_IOP
|
||||
|
|
@ -558,26 +534,14 @@ config ARCH_IXP4XX
|
|||
help
|
||||
Support for Intel's IXP4XX (XScale) family of processors.
|
||||
|
||||
config ARCH_MVEBU
|
||||
bool "Marvell SOCs with Device Tree support"
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MULTI_IRQ_HANDLER
|
||||
select SPARSE_IRQ
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_IRQ_CHIP
|
||||
select IRQ_DOMAIN
|
||||
select COMMON_CLK
|
||||
help
|
||||
Support for the Marvell SoC Family with device tree support
|
||||
|
||||
config ARCH_DOVE
|
||||
bool "Marvell Dove"
|
||||
select CPU_V7
|
||||
select PCI
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select NEED_MACH_IO_H
|
||||
select PLAT_ORION
|
||||
select MIGHT_HAVE_PCI
|
||||
select PLAT_ORION_LEGACY
|
||||
select USB_ARCH_HAS_EHCI
|
||||
help
|
||||
Support for the Marvell Dove SoC 88AP510
|
||||
|
||||
|
|
@ -587,8 +551,7 @@ config ARCH_KIRKWOOD
|
|||
select PCI
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select NEED_MACH_IO_H
|
||||
select PLAT_ORION
|
||||
select PLAT_ORION_LEGACY
|
||||
help
|
||||
Support for the following Marvell Kirkwood series SoCs:
|
||||
88F6180, 88F6192 and 88F6281.
|
||||
|
|
@ -614,8 +577,7 @@ config ARCH_MV78XX0
|
|||
select PCI
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select NEED_MACH_IO_H
|
||||
select PLAT_ORION
|
||||
select PLAT_ORION_LEGACY
|
||||
help
|
||||
Support for the following Marvell MV78xx0 series SoCs:
|
||||
MV781x0, MV782x0.
|
||||
|
|
@ -627,8 +589,7 @@ config ARCH_ORION5X
|
|||
select PCI
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select NEED_MACH_IO_H
|
||||
select PLAT_ORION
|
||||
select PLAT_ORION_LEGACY
|
||||
help
|
||||
Support for the following Marvell Orion 5x series SoCs:
|
||||
Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
|
||||
|
|
@ -645,6 +606,7 @@ config ARCH_MMP
|
|||
select PLAT_PXA
|
||||
select SPARSE_IRQ
|
||||
select GENERIC_ALLOCATOR
|
||||
select NEED_MACH_GPIO_H
|
||||
help
|
||||
Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
|
||||
|
||||
|
|
@ -652,8 +614,9 @@ config ARCH_KS8695
|
|||
bool "Micrel/Kendin KS8695"
|
||||
select CPU_ARM922T
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select NEED_MACH_MEMORY_H
|
||||
select CLKSRC_MMIO
|
||||
select GENERIC_CLOCKEVENTS
|
||||
help
|
||||
Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
|
||||
System-on-Chip devices.
|
||||
|
|
@ -683,40 +646,13 @@ config ARCH_TEGRA
|
|||
select HAVE_CLK
|
||||
select HAVE_SMP
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select NEED_MACH_IO_H if PCI
|
||||
select ARCH_HAS_CPUFREQ
|
||||
select USE_OF
|
||||
select COMMON_CLK
|
||||
help
|
||||
This enables support for NVIDIA Tegra based systems (Tegra APX,
|
||||
Tegra 6xx and Tegra 2 series).
|
||||
|
||||
config ARCH_PICOXCELL
|
||||
bool "Picochip picoXcell"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_PATCH_PHYS_VIRT
|
||||
select ARM_VIC
|
||||
select CPU_V6K
|
||||
select DW_APB_TIMER
|
||||
select DW_APB_TIMER_OF
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GENERIC_GPIO
|
||||
select HAVE_TCM
|
||||
select NO_IOPORT
|
||||
select SPARSE_IRQ
|
||||
select USE_OF
|
||||
help
|
||||
This enables support for systems based on the Picochip picoXcell
|
||||
family of Femtocell devices. The picoxcell support requires device tree
|
||||
for all boards.
|
||||
|
||||
config ARCH_PNX4008
|
||||
bool "Philips Nexperia PNX4008 Mobile"
|
||||
select CPU_ARM926T
|
||||
select CLKDEV_LOOKUP
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
help
|
||||
This enables support for Philips PNX4008 mobile platform.
|
||||
|
||||
config ARCH_PXA
|
||||
bool "PXA2xx/PXA3xx-based"
|
||||
depends on MMU
|
||||
|
|
@ -733,6 +669,7 @@ config ARCH_PXA
|
|||
select MULTI_IRQ_HANDLER
|
||||
select ARM_CPU_SUSPEND if PM
|
||||
select HAVE_IDE
|
||||
select NEED_MACH_GPIO_H
|
||||
help
|
||||
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
|
||||
|
||||
|
|
@ -795,6 +732,7 @@ config ARCH_SA1100
|
|||
select CLKDEV_LOOKUP
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select HAVE_IDE
|
||||
select NEED_MACH_GPIO_H
|
||||
select NEED_MACH_MEMORY_H
|
||||
select SPARSE_IRQ
|
||||
help
|
||||
|
|
@ -810,6 +748,7 @@ config ARCH_S3C24XX
|
|||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select NEED_MACH_GPIO_H
|
||||
select NEED_MACH_IO_H
|
||||
help
|
||||
Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
|
||||
|
|
@ -837,6 +776,7 @@ config ARCH_S3C64XX
|
|||
select SAMSUNG_GPIOLIB_4BIT
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select NEED_MACH_GPIO_H
|
||||
help
|
||||
Samsung S3C64XX series based systems
|
||||
|
||||
|
|
@ -851,6 +791,7 @@ config ARCH_S5P64X0
|
|||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
select NEED_MACH_GPIO_H
|
||||
help
|
||||
Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
|
||||
SMDK6450.
|
||||
|
|
@ -865,6 +806,7 @@ config ARCH_S5PC100
|
|||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select NEED_MACH_GPIO_H
|
||||
help
|
||||
Samsung S5PC100 series based systems
|
||||
|
||||
|
|
@ -882,6 +824,7 @@ config ARCH_S5PV210
|
|||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select NEED_MACH_GPIO_H
|
||||
select NEED_MACH_MEMORY_H
|
||||
help
|
||||
Samsung S5PV210/S5PC110 series based systems
|
||||
|
|
@ -899,6 +842,7 @@ config ARCH_EXYNOS
|
|||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
select HAVE_S3C2410_I2C if I2C
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select NEED_MACH_GPIO_H
|
||||
select NEED_MACH_MEMORY_H
|
||||
help
|
||||
Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
|
||||
|
|
@ -912,7 +856,6 @@ config ARCH_SHARK
|
|||
select PCI
|
||||
select ARCH_USES_GETTIMEOFFSET
|
||||
select NEED_MACH_MEMORY_H
|
||||
select NEED_MACH_IO_H
|
||||
help
|
||||
Support for the StrongARM based Digital DNARD machine, also known
|
||||
as "Shark" (<http://www.shark-linux.de/shark.html>).
|
||||
|
|
@ -931,6 +874,7 @@ config ARCH_U300
|
|||
select COMMON_CLK
|
||||
select GENERIC_GPIO
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select SPARSE_IRQ
|
||||
help
|
||||
Support for ST-Ericsson U300 series mobile platforms.
|
||||
|
||||
|
|
@ -971,6 +915,7 @@ config ARCH_DAVINCI
|
|||
select GENERIC_ALLOCATOR
|
||||
select GENERIC_IRQ_CHIP
|
||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select NEED_MACH_GPIO_H
|
||||
help
|
||||
Support for TI's DaVinci platform.
|
||||
|
||||
|
|
@ -983,6 +928,7 @@ config ARCH_OMAP
|
|||
select CLKSRC_MMIO
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select ARCH_HAS_HOLES_MEMORYMODEL
|
||||
select NEED_MACH_GPIO_H
|
||||
help
|
||||
Support for TI's OMAP platform (OMAP1/2/3/4).
|
||||
|
||||
|
|
@ -1022,6 +968,50 @@ config ARCH_ZYNQ
|
|||
Support for Xilinx Zynq ARM Cortex A9 Platform
|
||||
endchoice
|
||||
|
||||
menu "Multiple platform selection"
|
||||
depends on ARCH_MULTIPLATFORM
|
||||
|
||||
comment "CPU Core family selection"
|
||||
|
||||
config ARCH_MULTI_V4
|
||||
bool "ARMv4 based platforms (FA526, StrongARM)"
|
||||
select ARCH_MULTI_V4_V5
|
||||
depends on !ARCH_MULTI_V6_V7
|
||||
|
||||
config ARCH_MULTI_V4T
|
||||
bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
|
||||
select ARCH_MULTI_V4_V5
|
||||
depends on !ARCH_MULTI_V6_V7
|
||||
|
||||
config ARCH_MULTI_V5
|
||||
bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
|
||||
select ARCH_MULTI_V4_V5
|
||||
depends on !ARCH_MULTI_V6_V7
|
||||
|
||||
config ARCH_MULTI_V4_V5
|
||||
bool
|
||||
|
||||
config ARCH_MULTI_V6
|
||||
bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
|
||||
select CPU_V6
|
||||
select ARCH_MULTI_V6_V7
|
||||
|
||||
config ARCH_MULTI_V7
|
||||
bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
|
||||
select CPU_V7
|
||||
select ARCH_VEXPRESS
|
||||
default y
|
||||
select ARCH_MULTI_V6_V7
|
||||
|
||||
config ARCH_MULTI_V6_V7
|
||||
bool
|
||||
|
||||
config ARCH_MULTI_CPU_AUTO
|
||||
def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
|
||||
select ARCH_MULTI_V5
|
||||
|
||||
endmenu
|
||||
|
||||
#
|
||||
# This is sorted alphabetically by mach-* pathname. However, plat-*
|
||||
# Kconfigs may be included either alphabetically (according to the
|
||||
|
|
@ -1049,6 +1039,8 @@ source "arch/arm/mach-gemini/Kconfig"
|
|||
|
||||
source "arch/arm/mach-h720x/Kconfig"
|
||||
|
||||
source "arch/arm/mach-highbank/Kconfig"
|
||||
|
||||
source "arch/arm/mach-integrator/Kconfig"
|
||||
|
||||
source "arch/arm/mach-iop32x/Kconfig"
|
||||
|
|
@ -1084,6 +1076,8 @@ source "arch/arm/mach-omap2/Kconfig"
|
|||
|
||||
source "arch/arm/mach-orion5x/Kconfig"
|
||||
|
||||
source "arch/arm/mach-picoxcell/Kconfig"
|
||||
|
||||
source "arch/arm/mach-pxa/Kconfig"
|
||||
source "arch/arm/plat-pxa/Kconfig"
|
||||
|
||||
|
|
@ -1096,6 +1090,8 @@ source "arch/arm/mach-sa1100/Kconfig"
|
|||
source "arch/arm/plat-samsung/Kconfig"
|
||||
source "arch/arm/plat-s3c24xx/Kconfig"
|
||||
|
||||
source "arch/arm/mach-socfpga/Kconfig"
|
||||
|
||||
source "arch/arm/plat-spear/Kconfig"
|
||||
|
||||
source "arch/arm/mach-s3c24xx/Kconfig"
|
||||
|
|
@ -1118,6 +1114,8 @@ source "arch/arm/mach-exynos/Kconfig"
|
|||
|
||||
source "arch/arm/mach-shmobile/Kconfig"
|
||||
|
||||
source "arch/arm/mach-prima2/Kconfig"
|
||||
|
||||
source "arch/arm/mach-tegra/Kconfig"
|
||||
|
||||
source "arch/arm/mach-u300/Kconfig"
|
||||
|
|
@ -1148,6 +1146,10 @@ config PLAT_ORION
|
|||
select IRQ_DOMAIN
|
||||
select COMMON_CLK
|
||||
|
||||
config PLAT_ORION_LEGACY
|
||||
bool
|
||||
select PLAT_ORION
|
||||
|
||||
config PLAT_PXA
|
||||
bool
|
||||
|
||||
|
|
@ -1179,12 +1181,6 @@ config XSCALE_PMU
|
|||
depends on CPU_XSCALE
|
||||
default y
|
||||
|
||||
config CPU_HAS_PMU
|
||||
depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
|
||||
(!ARCH_OMAP3 || OMAP3_EMU)
|
||||
default y
|
||||
bool
|
||||
|
||||
config MULTI_IRQ_HANDLER
|
||||
bool
|
||||
help
|
||||
|
|
@ -1757,7 +1753,7 @@ config HIGHPTE
|
|||
|
||||
config HW_PERF_EVENTS
|
||||
bool "Enable hardware performance counter support for perf events"
|
||||
depends on PERF_EVENTS && CPU_HAS_PMU
|
||||
depends on PERF_EVENTS
|
||||
default y
|
||||
help
|
||||
Enable hardware performance counter support for perf events. If
|
||||
|
|
@ -2060,7 +2056,7 @@ endchoice
|
|||
|
||||
config XIP_KERNEL
|
||||
bool "Kernel Execute-In-Place from ROM"
|
||||
depends on !ZBOOT_ROM && !ARM_LPAE
|
||||
depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
|
||||
help
|
||||
Execute-In-Place allows the kernel to run from non-volatile storage
|
||||
directly addressable by the CPU, such as NOR flash. This saves RAM
|
||||
|
|
|
|||
|
|
@ -261,6 +261,20 @@ choice
|
|||
Say Y here if you want the debug print routines to direct
|
||||
their output to the serial port on MSM 8960 devices.
|
||||
|
||||
config DEBUG_MVEBU_UART
|
||||
bool "Kernel low-level debugging messages via MVEBU UART"
|
||||
depends on ARCH_MVEBU
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on MVEBU based platforms.
|
||||
|
||||
config DEBUG_PICOXCELL_UART
|
||||
depends on ARCH_PICOXCELL
|
||||
bool "Use PicoXcell UART for low-level debug"
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on PicoXcell based platforms.
|
||||
|
||||
config DEBUG_REALVIEW_STD_PORT
|
||||
bool "RealView Default UART"
|
||||
depends on ARCH_REALVIEW
|
||||
|
|
@ -310,6 +324,13 @@ choice
|
|||
The uncompressor code port configuration is now handled
|
||||
by CONFIG_S3C_LOWLEVEL_UART_PORT.
|
||||
|
||||
config DEBUG_SOCFPGA_UART
|
||||
depends on ARCH_SOCFPGA
|
||||
bool "Use SOCFPGA UART for low-level debug"
|
||||
help
|
||||
Say Y here if you want kernel low-level debugging support
|
||||
on SOCFPGA based platforms.
|
||||
|
||||
config DEBUG_VEXPRESS_UART0_DETECT
|
||||
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
|
||||
depends on ARCH_VEXPRESS && CPU_CP15_MMU
|
||||
|
|
@ -338,6 +359,7 @@ choice
|
|||
|
||||
config DEBUG_LL_UART_NONE
|
||||
bool "No low-level debugging UART"
|
||||
depends on !ARCH_MULTIPLATFORM
|
||||
help
|
||||
Say Y here if your platform doesn't provide a UART option
|
||||
below. This relies on your platform choosing the right UART
|
||||
|
|
@ -373,6 +395,17 @@ choice
|
|||
|
||||
endchoice
|
||||
|
||||
config DEBUG_LL_INCLUDE
|
||||
string
|
||||
default "debug/icedcc.S" if DEBUG_ICEDCC
|
||||
default "debug/highbank.S" if DEBUG_HIGHBANK_UART
|
||||
default "debug/mvebu.S" if DEBUG_MVEBU_UART
|
||||
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
|
||||
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
|
||||
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
|
||||
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
|
||||
default "mach/debug-macro.S"
|
||||
|
||||
config EARLY_PRINTK
|
||||
bool "Early printk"
|
||||
depends on DEBUG_LL
|
||||
|
|
|
|||
|
|
@ -135,84 +135,79 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
|
|||
|
||||
# Machine directory name. This list is sorted alphanumerically
|
||||
# by CONFIG_* macro name.
|
||||
machine-$(CONFIG_ARCH_AT91) := at91
|
||||
machine-$(CONFIG_ARCH_BCMRING) := bcmring
|
||||
machine-$(CONFIG_ARCH_CLPS711X) := clps711x
|
||||
machine-$(CONFIG_ARCH_CNS3XXX) := cns3xxx
|
||||
machine-$(CONFIG_ARCH_DAVINCI) := davinci
|
||||
machine-$(CONFIG_ARCH_DOVE) := dove
|
||||
machine-$(CONFIG_ARCH_EBSA110) := ebsa110
|
||||
machine-$(CONFIG_ARCH_EP93XX) := ep93xx
|
||||
machine-$(CONFIG_ARCH_GEMINI) := gemini
|
||||
machine-$(CONFIG_ARCH_H720X) := h720x
|
||||
machine-$(CONFIG_ARCH_HIGHBANK) := highbank
|
||||
machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
|
||||
machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
|
||||
machine-$(CONFIG_ARCH_IOP32X) := iop32x
|
||||
machine-$(CONFIG_ARCH_IOP33X) := iop33x
|
||||
machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
|
||||
machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
|
||||
machine-$(CONFIG_ARCH_KS8695) := ks8695
|
||||
machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
|
||||
machine-$(CONFIG_ARCH_MMP) := mmp
|
||||
machine-$(CONFIG_ARCH_MSM) := msm
|
||||
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
|
||||
machine-$(CONFIG_ARCH_IMX_V4_V5) := imx
|
||||
machine-$(CONFIG_ARCH_IMX_V6_V7) := imx
|
||||
machine-$(CONFIG_ARCH_MXS) := mxs
|
||||
machine-$(CONFIG_ARCH_MVEBU) := mvebu
|
||||
machine-$(CONFIG_ARCH_NETX) := netx
|
||||
machine-$(CONFIG_ARCH_NOMADIK) := nomadik
|
||||
machine-$(CONFIG_ARCH_OMAP1) := omap1
|
||||
machine-$(CONFIG_ARCH_OMAP2PLUS) := omap2
|
||||
machine-$(CONFIG_ARCH_ORION5X) := orion5x
|
||||
machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell
|
||||
machine-$(CONFIG_ARCH_PNX4008) := pnx4008
|
||||
machine-$(CONFIG_ARCH_PRIMA2) := prima2
|
||||
machine-$(CONFIG_ARCH_PXA) := pxa
|
||||
machine-$(CONFIG_ARCH_REALVIEW) := realview
|
||||
machine-$(CONFIG_ARCH_RPC) := rpc
|
||||
machine-$(CONFIG_ARCH_S3C24XX) := s3c24xx s3c2412 s3c2440
|
||||
machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
|
||||
machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
|
||||
machine-$(CONFIG_ARCH_S5PC100) := s5pc100
|
||||
machine-$(CONFIG_ARCH_S5PV210) := s5pv210
|
||||
machine-$(CONFIG_ARCH_EXYNOS4) := exynos
|
||||
machine-$(CONFIG_ARCH_EXYNOS5) := exynos
|
||||
machine-$(CONFIG_ARCH_SA1100) := sa1100
|
||||
machine-$(CONFIG_ARCH_SHARK) := shark
|
||||
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
|
||||
machine-$(CONFIG_ARCH_TEGRA) := tegra
|
||||
machine-$(CONFIG_ARCH_U300) := u300
|
||||
machine-$(CONFIG_ARCH_U8500) := ux500
|
||||
machine-$(CONFIG_ARCH_VERSATILE) := versatile
|
||||
machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
|
||||
machine-$(CONFIG_ARCH_VT8500) := vt8500
|
||||
machine-$(CONFIG_ARCH_W90X900) := w90x900
|
||||
machine-$(CONFIG_FOOTBRIDGE) := footbridge
|
||||
machine-$(CONFIG_ARCH_SOCFPGA) := socfpga
|
||||
machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
|
||||
machine-$(CONFIG_MACH_SPEAR1340) := spear13xx
|
||||
machine-$(CONFIG_MACH_SPEAR300) := spear3xx
|
||||
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
|
||||
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
|
||||
machine-$(CONFIG_MACH_SPEAR600) := spear6xx
|
||||
machine-$(CONFIG_ARCH_ZYNQ) := zynq
|
||||
machine-$(CONFIG_ARCH_AT91) += at91
|
||||
machine-$(CONFIG_ARCH_BCM2835) += bcm2835
|
||||
machine-$(CONFIG_ARCH_BCMRING) += bcmring
|
||||
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
|
||||
machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
|
||||
machine-$(CONFIG_ARCH_DAVINCI) += davinci
|
||||
machine-$(CONFIG_ARCH_DOVE) += dove
|
||||
machine-$(CONFIG_ARCH_EBSA110) += ebsa110
|
||||
machine-$(CONFIG_ARCH_EP93XX) += ep93xx
|
||||
machine-$(CONFIG_ARCH_GEMINI) += gemini
|
||||
machine-$(CONFIG_ARCH_H720X) += h720x
|
||||
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
|
||||
machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
|
||||
machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
|
||||
machine-$(CONFIG_ARCH_IOP32X) += iop32x
|
||||
machine-$(CONFIG_ARCH_IOP33X) += iop33x
|
||||
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
|
||||
machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood
|
||||
machine-$(CONFIG_ARCH_KS8695) += ks8695
|
||||
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
|
||||
machine-$(CONFIG_ARCH_MMP) += mmp
|
||||
machine-$(CONFIG_ARCH_MSM) += msm
|
||||
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
|
||||
machine-$(CONFIG_ARCH_MXC) += imx
|
||||
machine-$(CONFIG_ARCH_MXS) += mxs
|
||||
machine-$(CONFIG_ARCH_MVEBU) += mvebu
|
||||
machine-$(CONFIG_ARCH_NETX) += netx
|
||||
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
|
||||
machine-$(CONFIG_ARCH_OMAP1) += omap1
|
||||
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
|
||||
machine-$(CONFIG_ARCH_ORION5X) += orion5x
|
||||
machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell
|
||||
machine-$(CONFIG_ARCH_PRIMA2) += prima2
|
||||
machine-$(CONFIG_ARCH_PXA) += pxa
|
||||
machine-$(CONFIG_ARCH_REALVIEW) += realview
|
||||
machine-$(CONFIG_ARCH_RPC) += rpc
|
||||
machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx s3c2412 s3c2440
|
||||
machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx
|
||||
machine-$(CONFIG_ARCH_S5P64X0) += s5p64x0
|
||||
machine-$(CONFIG_ARCH_S5PC100) += s5pc100
|
||||
machine-$(CONFIG_ARCH_S5PV210) += s5pv210
|
||||
machine-$(CONFIG_ARCH_EXYNOS) += exynos
|
||||
machine-$(CONFIG_ARCH_SA1100) += sa1100
|
||||
machine-$(CONFIG_ARCH_SHARK) += shark
|
||||
machine-$(CONFIG_ARCH_SHMOBILE) += shmobile
|
||||
machine-$(CONFIG_ARCH_TEGRA) += tegra
|
||||
machine-$(CONFIG_ARCH_U300) += u300
|
||||
machine-$(CONFIG_ARCH_U8500) += ux500
|
||||
machine-$(CONFIG_ARCH_VERSATILE) += versatile
|
||||
machine-$(CONFIG_ARCH_VEXPRESS) += vexpress
|
||||
machine-$(CONFIG_ARCH_VT8500) += vt8500
|
||||
machine-$(CONFIG_ARCH_W90X900) += w90x900
|
||||
machine-$(CONFIG_FOOTBRIDGE) += footbridge
|
||||
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
|
||||
machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx
|
||||
machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx
|
||||
machine-$(CONFIG_MACH_SPEAR600) += spear6xx
|
||||
machine-$(CONFIG_ARCH_ZYNQ) += zynq
|
||||
|
||||
# Platform directory name. This list is sorted alphanumerically
|
||||
# by CONFIG_* macro name.
|
||||
plat-$(CONFIG_ARCH_MXC) := mxc
|
||||
plat-$(CONFIG_ARCH_OMAP) := omap
|
||||
plat-$(CONFIG_ARCH_S3C64XX) := samsung
|
||||
plat-$(CONFIG_ARCH_ZYNQ) := versatile
|
||||
plat-$(CONFIG_PLAT_IOP) := iop
|
||||
plat-$(CONFIG_PLAT_NOMADIK) := nomadik
|
||||
plat-$(CONFIG_PLAT_ORION) := orion
|
||||
plat-$(CONFIG_PLAT_PXA) := pxa
|
||||
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung
|
||||
plat-$(CONFIG_PLAT_S5P) := samsung
|
||||
plat-$(CONFIG_PLAT_SPEAR) := spear
|
||||
plat-$(CONFIG_PLAT_VERSATILE) := versatile
|
||||
plat-$(CONFIG_ARCH_MXC) += mxc
|
||||
plat-$(CONFIG_ARCH_OMAP) += omap
|
||||
plat-$(CONFIG_ARCH_S3C64XX) += samsung
|
||||
plat-$(CONFIG_ARCH_ZYNQ) += versatile
|
||||
plat-$(CONFIG_PLAT_IOP) += iop
|
||||
plat-$(CONFIG_PLAT_NOMADIK) += nomadik
|
||||
plat-$(CONFIG_PLAT_ORION) += orion
|
||||
plat-$(CONFIG_PLAT_PXA) += pxa
|
||||
plat-$(CONFIG_PLAT_S3C24XX) += s3c24xx samsung
|
||||
plat-$(CONFIG_PLAT_S5P) += samsung
|
||||
plat-$(CONFIG_PLAT_SPEAR) += spear
|
||||
plat-$(CONFIG_PLAT_VERSATILE) += versatile
|
||||
|
||||
ifeq ($(CONFIG_ARCH_EBSA110),y)
|
||||
# This is what happens if you forget the IOCS16 line.
|
||||
|
|
@ -230,15 +225,20 @@ MACHINE := arch/arm/mach-$(word 1,$(machine-y))/
|
|||
else
|
||||
MACHINE :=
|
||||
endif
|
||||
ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
|
||||
MACHINE :=
|
||||
endif
|
||||
|
||||
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
|
||||
platdirs := $(patsubst %,arch/arm/plat-%/,$(plat-y))
|
||||
|
||||
ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
|
||||
ifeq ($(KBUILD_SRC),)
|
||||
KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
|
||||
else
|
||||
KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
|
||||
endif
|
||||
endif
|
||||
|
||||
export TEXT_OFFSET GZFLAGS MMUEXT
|
||||
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@ ifneq ($(MACHINE),)
|
|||
include $(srctree)/$(MACHINE)/Makefile.boot
|
||||
endif
|
||||
|
||||
include $(srctree)/arch/arm/boot/dts/Makefile
|
||||
|
||||
# Note: the following conditions must always be true:
|
||||
# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
|
||||
# PARAMS_PHYS must be within 4MB of ZRELADDR
|
||||
|
|
|
|||
|
|
@ -25,7 +25,13 @@ unsigned int __machine_arch_type;
|
|||
static void putstr(const char *ptr);
|
||||
extern void error(char *x);
|
||||
|
||||
#ifdef CONFIG_ARCH_MULTIPLATFORM
|
||||
static inline void putc(int c) {}
|
||||
static inline void flush(void) {}
|
||||
static inline void arch_decomp_setup(void) {}
|
||||
#else
|
||||
#include <mach/uncompress.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEBUG_ICEDCC
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,106 @@
|
|||
ifeq ($(CONFIG_OF),y)
|
||||
|
||||
dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \
|
||||
at91sam9263ek.dtb \
|
||||
at91sam9g20ek_2mmc.dtb \
|
||||
at91sam9g20ek.dtb \
|
||||
at91sam9g25ek.dtb \
|
||||
at91sam9m10g45ek.dtb \
|
||||
at91sam9n12ek.dtb \
|
||||
ethernut5.dtb \
|
||||
evk-pro3.dtb \
|
||||
kizbox.dtb \
|
||||
tny_a9260.dtb \
|
||||
tny_a9263.dtb \
|
||||
tny_a9g20.dtb \
|
||||
usb_a9260.dtb \
|
||||
usb_a9263.dtb \
|
||||
usb_a9g20.dtb
|
||||
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
|
||||
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
|
||||
dove-cubox.dtb \
|
||||
dove-dove-db.dtb
|
||||
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
|
||||
exynos4210-smdkv310.dtb \
|
||||
exynos5250-smdk5250.dtb
|
||||
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
|
||||
dtb-$(CONFIG_ARCH_IMX5) += imx51-babbage.dtb \
|
||||
imx53-ard.dtb \
|
||||
imx53-evk.dtb \
|
||||
imx53-qsb.dtb \
|
||||
imx53-smd.dtb
|
||||
dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
|
||||
imx6q-sabrelite.dtb \
|
||||
imx6q-sabresd.dtb
|
||||
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
|
||||
dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
|
||||
kirkwood-dns325.dtb \
|
||||
kirkwood-dockstar.dtb \
|
||||
kirkwood-dreamplug.dtb \
|
||||
kirkwood-goflexnet.dtb \
|
||||
kirkwood-ib62x0.dtb \
|
||||
kirkwood-iconnect.dtb \
|
||||
kirkwood-iomega_ix2_200.dtb \
|
||||
kirkwood-km_kirkwood.dtb \
|
||||
kirkwood-lschlv2.dtb \
|
||||
kirkwood-lsxhl.dtb \
|
||||
kirkwood-ts219-6281.dtb \
|
||||
kirkwood-ts219-6282.dtb
|
||||
dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
|
||||
msm8960-cdp.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
|
||||
armada-xp-db.dtb
|
||||
dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
|
||||
imx53-ard.dtb \
|
||||
imx53-evk.dtb \
|
||||
imx53-qsb.dtb \
|
||||
imx53-smd.dtb \
|
||||
imx6q-arm2.dtb \
|
||||
imx6q-sabrelite.dtb \
|
||||
imx6q-sabresd.dtb
|
||||
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
|
||||
imx23-olinuxino.dtb \
|
||||
imx23-stmp378x_devb.dtb \
|
||||
imx28-apx4devkit.dtb \
|
||||
imx28-cfa10036.dtb \
|
||||
imx28-cfa10049.dtb \
|
||||
imx28-evk.dtb \
|
||||
imx28-m28evk.dtb \
|
||||
imx28-tx28.dtb
|
||||
dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
|
||||
omap3-beagle-xm.dtb \
|
||||
omap3-evm.dtb \
|
||||
omap3-tobi.dtb \
|
||||
omap4-panda.dtb \
|
||||
omap4-pandaES.dtb \
|
||||
omap4-var_som.dtb \
|
||||
omap4-sdp.dtb \
|
||||
omap5-evm.dtb
|
||||
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb
|
||||
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
|
||||
r8a7740-armadillo800eva.dtb \
|
||||
sh73a0-kzm9g.dtb
|
||||
dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
|
||||
spear1340-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
|
||||
spear310-evb.dtb \
|
||||
spear320-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
|
||||
tegra20-medcom-wide.dtb \
|
||||
tegra20-paz00.dtb \
|
||||
tegra20-plutux.dtb \
|
||||
tegra20-seaboard.dtb \
|
||||
tegra20-tec.dtb \
|
||||
tegra20-trimslice.dtb \
|
||||
tegra20-ventana.dtb \
|
||||
tegra20-whistler.dtb \
|
||||
tegra30-cardhu-a02.dtb \
|
||||
tegra30-cardhu-a04.dtb
|
||||
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
|
||||
vexpress-v2p-ca9.dtb \
|
||||
vexpress-v2p-ca15-tc1.dtb \
|
||||
vexpress-v2p-ca15_a7.dtb
|
||||
|
||||
endif
|
||||
|
|
@ -17,4 +17,64 @@
|
|||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart1: serial@44e09000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@44e0b000 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@24 {
|
||||
reg = <0x24>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
regulators {
|
||||
dcdc1_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1325000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,4 +17,104 @@
|
|||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart1: serial@44e09000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@44e0b000 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@2d {
|
||||
reg = <0x2d>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vbat: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
vcc2-supply = <&vbat>;
|
||||
vcc3-supply = <&vbat>;
|
||||
vcc4-supply = <&vbat>;
|
||||
vcc5-supply = <&vbat>;
|
||||
vcc6-supply = <&vbat>;
|
||||
vcc7-supply = <&vbat>;
|
||||
vccio-supply = <&vbat>;
|
||||
|
||||
regulators {
|
||||
vrtc_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1312500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd3_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig1_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -69,95 +69,146 @@
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x44e07000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <96>;
|
||||
};
|
||||
|
||||
gpio2: gpio@4804C000 {
|
||||
gpio2: gpio@4804c000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio2";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x4804c000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <98>;
|
||||
};
|
||||
|
||||
gpio3: gpio@481AC000 {
|
||||
gpio3: gpio@481ac000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio3";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x481ac000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <32>;
|
||||
};
|
||||
|
||||
gpio4: gpio@481AE000 {
|
||||
gpio4: gpio@481ae000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio4";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x481ae000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <62>;
|
||||
};
|
||||
|
||||
uart1: serial@44E09000 {
|
||||
uart1: serial@44e09000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart1";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x44e09000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <72>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@48022000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart2";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x48022000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <73>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@48024000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart3";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x48024000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <74>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@481A6000 {
|
||||
uart4: serial@481a6000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481a6000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <44>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@481A8000 {
|
||||
uart5: serial@481a8000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart5";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481a8000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart6: serial@481AA000 {
|
||||
uart6: serial@481aa000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart6";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481aa000 0x2000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <46>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@44E0B000 {
|
||||
i2c1: i2c@44e0b000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c1";
|
||||
reg = <0x44e0b000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <70>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@4802A000 {
|
||||
i2c2: i2c@4802a000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c2";
|
||||
reg = <0x4802a000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <71>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@4819C000 {
|
||||
i2c3: i2c@4819c000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c3";
|
||||
reg = <0x4819c000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt2: wdt@44e35000 {
|
||||
compatible = "ti,omap3-wdt";
|
||||
ti,hwmods = "wd_timer2";
|
||||
reg = <0x44e35000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -63,6 +63,11 @@
|
|||
reg = <0xd0020300 0x30>;
|
||||
interrupts = <37>, <38>, <39>, <40>;
|
||||
};
|
||||
|
||||
addr-decoding@d0020000 {
|
||||
compatible = "marvell,armada-addr-decoding-controller";
|
||||
reg = <0xd0020000 0x258>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -21,6 +21,12 @@
|
|||
model = "Marvell Armada 370 family SoC";
|
||||
compatible = "marvell,armada370", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@d0020000 {
|
||||
reg = <0xd0020a00 0x1d0>,
|
||||
<0xd0021870 0x58>;
|
||||
|
|
@ -31,5 +37,43 @@
|
|||
compatible = "marvell,armada-370-xp-system-controller";
|
||||
reg = <0xd0018200 0x100>;
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
compatible = "marvell,mv88f6710-pinctrl";
|
||||
reg = <0xd0018000 0x38>;
|
||||
};
|
||||
|
||||
gpio0: gpio@d0018100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0xd0018100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
};
|
||||
|
||||
gpio1: gpio@d0018140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0xd0018140 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>, <90>;
|
||||
};
|
||||
|
||||
gpio2: gpio@d0018180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0xd0018180 0x40>;
|
||||
ngpios = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,11 +14,11 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "armada-xp.dtsi"
|
||||
/include/ "armada-xp-mv78460.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP Evaluation Board";
|
||||
compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78230 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
/include/ "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78230 SoC";
|
||||
compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl {
|
||||
compatible = "marvell,mv78230-pinctrl";
|
||||
reg = <0xd0018000 0x38>;
|
||||
};
|
||||
|
||||
gpio0: gpio@d0018100 {
|
||||
compatible = "marvell,armadaxp-gpio";
|
||||
reg = <0xd0018100 0x40>,
|
||||
<0xd0018800 0x30>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <16>, <17>, <18>, <19>;
|
||||
};
|
||||
|
||||
gpio1: gpio@d0018140 {
|
||||
compatible = "marvell,armadaxp-gpio";
|
||||
reg = <0xd0018140 0x40>,
|
||||
<0xd0018840 0x30>;
|
||||
ngpios = <17>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <20>, <21>, <22>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78260 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
/include/ "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78260 SoC";
|
||||
compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl {
|
||||
compatible = "marvell,mv78260-pinctrl";
|
||||
reg = <0xd0018000 0x38>;
|
||||
};
|
||||
|
||||
gpio0: gpio@d0018100 {
|
||||
compatible = "marvell,armadaxp-gpio";
|
||||
reg = <0xd0018100 0x40>,
|
||||
<0xd0018800 0x30>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <16>, <17>, <18>, <19>;
|
||||
};
|
||||
|
||||
gpio1: gpio@d0018140 {
|
||||
compatible = "marvell,armadaxp-gpio";
|
||||
reg = <0xd0018140 0x40>,
|
||||
<0xd0018840 0x30>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <20>, <21>, <22>, <23>;
|
||||
};
|
||||
|
||||
gpio2: gpio@d0018180 {
|
||||
compatible = "marvell,armadaxp-gpio";
|
||||
reg = <0xd0018180 0x40>,
|
||||
<0xd0018870 0x30>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78460 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
/include/ "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78460 SoC";
|
||||
compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl {
|
||||
compatible = "marvell,mv78460-pinctrl";
|
||||
reg = <0xd0018000 0x38>;
|
||||
};
|
||||
|
||||
gpio0: gpio@d0018100 {
|
||||
compatible = "marvell,armadaxp-gpio";
|
||||
reg = <0xd0018100 0x40>,
|
||||
<0xd0018800 0x30>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <16>, <17>, <18>, <19>;
|
||||
};
|
||||
|
||||
gpio1: gpio@d0018140 {
|
||||
compatible = "marvell,armadaxp-gpio";
|
||||
reg = <0xd0018140 0x40>,
|
||||
<0xd0018840 0x30>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <20>, <21>, <22>, <23>;
|
||||
};
|
||||
|
||||
gpio2: gpio@d0018180 {
|
||||
compatible = "marvell,armadaxp-gpio";
|
||||
reg = <0xd0018180 0x40>,
|
||||
<0xd0018870 0x30>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupts-cells = <2>;
|
||||
interrupts = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/dts-v1/;
|
||||
/memreserve/ 0x0c000000 0x04000000;
|
||||
/include/ "bcm2835.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "raspberrypi,model-b", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Model B";
|
||||
|
||||
memory {
|
||||
reg = <0 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
model = "BCM2835";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
chosen {
|
||||
bootargs = "earlyprintk console=ttyAMA0";
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x7e000000 0x20000000 0x02000000>;
|
||||
|
||||
timer {
|
||||
compatible = "brcm,bcm2835-system-timer";
|
||||
reg = <0x7e003000 0x1000>;
|
||||
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "brcm,bcm2835-armctrl-ic";
|
||||
reg = <0x7e00b200 0x200>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
uart@20201000 {
|
||||
compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
|
||||
reg = <0x7e201000 0x1000>;
|
||||
interrupts = <2 25>;
|
||||
clock-frequency = <3000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "dove.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Compulab CM-A510";
|
||||
compatible = "compulab,cm-a510", "marvell,dove";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8 earlyprintk";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 { status = "okay"; };
|
||||
&uart1 { status = "okay"; };
|
||||
&sdio0 { status = "okay"; };
|
||||
&sdio1 { status = "okay"; };
|
||||
&sata0 { status = "okay"; };
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
/* spi0.0: 4M Flash Winbond W25Q32BV */
|
||||
spi-flash@0 {
|
||||
compatible = "st,w25q32";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "dove.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SolidRun CuBox";
|
||||
compatible = "solidrun,cubox", "marvell,dove";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8 earlyprintk";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
power {
|
||||
label = "Power";
|
||||
gpios = <&gpio0 18 1>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 { status = "okay"; };
|
||||
&sdio0 { status = "okay"; };
|
||||
&sata0 { status = "okay"; };
|
||||
&i2c0 { status = "okay"; };
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
/* spi0.0: 4M Flash Winbond W25Q32BV */
|
||||
spi-flash@0 {
|
||||
compatible = "st,w25q32";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "dove.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell DB-MV88AP510-BP Development Board";
|
||||
compatible = "marvell,dove-db", "marvell,dove";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8 earlyprintk";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 { status = "okay"; };
|
||||
&uart1 { status = "okay"; };
|
||||
&sdio0 { status = "okay"; };
|
||||
&sdio1 { status = "okay"; };
|
||||
&sata0 { status = "okay"; };
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
/* spi0.0: 4M Flash ST-M25P32-VMF6P */
|
||||
spi-flash@0 {
|
||||
compatible = "st,m25p32";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "marvell,dove";
|
||||
model = "Marvell Armada 88AP510 SoC";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "marvell,orion-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0xf1020204 0x04>,
|
||||
<0xf1020214 0x04>;
|
||||
};
|
||||
|
||||
mbus@f1000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0xf1000000 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x12000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <7>;
|
||||
clock-frequency = <166666667>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@12100 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <8>;
|
||||
clock-frequency = <166666667>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@12200 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x12000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <9>;
|
||||
clock-frequency = <166666667>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@12300 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <10>;
|
||||
clock-frequency = <166666667>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt: wdt@20300 {
|
||||
compatible = "marvell,orion-wdt";
|
||||
reg = <0x20300 0x28>;
|
||||
};
|
||||
|
||||
gpio0: gpio@d0400 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
reg = <0xd0400 0x20>;
|
||||
ngpio = <32>;
|
||||
interrupts = <12>, <13>, <14>, <60>;
|
||||
};
|
||||
|
||||
gpio1: gpio@d0420 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
reg = <0xd0420 0x20>;
|
||||
ngpio = <32>;
|
||||
interrupts = <61>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e8400 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
reg = <0xe8400 0x0c>;
|
||||
ngpio = <8>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,orion-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <6>;
|
||||
reg = <0x10600 0x28>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@14600 {
|
||||
compatible = "marvell,orion-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <5>;
|
||||
reg = <0x14600 0x28>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <11>;
|
||||
clock-frequency = <400000>;
|
||||
timeout-ms = <1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio0: sdio@92000 {
|
||||
compatible = "marvell,dove-sdhci";
|
||||
reg = <0x92000 0x100>;
|
||||
interrupts = <35>, <37>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio1: sdio@90000 {
|
||||
compatible = "marvell,dove-sdhci";
|
||||
reg = <0x90000 0x100>;
|
||||
interrupts = <36>, <38>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata0: sata@a0000 {
|
||||
compatible = "marvell,orion-sata";
|
||||
reg = <0xa0000 0x2400>;
|
||||
interrupts = <62>;
|
||||
nr-ports = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -166,9 +166,116 @@
|
|||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
button@21 {
|
||||
label = "GPIO Key UP";
|
||||
label = "Interrupt Key";
|
||||
linux,code = <103>;
|
||||
gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
|
||||
};
|
||||
key1 {
|
||||
label = "KEY1";
|
||||
linux,code = <1>;
|
||||
gpios = <&pca9532 0 0>;
|
||||
};
|
||||
key2 {
|
||||
label = "KEY2";
|
||||
linux,code = <2>;
|
||||
gpios = <&pca9532 1 0>;
|
||||
};
|
||||
key3 {
|
||||
label = "KEY3";
|
||||
linux,code = <3>;
|
||||
gpios = <&pca9532 2 0>;
|
||||
};
|
||||
key4 {
|
||||
label = "KEY4";
|
||||
linux,code = <4>;
|
||||
gpios = <&pca9532 3 0>;
|
||||
};
|
||||
joy0 {
|
||||
label = "Joystick Key 0";
|
||||
linux,code = <10>;
|
||||
gpios = <&gpio 2 0 0>; /* P2.0 */
|
||||
};
|
||||
joy1 {
|
||||
label = "Joystick Key 1";
|
||||
linux,code = <11>;
|
||||
gpios = <&gpio 2 1 0>; /* P2.1 */
|
||||
};
|
||||
joy2 {
|
||||
label = "Joystick Key 2";
|
||||
linux,code = <12>;
|
||||
gpios = <&gpio 2 2 0>; /* P2.2 */
|
||||
};
|
||||
joy3 {
|
||||
label = "Joystick Key 3";
|
||||
linux,code = <13>;
|
||||
gpios = <&gpio 2 3 0>; /* P2.3 */
|
||||
};
|
||||
joy4 {
|
||||
label = "Joystick Key 4";
|
||||
linux,code = <14>;
|
||||
gpios = <&gpio 2 4 0>; /* P2.4 */
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
/* LEDs on OEM Board */
|
||||
|
||||
led1 {
|
||||
gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
|
||||
linux,default-trigger = "timer";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led2 {
|
||||
gpios = <&gpio 2 10 1>; /* P2.10, active low */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led3 {
|
||||
gpios = <&gpio 2 11 1>; /* P2.11, active low */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led4 {
|
||||
gpios = <&gpio 2 12 1>; /* P2.12, active low */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
/* LEDs on Base Board */
|
||||
|
||||
lede1 {
|
||||
gpios = <&pca9532 8 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede2 {
|
||||
gpios = <&pca9532 9 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede3 {
|
||||
gpios = <&pca9532 10 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede4 {
|
||||
gpios = <&pca9532 11 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede5 {
|
||||
gpios = <&pca9532 12 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede6 {
|
||||
gpios = <&pca9532 13 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede7 {
|
||||
gpios = <&pca9532 14 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
lede8 {
|
||||
gpios = <&pca9532 15 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Common devices used in different OMAP boards
|
||||
*/
|
||||
|
||||
/ {
|
||||
elpida_ECB240ABACN: lpddr2 {
|
||||
compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
|
||||
density = <2048>;
|
||||
io-width = <32>;
|
||||
|
||||
tRPab-min-tck = <3>;
|
||||
tRCD-min-tck = <3>;
|
||||
tWR-min-tck = <3>;
|
||||
tRASmin-min-tck = <3>;
|
||||
tRRD-min-tck = <2>;
|
||||
tWTR-min-tck = <2>;
|
||||
tXP-min-tck = <2>;
|
||||
tRTP-min-tck = <2>;
|
||||
tCKE-min-tck = <3>;
|
||||
tCKESR-min-tck = <3>;
|
||||
tFAW-min-tck = <8>;
|
||||
|
||||
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <400000000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tWR = <15000>;
|
||||
tRAS-min = <42000>;
|
||||
tRRD = <10000>;
|
||||
tWTR = <7500>;
|
||||
tXP = <7500>;
|
||||
tRTP = <7500>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tZQCS = <90000>;
|
||||
tZQCL = <360000>;
|
||||
tZQinit = <1000000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
tDQSCK-max-derated = <6000>;
|
||||
};
|
||||
|
||||
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
|
||||
compatible = "jedec,lpddr2-timings";
|
||||
min-freq = <10000000>;
|
||||
max-freq = <200000000>;
|
||||
tRPab = <21000>;
|
||||
tRCD = <18000>;
|
||||
tWR = <15000>;
|
||||
tRAS-min = <42000>;
|
||||
tRRD = <10000>;
|
||||
tWTR = <10000>;
|
||||
tXP = <7500>;
|
||||
tRTP = <7500>;
|
||||
tCKESR = <15000>;
|
||||
tDQSCK-max = <5500>;
|
||||
tFAW = <50000>;
|
||||
tZQCS = <90000>;
|
||||
tZQCL = <360000>;
|
||||
tZQinit = <1000000>;
|
||||
tRAS-max-ns = <70000>;
|
||||
tDQSCK-max-derated = <6000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -42,12 +42,13 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
|
||||
0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
|
||||
0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
|
||||
0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
|
|
|
|||
|
|
@ -31,6 +31,22 @@
|
|||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@80018000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
|
||||
0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
apbx@80040000 {
|
||||
|
|
@ -39,6 +55,47 @@
|
|||
pinctrl-0 = <&duart_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
auart0: serial@8006c000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&auart0_2pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy0: usbphy@8007c000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ahb@80080000 {
|
||||
usb0: usb@80080000 {
|
||||
vbus-supply = <®_usb0_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_usb0_vbus: usb0_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb0_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
|
||||
gpio = <&gpio0 17 0>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
user {
|
||||
label = "green";
|
||||
gpios = <&gpio2 1 0>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@
|
|||
dma-apbh@80004000 {
|
||||
compatible = "fsl,imx23-dma-apbh";
|
||||
reg = <0x80004000 0x2000>;
|
||||
clocks = <&clks 15>;
|
||||
};
|
||||
|
||||
ecc@80008000 {
|
||||
|
|
@ -67,6 +68,7 @@
|
|||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <13>, <56>;
|
||||
interrupt-names = "gpmi-dma", "bch";
|
||||
clocks = <&clks 34>;
|
||||
fsl,gpmi-dma-channel = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -74,6 +76,7 @@
|
|||
ssp0: ssp@80010000 {
|
||||
reg = <0x80010000 0x2000>;
|
||||
interrupts = <15 14>;
|
||||
clocks = <&clks 33>;
|
||||
fsl,ssp-dma-channel = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -140,6 +143,17 @@
|
|||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
auart0_2pins_a: auart0-2pins@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
|
||||
0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
gpmi_pins_a: gpmi-nand@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
|
|
@ -183,7 +197,6 @@
|
|||
0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
|
||||
0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
|
||||
0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
|
||||
0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
|
||||
0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
|
||||
>;
|
||||
fsl,drive-strength = <1>;
|
||||
|
|
@ -280,6 +293,7 @@
|
|||
dma-apbx@80024000 {
|
||||
compatible = "fsl,imx23-dma-apbx";
|
||||
reg = <0x80024000 0x2000>;
|
||||
clocks = <&clks 16>;
|
||||
};
|
||||
|
||||
dcp@80028000 {
|
||||
|
|
@ -306,12 +320,14 @@
|
|||
compatible = "fsl,imx23-lcdif";
|
||||
reg = <0x80030000 2000>;
|
||||
interrupts = <46 45>;
|
||||
clocks = <&clks 38>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp1: ssp@80034000 {
|
||||
reg = <0x80034000 0x2000>;
|
||||
interrupts = <2 20>;
|
||||
clocks = <&clks 33>;
|
||||
fsl,ssp-dma-channel = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -329,9 +345,10 @@
|
|||
reg = <0x80040000 0x40000>;
|
||||
ranges;
|
||||
|
||||
clkctl@80040000 {
|
||||
clks: clkctrl@80040000 {
|
||||
compatible = "fsl,imx23-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
saif0: saif@80042000 {
|
||||
|
|
@ -383,6 +400,7 @@
|
|||
pwm: pwm@80064000 {
|
||||
compatible = "fsl,imx23-pwm";
|
||||
reg = <0x80064000 0x2000>;
|
||||
clocks = <&clks 30>;
|
||||
#pwm-cells = <2>;
|
||||
fsl,pwm-number = <5>;
|
||||
status = "disabled";
|
||||
|
|
@ -397,6 +415,7 @@
|
|||
compatible = "fsl,imx23-auart";
|
||||
reg = <0x8006c000 0x2000>;
|
||||
interrupts = <24 25 23>;
|
||||
clocks = <&clks 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -404,6 +423,7 @@
|
|||
compatible = "fsl,imx23-auart";
|
||||
reg = <0x8006e000 0x2000>;
|
||||
interrupts = <59 60 58>;
|
||||
clocks = <&clks 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -411,11 +431,15 @@
|
|||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x80070000 0x2000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&clks 32>, <&clks 16>;
|
||||
clock-names = "uart", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy@8007c000 {
|
||||
usbphy0: usbphy@8007c000 {
|
||||
compatible = "fsl,imx23-usbphy";
|
||||
reg = <0x8007c000 0x2000>;
|
||||
clocks = <&clks 41>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -428,8 +452,12 @@
|
|||
reg = <0x80080000 0x80000>;
|
||||
ranges;
|
||||
|
||||
usbctrl@80080000 {
|
||||
usb0: usb@80080000 {
|
||||
compatible = "fsl,imx23-usb", "fsl,imx27-usb";
|
||||
reg = <0x80080000 0x40000>;
|
||||
interrupts = <11>;
|
||||
fsl,usbphy = <&usbphy0>;
|
||||
clocks = <&clks 40>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,10 +23,6 @@
|
|||
soc {
|
||||
aipi@10000000 { /* aipi */
|
||||
|
||||
wdog@10002000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@1000a000 {
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
|
|
@ -49,7 +45,7 @@
|
|||
i2c@1001d000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
at24@4c {
|
||||
at24@52 {
|
||||
compatible = "at,24c32";
|
||||
pagesize = <32>;
|
||||
reg = <0x52>;
|
||||
|
|
|
|||
|
|
@ -62,7 +62,6 @@
|
|||
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x10002000 0x4000>;
|
||||
interrupts = <27>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright 2012 Free Electrons
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/*
|
||||
* The CFA-10049 is an expansion board for the CFA-10036 module, thus we
|
||||
* need to include the CFA-10036 DTS.
|
||||
*/
|
||||
/include/ "imx28-cfa10036.dts"
|
||||
|
||||
/ {
|
||||
model = "Crystalfontz CFA-10049 Board";
|
||||
compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
|
||||
|
||||
apb@80000000 {
|
||||
apbh@80000000 {
|
||||
pinctrl@80018000 {
|
||||
spi3_pins_cfa10049: spi3-cfa10049@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
|
||||
0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
|
||||
0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
|
||||
0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
|
||||
>;
|
||||
fsl,drive-strength = <1>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ssp3: ssp@80016000 {
|
||||
compatible = "fsl,imx28-spi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi3_pins_cfa10049>;
|
||||
status = "okay";
|
||||
|
||||
gpio5: gpio5@0 {
|
||||
compatible = "fairchild,74hc595";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0>;
|
||||
registers-number = <2>;
|
||||
spi-max-frequency = <100000>;
|
||||
};
|
||||
|
||||
gpio6: gpio6@1 {
|
||||
compatible = "fairchild,74hc595";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <1>;
|
||||
registers-number = <4>;
|
||||
spi-max-frequency = <100000>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
apbx@80040000 {
|
||||
i2c1: i2c@8005a000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@8007e000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ahb@80080000 {
|
||||
usb1: usb@80090000 {
|
||||
vbus-supply = <®_usb1_vbus>;
|
||||
pinctrl-0 = <&usbphy1_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_usb1_vbus: usb1_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio0 7 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -46,11 +46,28 @@
|
|||
wp-gpios = <&gpio0 28 0>;
|
||||
};
|
||||
|
||||
ssp2: ssp@80014000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx28-spi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25vf016b";
|
||||
spi-max-frequency = <40000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@80018000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
|
||||
|
|
@ -128,6 +145,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
lradc@80050000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@80058000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
|
|
@ -140,6 +161,12 @@
|
|||
VDDIO-supply = <®_3p3v>;
|
||||
|
||||
};
|
||||
|
||||
at24@51 {
|
||||
compatible = "at24,24c32";
|
||||
pagesize = <32>;
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm: pwm@80064000 {
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@
|
|||
apb@80000000 {
|
||||
apbh@80000000 {
|
||||
gpmi-nand@8000c000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
|
||||
status = "okay";
|
||||
|
|
@ -61,19 +63,40 @@
|
|||
&mmc0_cd_cfg
|
||||
&mmc0_sck_cfg>;
|
||||
bus-width = <8>;
|
||||
wp-gpios = <&gpio3 10 1>;
|
||||
wp-gpios = <&gpio3 10 0>;
|
||||
vmmc-supply = <®_vddio_sd0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssp2: ssp@80014000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx28-spi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p80";
|
||||
spi-max-frequency = <40000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl@80018000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
|
||||
0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
|
||||
0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
|
||||
0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
|
||||
0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
|
|
@ -129,6 +152,7 @@
|
|||
i2c0: i2c@80058000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
|
|
@ -151,32 +175,51 @@
|
|||
};
|
||||
};
|
||||
|
||||
lradc@80050000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
duart: serial@80074000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&duart_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy0: usbphy@8007c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@8007e000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
auart0: serial@8006a000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&auart0_2pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
auart3: serial@80070000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&auart3_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ahb@80080000 {
|
||||
usb0: usb@80080000 {
|
||||
vbus-supply = <®_usb0_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usbphy0_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: usb@80090000 {
|
||||
vbus-supply = <®_usb1_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usbphy1_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mac0: ethernet@800f0000 {
|
||||
phy-mode = "rmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mac0_pins_a>;
|
||||
phy-reset-gpios = <&gpio3 11 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -198,6 +241,30 @@
|
|||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vddio_sd0: vddio-sd0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddio-sd0";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio3 28 0>;
|
||||
};
|
||||
|
||||
reg_usb0_vbus: usb0_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb0_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 12 0>;
|
||||
};
|
||||
|
||||
reg_usb1_vbus: usb1_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio3 13 0>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hog_pins_a>;
|
||||
|
||||
hog_pins_a: hog-gpios@0 {
|
||||
hog_pins_a: hog@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
|
||||
|
|
@ -34,6 +34,24 @@
|
|||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
mac0_pins_gpio: mac0-gpio-mode@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
|
||||
0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
|
||||
0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
|
||||
0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
|
||||
0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
|
||||
0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
|
||||
0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
|
||||
0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
|
||||
0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -72,8 +90,9 @@
|
|||
ahb@80080000 {
|
||||
mac0: ethernet@800f0000 {
|
||||
phy-mode = "rmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-names = "default", "gpio_mode";
|
||||
pinctrl-0 = <&mac0_pins_a>;
|
||||
pinctrl-1 = <&mac0_pins_gpio>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -27,6 +27,8 @@
|
|||
serial2 = &auart2;
|
||||
serial3 = &auart3;
|
||||
serial4 = &auart4;
|
||||
ethernet0 = &mac0;
|
||||
ethernet1 = &mac1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -65,6 +67,7 @@
|
|||
dma-apbh@80004000 {
|
||||
compatible = "fsl,imx28-dma-apbh";
|
||||
reg = <0x80004000 0x2000>;
|
||||
clocks = <&clks 25>;
|
||||
};
|
||||
|
||||
perfmon@80006000 {
|
||||
|
|
@ -81,34 +84,47 @@
|
|||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <88>, <41>;
|
||||
interrupt-names = "gpmi-dma", "bch";
|
||||
clocks = <&clks 50>;
|
||||
fsl,gpmi-dma-channel = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp0: ssp@80010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80010000 0x2000>;
|
||||
interrupts = <96 82>;
|
||||
clocks = <&clks 46>;
|
||||
fsl,ssp-dma-channel = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp1: ssp@80012000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80012000 0x2000>;
|
||||
interrupts = <97 83>;
|
||||
clocks = <&clks 47>;
|
||||
fsl,ssp-dma-channel = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp2: ssp@80014000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80014000 0x2000>;
|
||||
interrupts = <98 84>;
|
||||
clocks = <&clks 48>;
|
||||
fsl,ssp-dma-channel = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp3: ssp@80016000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x80016000 0x2000>;
|
||||
interrupts = <99 85>;
|
||||
clocks = <&clks 49>;
|
||||
fsl,ssp-dma-channel = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -410,6 +426,28 @@
|
|||
fsl,pull-up = <1>;
|
||||
};
|
||||
|
||||
i2c0_pins_b: i2c0@1 {
|
||||
reg = <1>;
|
||||
fsl,pinmux-ids = <
|
||||
0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
|
||||
0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
|
||||
>;
|
||||
fsl,drive-strength = <1>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
|
||||
0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
|
||||
>;
|
||||
fsl,drive-strength = <1>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
|
||||
saif0_pins_a: saif0@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
|
|
@ -453,6 +491,16 @@
|
|||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
pwm4_pins_a: pwm4@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x31d0 /* MX28_PAD_PWM4__PWM_4 */
|
||||
>;
|
||||
fsl,drive-strength = <0>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
lcdif_24bit_pins_a: lcdif-24bit@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
|
|
@ -507,6 +555,49 @@
|
|||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
spi2_pins_a: spi2@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
|
||||
0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
|
||||
0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
|
||||
0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
|
||||
>;
|
||||
fsl,drive-strength = <1>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <1>;
|
||||
};
|
||||
|
||||
usbphy0_pins_a: usbphy0@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
|
||||
>;
|
||||
fsl,drive-strength = <2>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
usbphy0_pins_b: usbphy0@1 {
|
||||
reg = <1>;
|
||||
fsl,pinmux-ids = <
|
||||
0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
|
||||
>;
|
||||
fsl,drive-strength = <2>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
|
||||
usbphy1_pins_a: usbphy1@0 {
|
||||
reg = <0>;
|
||||
fsl,pinmux-ids = <
|
||||
0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
|
||||
>;
|
||||
fsl,drive-strength = <2>;
|
||||
fsl,voltage = <1>;
|
||||
fsl,pull-up = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
digctl@8001c000 {
|
||||
|
|
@ -523,6 +614,7 @@
|
|||
dma-apbx@80024000 {
|
||||
compatible = "fsl,imx28-dma-apbx";
|
||||
reg = <0x80024000 0x2000>;
|
||||
clocks = <&clks 26>;
|
||||
};
|
||||
|
||||
dcp@80028000 {
|
||||
|
|
@ -551,6 +643,7 @@
|
|||
compatible = "fsl,imx28-lcdif";
|
||||
reg = <0x80030000 0x2000>;
|
||||
interrupts = <38 86>;
|
||||
clocks = <&clks 55>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -558,6 +651,8 @@
|
|||
compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x80032000 0x2000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&clks 58>, <&clks 58>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -565,6 +660,8 @@
|
|||
compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x80034000 0x2000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&clks 59>, <&clks 59>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -611,15 +708,17 @@
|
|||
reg = <0x80040000 0x40000>;
|
||||
ranges;
|
||||
|
||||
clkctl@80040000 {
|
||||
clks: clkctrl@80040000 {
|
||||
compatible = "fsl,imx28-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
status = "disabled";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
saif0: saif@80042000 {
|
||||
compatible = "fsl,imx28-saif";
|
||||
reg = <0x80042000 0x2000>;
|
||||
interrupts = <59 80>;
|
||||
clocks = <&clks 53>;
|
||||
fsl,saif-dma-channel = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -633,12 +732,16 @@
|
|||
compatible = "fsl,imx28-saif";
|
||||
reg = <0x80046000 0x2000>;
|
||||
interrupts = <58 81>;
|
||||
clocks = <&clks 54>;
|
||||
fsl,saif-dma-channel = <5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lradc@80050000 {
|
||||
compatible = "fsl,imx28-lradc";
|
||||
reg = <0x80050000 0x2000>;
|
||||
interrupts = <10 14 15 16 17 18 19
|
||||
20 21 22 23 24 25>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -677,6 +780,7 @@
|
|||
pwm: pwm@80064000 {
|
||||
compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
|
||||
reg = <0x80064000 0x2000>;
|
||||
clocks = <&clks 44>;
|
||||
#pwm-cells = <2>;
|
||||
fsl,pwm-number = <8>;
|
||||
status = "disabled";
|
||||
|
|
@ -691,6 +795,7 @@
|
|||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x8006a000 0x2000>;
|
||||
interrupts = <112 70 71>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -698,6 +803,7 @@
|
|||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x8006c000 0x2000>;
|
||||
interrupts = <113 72 73>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -705,6 +811,7 @@
|
|||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x8006e000 0x2000>;
|
||||
interrupts = <114 74 75>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -712,6 +819,7 @@
|
|||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x80070000 0x2000>;
|
||||
interrupts = <115 76 77>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -719,6 +827,7 @@
|
|||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x80072000 0x2000>;
|
||||
interrupts = <116 78 79>;
|
||||
clocks = <&clks 45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -726,18 +835,22 @@
|
|||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x80074000 0x1000>;
|
||||
interrupts = <47>;
|
||||
clocks = <&clks 45>, <&clks 26>;
|
||||
clock-names = "uart", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy0: usbphy@8007c000 {
|
||||
compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x8007c000 0x2000>;
|
||||
clocks = <&clks 62>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@8007e000 {
|
||||
compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x8007e000 0x2000>;
|
||||
clocks = <&clks 63>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -754,6 +867,7 @@
|
|||
compatible = "fsl,imx28-usb", "fsl,imx27-usb";
|
||||
reg = <0x80080000 0x10000>;
|
||||
interrupts = <93>;
|
||||
clocks = <&clks 60>;
|
||||
fsl,usbphy = <&usbphy0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -762,6 +876,7 @@
|
|||
compatible = "fsl,imx28-usb", "fsl,imx27-usb";
|
||||
reg = <0x80090000 0x10000>;
|
||||
interrupts = <92>;
|
||||
clocks = <&clks 61>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -775,6 +890,8 @@
|
|||
compatible = "fsl,imx28-fec";
|
||||
reg = <0x800f0000 0x4000>;
|
||||
interrupts = <101>;
|
||||
clocks = <&clks 57>, <&clks 57>;
|
||||
clock-names = "ipg", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -782,6 +899,8 @@
|
|||
compatible = "fsl,imx28-fec";
|
||||
reg = <0x800f4000 0x4000>;
|
||||
interrupts = <102>;
|
||||
clocks = <&clks 57>, <&clks 57>;
|
||||
clock-names = "ipg", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -25,23 +25,31 @@
|
|||
aips@70000000 { /* aips-1 */
|
||||
spba@70000000 {
|
||||
esdhc@70004000 { /* ESDHC1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_1>;
|
||||
fsl,cd-controller;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
esdhc@70008000 { /* ESDHC2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2_1>;
|
||||
cd-gpios = <&gpio1 6 0>;
|
||||
wp-gpios = <&gpio1 5 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart3: serial@7000c000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3_1>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ecspi@70010000 { /* ECSPI1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1_1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
|
||||
status = "okay";
|
||||
|
|
@ -169,31 +177,43 @@
|
|||
};
|
||||
};
|
||||
|
||||
wdog@73f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@73fa8000 {
|
||||
compatible = "fsl,imx51-iomuxc-babbage";
|
||||
reg = <0x73fa8000 0x4000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
|
||||
697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
|
||||
737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
|
||||
740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
|
||||
121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
|
||||
402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
|
||||
405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@73fbc000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart2: serial@73fc0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@80000000 { /* aips-2 */
|
||||
sdma@83fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
|
||||
};
|
||||
|
||||
i2c@83fc4000 { /* I2C2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_1>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
|
|
@ -206,10 +226,14 @@
|
|||
};
|
||||
|
||||
audmux@83fd0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@83fec000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_1>;
|
||||
phy-mode = "mii";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -130,6 +130,34 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb@73f80000 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80000 0x0200>;
|
||||
interrupts = <18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@73f80200 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80200 0x0200>;
|
||||
interrupts = <14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@73f80400 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80400 0x0200>;
|
||||
interrupts = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@73f80600 {
|
||||
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
|
||||
reg = <0x73f80600 0x0200>;
|
||||
interrupts = <17>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@73f84000 {
|
||||
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x73f84000 0x4000>;
|
||||
|
|
@ -174,7 +202,6 @@
|
|||
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x73f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog@73f9c000 { /* WDOG2 */
|
||||
|
|
@ -184,6 +211,122 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc@73fa8000 {
|
||||
compatible = "fsl,imx51-iomuxc";
|
||||
reg = <0x73fa8000 0x4000>;
|
||||
|
||||
audmux {
|
||||
pinctrl_audmux_1: audmuxgrp-1 {
|
||||
fsl,pins = <
|
||||
384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
|
||||
386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
|
||||
389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
|
||||
391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
fec {
|
||||
pinctrl_fec_1: fecgrp-1 {
|
||||
fsl,pins = <
|
||||
128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
|
||||
134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
|
||||
146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
|
||||
152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
|
||||
158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
|
||||
165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
|
||||
206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
|
||||
213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
|
||||
293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
|
||||
298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
|
||||
225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
|
||||
231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
|
||||
237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
|
||||
243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
|
||||
250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
|
||||
255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
|
||||
260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
|
||||
394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
|
||||
409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc1 {
|
||||
pinctrl_esdhc1_1: esdhc1grp-1 {
|
||||
fsl,pins = <
|
||||
666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
|
||||
669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
|
||||
672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
|
||||
678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
|
||||
684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
|
||||
691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc2 {
|
||||
pinctrl_esdhc2_1: esdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
|
||||
707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
|
||||
710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
|
||||
712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
|
||||
715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
|
||||
719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
pinctrl_i2c2_1: i2c2grp-1 {
|
||||
fsl,pins = <
|
||||
449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
|
||||
454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
|
||||
416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
|
||||
418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
|
||||
420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
|
||||
426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3_1: uart3grp-1 {
|
||||
fsl,pins = <
|
||||
54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
|
||||
59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
|
||||
65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
|
||||
49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@73fbc000 {
|
||||
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
|
||||
reg = <0x73fbc000 0x4000>;
|
||||
|
|
@ -219,6 +362,7 @@
|
|||
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x83fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
|
||||
};
|
||||
|
||||
cspi@83fc0000 {
|
||||
|
|
|
|||
|
|
@ -25,31 +25,66 @@
|
|||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_2>;
|
||||
cd-gpios = <&gpio1 1 0>;
|
||||
wp-gpios = <&gpio1 9 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-ard";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
|
||||
1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
|
||||
486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
|
||||
739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
|
||||
218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
|
||||
226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
|
||||
233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
|
||||
241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
|
||||
429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
|
||||
435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
|
||||
441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
|
||||
448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
|
||||
456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
|
||||
464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
|
||||
471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
|
||||
477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
|
||||
492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
|
||||
500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
|
||||
508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
|
||||
516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
|
||||
524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
|
||||
532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
|
||||
540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
|
||||
548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
|
||||
637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
|
||||
642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
|
||||
647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
|
||||
652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
|
||||
657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
|
||||
662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
|
||||
667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
|
||||
611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
|
||||
616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
|
||||
607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_2>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eim-cs1@f4000000 {
|
||||
|
|
|
|||
|
|
@ -25,12 +25,16 @@
|
|||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_1>;
|
||||
cd-gpios = <&gpio3 13 0>;
|
||||
wp-gpios = <&gpio3 14 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ecspi@50010000 { /* ECSPI1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1_1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
|
||||
status = "okay";
|
||||
|
|
@ -56,32 +60,45 @@
|
|||
};
|
||||
|
||||
esdhc@50020000 { /* ESDHC3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc3_1>;
|
||||
cd-gpios = <&gpio3 11 0>;
|
||||
wp-gpios = <&gpio3 12 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-evk";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
|
||||
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
|
||||
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
|
||||
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
|
||||
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
|
||||
705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
|
||||
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
|
||||
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
i2c@63fc4000 { /* I2C2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_1>;
|
||||
status = "okay";
|
||||
|
||||
pmic: mc13892@08 {
|
||||
|
|
@ -96,6 +113,8 @@
|
|||
};
|
||||
|
||||
ethernet@63fec000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_1>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -25,6 +25,8 @@
|
|||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_1>;
|
||||
cd-gpios = <&gpio3 13 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -35,32 +37,46 @@
|
|||
};
|
||||
|
||||
esdhc@50020000 { /* ESDHC3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc3_1>;
|
||||
cd-gpios = <&gpio3 11 0>;
|
||||
wp-gpios = <&gpio3 12 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-qsb";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
|
||||
1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
|
||||
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
|
||||
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
|
||||
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
|
||||
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
|
||||
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
|
||||
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
|
||||
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
i2c@63fc4000 { /* I2C2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_1>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: codec@0a {
|
||||
|
|
@ -72,6 +88,8 @@
|
|||
};
|
||||
|
||||
i2c@63fc8000 { /* I2C1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1_1>;
|
||||
status = "okay";
|
||||
|
||||
accelerometer: mma8450@1c {
|
||||
|
|
@ -158,10 +176,14 @@
|
|||
};
|
||||
|
||||
audmux@63fd0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@63fec000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_1>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -25,22 +25,30 @@
|
|||
aips@50000000 { /* AIPS1 */
|
||||
spba@50000000 {
|
||||
esdhc@50004000 { /* ESDHC1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc1_1>;
|
||||
cd-gpios = <&gpio3 13 0>;
|
||||
wp-gpios = <&gpio4 11 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
esdhc@50008000 { /* ESDHC2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc2_1>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart3: serial@5000c000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3_1>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ecspi@50010000 { /* ECSPI1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1_1>;
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
|
||||
status = "okay";
|
||||
|
|
@ -72,35 +80,49 @@
|
|||
};
|
||||
|
||||
esdhc@50020000 { /* ESDHC3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_esdhc3_1>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
wdog@53f98000 { /* WDOG1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-smd";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
|
||||
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
|
||||
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
|
||||
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
|
||||
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
|
||||
43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
|
||||
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart2: serial@53fc0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
sdma@63fb0000 {
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
i2c@63fc4000 { /* I2C2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_1>;
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
|
|
@ -120,6 +142,8 @@
|
|||
};
|
||||
|
||||
i2c@63fc8000 { /* I2C1 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1_1>;
|
||||
status = "okay";
|
||||
|
||||
accelerometer: mma8450@1c {
|
||||
|
|
@ -139,6 +163,8 @@
|
|||
};
|
||||
|
||||
ethernet@63fec000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec_1>;
|
||||
phy-mode = "rmii";
|
||||
phy-reset-gpios = <&gpio7 6 0>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -135,6 +135,34 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb@53f80000 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80000 0x0200>;
|
||||
interrupts = <18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@53f80200 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80200 0x0200>;
|
||||
interrupts = <14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@53f80400 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80400 0x0200>;
|
||||
interrupts = <16>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@53f80600 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80600 0x0200>;
|
||||
interrupts = <17>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@53f84000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53f84000 0x4000>;
|
||||
|
|
@ -179,7 +207,6 @@
|
|||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog@53f9c000 { /* WDOG2 */
|
||||
|
|
@ -189,6 +216,161 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
|
||||
audmux {
|
||||
pinctrl_audmux_1: audmuxgrp-1 {
|
||||
fsl,pins = <
|
||||
10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
|
||||
17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
|
||||
23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
|
||||
30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
fec {
|
||||
pinctrl_fec_1: fecgrp-1 {
|
||||
fsl,pins = <
|
||||
820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
|
||||
779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
|
||||
786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
|
||||
791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
|
||||
796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
|
||||
799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
|
||||
804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
|
||||
808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
|
||||
811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
|
||||
816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
|
||||
439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
|
||||
445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc1 {
|
||||
pinctrl_esdhc1_1: esdhc1grp-1 {
|
||||
fsl,pins = <
|
||||
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
|
||||
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
|
||||
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
|
||||
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
|
||||
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
|
||||
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1_2: esdhc1grp-2 {
|
||||
fsl,pins = <
|
||||
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
|
||||
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
|
||||
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
|
||||
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
|
||||
941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
|
||||
948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
|
||||
955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
|
||||
962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
|
||||
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
|
||||
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc2 {
|
||||
pinctrl_esdhc2_1: esdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
|
||||
1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
|
||||
1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
|
||||
1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
|
||||
1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
|
||||
1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc3 {
|
||||
pinctrl_esdhc3_1: esdhc3grp-1 {
|
||||
fsl,pins = <
|
||||
943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
|
||||
950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
|
||||
957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
|
||||
964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
|
||||
893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
|
||||
900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
|
||||
906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
|
||||
912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
|
||||
857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
|
||||
863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
pinctrl_i2c1_1: i2c1grp-1 {
|
||||
fsl,pins = <
|
||||
333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
|
||||
341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
pinctrl_i2c2_1: i2c2grp-1 {
|
||||
fsl,pins = <
|
||||
61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
|
||||
53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
|
||||
354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1_2: uart1grp-2 {
|
||||
fsl,pins = <
|
||||
828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
|
||||
832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
|
||||
836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3_1: uart3grp-1 {
|
||||
fsl,pins = <
|
||||
884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
|
||||
888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
|
||||
875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
|
||||
880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fbc000 0x4000>;
|
||||
|
|
@ -203,6 +385,20 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@53fc8000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can2: can@53fcc000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fcc000 0x4000>;
|
||||
interrupts = <83>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio5: gpio@53fdc000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fdc000 0x4000>;
|
||||
|
|
@ -277,6 +473,7 @@
|
|||
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x63fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
cspi@63fc0000 {
|
||||
|
|
|
|||
|
|
@ -28,8 +28,27 @@
|
|||
status = "disabled"; /* gpmi nand conflicts with SD */
|
||||
};
|
||||
|
||||
aips-bus@02000000 { /* AIPS1 */
|
||||
iomuxc@020e0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
|
||||
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
|
||||
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aips-bus@02100000 { /* AIPS2 */
|
||||
ethernet@02188000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_2>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -52,6 +71,8 @@
|
|||
};
|
||||
|
||||
uart4: serial@021f0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -46,15 +46,20 @@
|
|||
|
||||
iomuxc@020e0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_hog>;
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
gpios {
|
||||
pinctrl_gpio_hog: gpiohog {
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
|
||||
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
|
||||
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
|
||||
>;
|
||||
1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
|
||||
1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
|
||||
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
|
||||
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
|
||||
152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
|
||||
1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
|
||||
1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
|
||||
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -63,6 +68,9 @@
|
|||
aips-bus@02100000 { /* AIPS2 */
|
||||
usb@02184000 { /* USB OTG */
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg_1>;
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -71,12 +79,16 @@
|
|||
};
|
||||
|
||||
ethernet@02188000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_1>;
|
||||
phy-mode = "rgmii";
|
||||
phy-reset-gpios = <&gpio3 23 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usdhc@02198000 { /* uSDHC3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_2>;
|
||||
cd-gpios = <&gpio7 0 0>;
|
||||
wp-gpios = <&gpio7 1 0>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
|
|
@ -84,6 +96,8 @@
|
|||
};
|
||||
|
||||
usdhc@0219c000 { /* uSDHC4 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4_2>;
|
||||
cd-gpios = <&gpio2 6 0>;
|
||||
wp-gpios = <&gpio2 7 0>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
|
|
@ -99,7 +113,7 @@
|
|||
uart2: serial@021e8000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_serial2_1>;
|
||||
pinctrl-0 = <&pinctrl_uart2_1>;
|
||||
};
|
||||
|
||||
i2c@021a0000 { /* I2C1 */
|
||||
|
|
@ -111,6 +125,7 @@
|
|||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 169>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -22,28 +22,51 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
|
||||
aips-bus@02000000 { /* AIPS1 */
|
||||
spba-bus@02000000 {
|
||||
uart1: serial@02020000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
iomuxc@020e0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
|
||||
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
|
||||
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
|
||||
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aips-bus@02100000 { /* AIPS2 */
|
||||
ethernet@02188000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_1>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usdhc@02194000 { /* uSDHC2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2_1>;
|
||||
cd-gpios = <&gpio2 2 0>;
|
||||
wp-gpios = <&gpio2 3 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usdhc@02198000 { /* uSDHC3 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_1>;
|
||||
cd-gpios = <&gpio2 0 0>;
|
||||
wp-gpios = <&gpio2 1 0>;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -97,18 +97,23 @@
|
|||
dma-apbh@00110000 {
|
||||
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
|
||||
reg = <0x00110000 0x2000>;
|
||||
clocks = <&clks 106>;
|
||||
};
|
||||
|
||||
gpmi-nand@00112000 {
|
||||
compatible = "fsl,imx6q-gpmi-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
|
||||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <0 13 0x04>, <0 15 0x04>;
|
||||
interrupt-names = "gpmi-dma", "bch";
|
||||
fsl,gpmi-dma-channel = <0>;
|
||||
status = "disabled";
|
||||
compatible = "fsl,imx6q-gpmi-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
|
||||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <0 13 0x04>, <0 15 0x04>;
|
||||
interrupt-names = "gpmi-dma", "bch";
|
||||
clocks = <&clks 152>, <&clks 153>, <&clks 151>,
|
||||
<&clks 150>, <&clks 149>;
|
||||
clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
|
||||
"gpmi_bch_apb", "per1_bch";
|
||||
fsl,gpmi-dma-channel = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@00a00600 {
|
||||
|
|
@ -150,6 +155,8 @@
|
|||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02008000 0x4000>;
|
||||
interrupts = <0 31 0x04>;
|
||||
clocks = <&clks 112>, <&clks 112>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -159,6 +166,8 @@
|
|||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x0200c000 0x4000>;
|
||||
interrupts = <0 32 0x04>;
|
||||
clocks = <&clks 113>, <&clks 113>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -168,6 +177,8 @@
|
|||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02010000 0x4000>;
|
||||
interrupts = <0 33 0x04>;
|
||||
clocks = <&clks 114>, <&clks 114>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -177,6 +188,8 @@
|
|||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02014000 0x4000>;
|
||||
interrupts = <0 34 0x04>;
|
||||
clocks = <&clks 115>, <&clks 115>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -186,6 +199,8 @@
|
|||
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x02018000 0x4000>;
|
||||
interrupts = <0 35 0x04>;
|
||||
clocks = <&clks 116>, <&clks 116>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -193,6 +208,8 @@
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -205,6 +222,7 @@
|
|||
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <0 46 0x04>;
|
||||
clocks = <&clks 178>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <38 37>;
|
||||
status = "disabled";
|
||||
|
|
@ -214,6 +232,7 @@
|
|||
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <0 47 0x04>;
|
||||
clocks = <&clks 179>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <42 41>;
|
||||
status = "disabled";
|
||||
|
|
@ -223,6 +242,7 @@
|
|||
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
|
||||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <0 48 0x04>;
|
||||
clocks = <&clks 180>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <46 45>;
|
||||
status = "disabled";
|
||||
|
|
@ -362,20 +382,22 @@
|
|||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020bc000 0x4000>;
|
||||
interrupts = <0 80 0x04>;
|
||||
status = "disabled";
|
||||
clocks = <&clks 0>;
|
||||
};
|
||||
|
||||
wdog@020c0000 { /* WDOG2 */
|
||||
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x020c0000 0x4000>;
|
||||
interrupts = <0 81 0x04>;
|
||||
clocks = <&clks 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ccm@020c4000 {
|
||||
clks: ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 0x04 0 88 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
anatop@020c8000 {
|
||||
|
|
@ -472,12 +494,14 @@
|
|||
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020c9000 0x1000>;
|
||||
interrupts = <0 44 0x04>;
|
||||
clocks = <&clks 182>;
|
||||
};
|
||||
|
||||
usbphy2: usbphy@020ca000 {
|
||||
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020ca000 0x1000>;
|
||||
interrupts = <0 45 0x04>;
|
||||
clocks = <&clks 183>;
|
||||
};
|
||||
|
||||
snvs@020cc000 {
|
||||
|
|
@ -514,86 +538,207 @@
|
|||
/* shared pinctrl settings */
|
||||
audmux {
|
||||
pinctrl_audmux_1: audmux-1 {
|
||||
fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
|
||||
1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
|
||||
11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
|
||||
3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
|
||||
};
|
||||
};
|
||||
|
||||
gpmi-nand {
|
||||
pinctrl_gpmi_nand_1: gpmi-nand-1 {
|
||||
fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
|
||||
1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
|
||||
1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
|
||||
1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
|
||||
1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
|
||||
1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
|
||||
1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
|
||||
1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
|
||||
1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
|
||||
1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
|
||||
1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
|
||||
1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
|
||||
1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
|
||||
1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
|
||||
1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
|
||||
1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
|
||||
1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
|
||||
1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
|
||||
1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
pinctrl_i2c1_1: i2c1grp-1 {
|
||||
fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
|
||||
196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */
|
||||
};
|
||||
};
|
||||
|
||||
serial2 {
|
||||
pinctrl_serial2_1: serial2grp-1 {
|
||||
fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
|
||||
191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */
|
||||
};
|
||||
};
|
||||
|
||||
usdhc3 {
|
||||
pinctrl_usdhc3_1: usdhc3grp-1 {
|
||||
fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
|
||||
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
|
||||
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
|
||||
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
|
||||
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
|
||||
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
|
||||
1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
|
||||
1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
|
||||
1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
|
||||
1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
|
||||
};
|
||||
};
|
||||
|
||||
usdhc4 {
|
||||
pinctrl_usdhc4_1: usdhc4grp-1 {
|
||||
fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
|
||||
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
|
||||
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
|
||||
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
|
||||
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
|
||||
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
|
||||
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
|
||||
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
|
||||
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
|
||||
1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
|
||||
fsl,pins = <
|
||||
18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
|
||||
1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
|
||||
11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
|
||||
3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
|
||||
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
|
||||
94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
|
||||
fsl,pins = <
|
||||
101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
|
||||
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
|
||||
94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
enet {
|
||||
pinctrl_enet_1: enetgrp-1 {
|
||||
fsl,pins = <
|
||||
695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
|
||||
756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
|
||||
24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
|
||||
30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
|
||||
34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
|
||||
39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
|
||||
44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
|
||||
56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
|
||||
702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
|
||||
74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
|
||||
52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
|
||||
61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
|
||||
66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
|
||||
70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
|
||||
48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet_2: enetgrp-2 {
|
||||
fsl,pins = <
|
||||
890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
|
||||
909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
|
||||
24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
|
||||
30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
|
||||
34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
|
||||
39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
|
||||
44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
|
||||
56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
|
||||
702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
|
||||
74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
|
||||
52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
|
||||
61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
|
||||
66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
|
||||
70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
|
||||
48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
gpmi-nand {
|
||||
pinctrl_gpmi_nand_1: gpmi-nand-1 {
|
||||
fsl,pins = <
|
||||
1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
|
||||
1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
|
||||
1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
|
||||
1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
|
||||
1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
|
||||
1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
|
||||
1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
|
||||
1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
|
||||
1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
|
||||
1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
|
||||
1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
|
||||
1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
|
||||
1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
|
||||
1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
|
||||
1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
|
||||
1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
|
||||
1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
|
||||
1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
|
||||
1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
pinctrl_i2c1_1: i2c1grp-1 {
|
||||
fsl,pins = <
|
||||
137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
|
||||
196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
|
||||
1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
|
||||
191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart4 {
|
||||
pinctrl_uart4_1: uart4grp-1 {
|
||||
fsl,pins = <
|
||||
877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
|
||||
885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg {
|
||||
pinctrl_usbotg_1: usbotggrp-1 {
|
||||
fsl,pins = <
|
||||
1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc2 {
|
||||
pinctrl_usdhc2_1: usdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
|
||||
1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
|
||||
16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
|
||||
0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
|
||||
8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
|
||||
1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
|
||||
1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
|
||||
1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
|
||||
1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
|
||||
1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc3 {
|
||||
pinctrl_usdhc3_1: usdhc3grp-1 {
|
||||
fsl,pins = <
|
||||
1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
|
||||
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
|
||||
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
|
||||
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
|
||||
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
|
||||
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
|
||||
1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
|
||||
1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
|
||||
1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
|
||||
1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_2: usdhc3grp-2 {
|
||||
fsl,pins = <
|
||||
1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
|
||||
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
|
||||
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
|
||||
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
|
||||
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
|
||||
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc4 {
|
||||
pinctrl_usdhc4_1: usdhc4grp-1 {
|
||||
fsl,pins = <
|
||||
1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
|
||||
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
|
||||
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
|
||||
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
|
||||
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
|
||||
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
|
||||
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
|
||||
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
|
||||
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
|
||||
1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4_2: usdhc4grp-2 {
|
||||
fsl,pins = <
|
||||
1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
|
||||
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
|
||||
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
|
||||
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
|
||||
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
|
||||
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -612,6 +757,9 @@
|
|||
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x020ec000 0x4000>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&clks 155>, <&clks 155>;
|
||||
clock-names = "ipg", "ahb";
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -635,7 +783,9 @@
|
|||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184000 0x200>;
|
||||
interrupts = <0 43 0x04>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -643,7 +793,9 @@
|
|||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184200 0x200>;
|
||||
interrupts = <0 40 0x04>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbphy = <&usbphy2>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -651,6 +803,8 @@
|
|||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184400 0x200>;
|
||||
interrupts = <0 41 0x04>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -658,13 +812,24 @@
|
|||
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
||||
reg = <0x02184600 0x200>;
|
||||
interrupts = <0 42 0x04>;
|
||||
clocks = <&clks 162>;
|
||||
fsl,usbmisc = <&usbmisc 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc: usbmisc@02184800 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx6q-usbmisc";
|
||||
reg = <0x02184800 0x200>;
|
||||
clocks = <&clks 162>;
|
||||
};
|
||||
|
||||
ethernet@02188000 {
|
||||
compatible = "fsl,imx6q-fec";
|
||||
reg = <0x02188000 0x4000>;
|
||||
interrupts = <0 118 0x04 0 119 0x04>;
|
||||
clocks = <&clks 117>, <&clks 117>;
|
||||
clock-names = "ipg", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -677,6 +842,8 @@
|
|||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02190000 0x4000>;
|
||||
interrupts = <0 22 0x04>;
|
||||
clocks = <&clks 163>, <&clks 163>, <&clks 163>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -684,6 +851,8 @@
|
|||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02194000 0x4000>;
|
||||
interrupts = <0 23 0x04>;
|
||||
clocks = <&clks 164>, <&clks 164>, <&clks 164>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -691,6 +860,8 @@
|
|||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x02198000 0x4000>;
|
||||
interrupts = <0 24 0x04>;
|
||||
clocks = <&clks 165>, <&clks 165>, <&clks 165>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -698,6 +869,8 @@
|
|||
compatible = "fsl,imx6q-usdhc";
|
||||
reg = <0x0219c000 0x4000>;
|
||||
interrupts = <0 25 0x04>;
|
||||
clocks = <&clks 166>, <&clks 166>, <&clks 166>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -707,6 +880,7 @@
|
|||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a0000 0x4000>;
|
||||
interrupts = <0 36 0x04>;
|
||||
clocks = <&clks 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -716,6 +890,7 @@
|
|||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a4000 0x4000>;
|
||||
interrupts = <0 37 0x04>;
|
||||
clocks = <&clks 126>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -725,6 +900,7 @@
|
|||
compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
|
||||
reg = <0x021a8000 0x4000>;
|
||||
interrupts = <0 38 0x04>;
|
||||
clocks = <&clks 127>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -788,6 +964,8 @@
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021e8000 0x4000>;
|
||||
interrupts = <0 27 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -795,6 +973,8 @@
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021ec000 0x4000>;
|
||||
interrupts = <0 28 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -802,6 +982,8 @@
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f0000 0x4000>;
|
||||
interrupts = <0 29 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -809,6 +991,8 @@
|
|||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f4000 0x4000>;
|
||||
interrupts = <0 30 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,6 +25,16 @@
|
|||
};
|
||||
};
|
||||
|
||||
gpio_fan {
|
||||
/* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&gpio1 14 1
|
||||
&gpio1 13 1>;
|
||||
gpio-fan,speed-map = <0 0
|
||||
3000 1
|
||||
6000 2>;
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
sata@80000 {
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Seagate FreeAgent Dockstar";
|
||||
compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x8000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
serial@12000 {
|
||||
clock-frequency = <200000000>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
nand@3000000 {
|
||||
status = "okay";
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0000000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "uImage";
|
||||
reg = <0x0100000 0x400000>;
|
||||
};
|
||||
|
||||
partition@500000 {
|
||||
label = "data";
|
||||
reg = <0x0500000 0xfb00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
health {
|
||||
label = "status:green:health";
|
||||
gpios = <&gpio1 14 1>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
fault {
|
||||
label = "status:orange:fault";
|
||||
gpios = <&gpio1 15 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -12,7 +12,7 @@
|
|||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)";
|
||||
bootargs = "console=ttyS0,115200n8 earlyprintk";
|
||||
linux,initrd-start = <0x4500040>;
|
||||
linux,initrd-end = <0x4800000>;
|
||||
};
|
||||
|
|
@ -30,7 +30,37 @@
|
|||
clock-frequency = <200000000>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
nand@3000000 {
|
||||
status = "okay";
|
||||
|
||||
partition@0 {
|
||||
label = "uboot";
|
||||
reg = <0x0000000 0xc0000>;
|
||||
};
|
||||
|
||||
partition@a0000 {
|
||||
label = "env";
|
||||
reg = <0xa0000 0x20000>;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "zImage";
|
||||
reg = <0x100000 0x300000>;
|
||||
};
|
||||
|
||||
partition@540000 {
|
||||
label = "initrd";
|
||||
reg = <0x540000 0x300000>;
|
||||
};
|
||||
|
||||
partition@980000 {
|
||||
label = "boot";
|
||||
reg = <0x980000 0x1f400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
|
|
@ -69,4 +99,22 @@
|
|||
gpios = <&gpio1 16 0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
button@1 {
|
||||
label = "OTB Button";
|
||||
linux,code = <133>;
|
||||
gpios = <&gpio1 3 1>;
|
||||
debounce-interval = <100>;
|
||||
};
|
||||
button@2 {
|
||||
label = "Reset";
|
||||
linux,code = <0x198>;
|
||||
gpios = <&gpio0 12 1>;
|
||||
debounce-interval = <100>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,105 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Iomega StorCenter ix2-200";
|
||||
compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8 earlyprintk";
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
i2c@11000 {
|
||||
status = "okay";
|
||||
|
||||
lm63: lm63@4c {
|
||||
compatible = "national,lm63";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
clock-frequency = <200000000>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
nand@3000000 {
|
||||
status = "okay";
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0000000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@a0000 {
|
||||
label = "env";
|
||||
reg = <0xa0000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "uImage";
|
||||
reg = <0x100000 0x300000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "uInitrd";
|
||||
reg = <0x540000 0x1000000>;
|
||||
};
|
||||
};
|
||||
sata@80000 {
|
||||
status = "okay";
|
||||
nr-ports = <2>;
|
||||
};
|
||||
|
||||
};
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power_led {
|
||||
label = "status:white:power_led";
|
||||
gpios = <&gpio0 16 0>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
health_led1 {
|
||||
label = "status:red:health_led";
|
||||
gpios = <&gpio1 5 0>;
|
||||
};
|
||||
health_led2 {
|
||||
label = "status:white:health_led";
|
||||
gpios = <&gpio1 4 0>;
|
||||
};
|
||||
backup_led {
|
||||
label = "status:blue:backup_led";
|
||||
gpios = <&gpio0 15 0>;
|
||||
};
|
||||
};
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
Power {
|
||||
label = "Power Button";
|
||||
linux,code = <116>;
|
||||
gpios = <&gpio0 14 1>;
|
||||
};
|
||||
Reset {
|
||||
label = "Reset Button";
|
||||
linux,code = <0x198>;
|
||||
gpios = <&gpio0 12 1>;
|
||||
};
|
||||
OTB {
|
||||
label = "OTB Button";
|
||||
linux,code = <133>;
|
||||
gpios = <&gpio1 3 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "kirkwood.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Keymile Kirkwood Reference Design";
|
||||
compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8 earlyprintk";
|
||||
};
|
||||
|
||||
ocp@f1000000 {
|
||||
serial@12000 {
|
||||
clock-frequency = <200000000>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
nand@3000000 {
|
||||
status = "ok";
|
||||
chip-delay = <25>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -14,7 +14,8 @@
|
|||
|
||||
ocp@f1000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0xf1000000 0x4000000>;
|
||||
ranges = <0x00000000 0xf1000000 0x4000000
|
||||
0xf5000000 0xf5000000 0x0000400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
@ -105,5 +106,14 @@
|
|||
clock-frequency = <100000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "marvell,orion-crypto";
|
||||
reg = <0x30000 0x10000>,
|
||||
<0xf5000000 0x800>;
|
||||
reg-names = "regs", "sram";
|
||||
interrupts = <22>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -26,6 +26,11 @@
|
|||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,tauros2-cache";
|
||||
marvell,tauros2-cache-features = <0x3>;
|
||||
};
|
||||
|
||||
axi@d4200000 { /* AXI */
|
||||
compatible = "mrvl,axi-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
compatible = "qcom,msm8660-surf", "qcom,msm8660";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
intc: interrupt-controller@02080000 {
|
||||
intc: interrupt-controller@2080000 {
|
||||
compatible = "qcom,msm-8660-qgic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -15,6 +15,23 @@
|
|||
< 0x02081000 0x1000 >;
|
||||
};
|
||||
|
||||
timer@2000004 {
|
||||
compatible = "qcom,msm-gpt", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>;
|
||||
reg = <0x02000004 0x10>;
|
||||
clock-frequency = <32768>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
|
||||
timer@2000024 {
|
||||
compatible = "qcom,msm-dgt", "qcom,msm-timer";
|
||||
interrupts = <1 0 0x301>;
|
||||
reg = <0x02000024 0x10>,
|
||||
<0x02000034 0x4>;
|
||||
clock-frequency = <6750000>;
|
||||
cpu-offset = <0x40000>;
|
||||
};
|
||||
|
||||
serial@19c400000 {
|
||||
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
|
||||
reg = <0x19c40000 0x1000>,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm MSM8960 CDP";
|
||||
compatible = "qcom,msm8960-cdp", "qcom,msm8960";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
intc: interrupt-controller@2000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = < 0x02000000 0x1000 >,
|
||||
< 0x02002000 0x1000 >;
|
||||
};
|
||||
|
||||
timer@200a004 {
|
||||
compatible = "qcom,msm-gpt", "qcom,msm-timer";
|
||||
interrupts = <1 2 0x301>;
|
||||
reg = <0x0200a004 0x10>;
|
||||
clock-frequency = <32768>;
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
|
||||
timer@200a024 {
|
||||
compatible = "qcom,msm-dgt", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>;
|
||||
reg = <0x0200a024 0x10>,
|
||||
<0x0200a034 0x4>;
|
||||
clock-frequency = <6750000>;
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
|
||||
serial@19c400000 {
|
||||
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
|
||||
reg = <0x16440000 0x1000>,
|
||||
<0x16400000 0x1000>;
|
||||
interrupts = <0 154 0x0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -7,7 +7,7 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap2.dtsi"
|
||||
/include/ "omap2420.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP2420 H4 board";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Device Tree Source for OMAP2420 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "omap2.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,omap2420", "ti,omap2";
|
||||
|
||||
ocp {
|
||||
omap2420_pmx: pinmux@48000030 {
|
||||
compatible = "ti,omap2420-padconf", "pinctrl-single";
|
||||
reg = <0x48000030 0x0113>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <8>;
|
||||
pinctrl-single,function-mask = <0x3f>;
|
||||
};
|
||||
|
||||
mcbsp1: mcbsp@48074000 {
|
||||
compatible = "ti,omap2420-mcbsp";
|
||||
reg = <0x48074000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <59>, /* TX interrupt */
|
||||
<60>; /* RX interrupt */
|
||||
interrupt-names = "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,hwmods = "mcbsp1";
|
||||
};
|
||||
|
||||
mcbsp2: mcbsp@48076000 {
|
||||
compatible = "ti,omap2420-mcbsp";
|
||||
reg = <0x48076000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <62>, /* TX interrupt */
|
||||
<63>; /* RX interrupt */
|
||||
interrupt-names = "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,hwmods = "mcbsp2";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Device Tree Source for OMAP243x SoC
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "omap2.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,omap2430", "ti,omap2";
|
||||
|
||||
ocp {
|
||||
omap2430_pmx: pinmux@49002030 {
|
||||
compatible = "ti,omap2430-padconf", "pinctrl-single";
|
||||
reg = <0x49002030 0x0154>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <8>;
|
||||
pinctrl-single,function-mask = <0x3f>;
|
||||
};
|
||||
|
||||
mcbsp1: mcbsp@48074000 {
|
||||
compatible = "ti,omap2430-mcbsp";
|
||||
reg = <0x48074000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <64>, /* OCP compliant interrupt */
|
||||
<59>, /* TX interrupt */
|
||||
<60>, /* RX interrupt */
|
||||
<61>; /* RX overflow interrupt */
|
||||
interrupt-names = "common", "tx", "rx", "rx_overflow";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp1";
|
||||
};
|
||||
|
||||
mcbsp2: mcbsp@48076000 {
|
||||
compatible = "ti,omap2430-mcbsp";
|
||||
reg = <0x48076000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <16>, /* OCP compliant interrupt */
|
||||
<62>, /* TX interrupt */
|
||||
<63>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp2";
|
||||
};
|
||||
|
||||
mcbsp3: mcbsp@4808c000 {
|
||||
compatible = "ti,omap2430-mcbsp";
|
||||
reg = <0x4808c000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <17>, /* OCP compliant interrupt */
|
||||
<89>, /* TX interrupt */
|
||||
<90>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp3";
|
||||
};
|
||||
|
||||
mcbsp4: mcbsp@4808e000 {
|
||||
compatible = "ti,omap2430-mcbsp";
|
||||
reg = <0x4808e000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <18>, /* OCP compliant interrupt */
|
||||
<54>, /* TX interrupt */
|
||||
<55>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp4";
|
||||
};
|
||||
|
||||
mcbsp5: mcbsp@48096000 {
|
||||
compatible = "ti,omap2430-mcbsp";
|
||||
reg = <0x48096000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <19>, /* OCP compliant interrupt */
|
||||
<81>, /* TX interrupt */
|
||||
<82>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp5";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -7,16 +7,44 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap3.dtsi"
|
||||
/include/ "omap36xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP3 BeagleBoard";
|
||||
compatible = "ti,omap3-beagle", "ti,omap3";
|
||||
model = "TI OMAP3 BeagleBoard xM";
|
||||
compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pmu_stat {
|
||||
label = "beagleboard::pmu_stat";
|
||||
gpios = <&twl_gpio 19 0>; /* LEDB */
|
||||
};
|
||||
|
||||
heartbeat {
|
||||
label = "beagleboard::usr0";
|
||||
gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
mmc {
|
||||
label = "beagleboard::usr1";
|
||||
gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ti,omap-twl4030";
|
||||
ti,model = "omap3beagle";
|
||||
|
||||
ti,mcbsp = <&mcbsp2>;
|
||||
ti,codec = <&twl_audio>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
|
|
@ -27,11 +55,17 @@
|
|||
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
vsim: regulator@10 {
|
||||
vsim: regulator-vsim {
|
||||
compatible = "ti,twl4030-vsim";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
twl_audio: audio {
|
||||
compatible = "ti,twl4030-audio";
|
||||
codec {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -67,3 +101,15 @@
|
|||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
/* pullups: BIT(1) */
|
||||
ti,pullups = <0x000002>;
|
||||
/*
|
||||
* pulldowns:
|
||||
* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
|
||||
* BIT(15), BIT(16), BIT(17)
|
||||
*/
|
||||
ti,pulldowns = <0x03a1c4>;
|
||||
};
|
||||
|
|
@ -17,6 +17,15 @@
|
|||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
ledb {
|
||||
label = "omap3evm::ledb";
|
||||
gpios = <&twl_gpio 19 0>; /* LEDB */
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
|
|
@ -46,3 +55,7 @@
|
|||
reg = <0x5c>;
|
||||
};
|
||||
};
|
||||
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The Gumstix Overo must be combined with an expansion board.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap3.dtsi"
|
||||
|
||||
/ {
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
overo {
|
||||
label = "overo:blue:COM";
|
||||
gpios = <&twl_gpio 19 0>;
|
||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <2600000>;
|
||||
|
||||
twl: twl@48 {
|
||||
reg = <0x48>;
|
||||
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "twl4030.dtsi"
|
||||
|
||||
/* i2c2 pins are used for gpio */
|
||||
&i2c2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* on board microSD slot */
|
||||
&mmc1 {
|
||||
vmmc-supply = <&vmmc1>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
/* optional on board WiFi */
|
||||
&mmc2 {
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&twl_gpio {
|
||||
ti,use-leds;
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Tobi expansion board is manufactured by Gumstix Inc.
|
||||
*/
|
||||
|
||||
/include/ "omap3-overo.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP3 Gumstix Overo on Tobi";
|
||||
compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
heartbeat {
|
||||
label = "overo:red:gpio21";
|
||||
gpios = <&gpio1 21 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -17,7 +17,6 @@
|
|||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -69,6 +68,24 @@
|
|||
reg = <0x48200000 0x1000>;
|
||||
};
|
||||
|
||||
omap3_pmx_core: pinmux@48002030 {
|
||||
compatible = "ti,omap3-padconf", "pinctrl-single";
|
||||
reg = <0x48002030 0x05cc>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0x7fff>;
|
||||
};
|
||||
|
||||
omap3_pmx_wkup: pinmux@0x48002a58 {
|
||||
compatible = "ti,omap3-padconf", "pinctrl-single";
|
||||
reg = <0x48002a58 0x5c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0x7fff>;
|
||||
};
|
||||
|
||||
gpio1: gpio@48310000 {
|
||||
compatible = "ti,omap3-gpio";
|
||||
ti,hwmods = "gpio1";
|
||||
|
|
@ -141,12 +158,6 @@
|
|||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
uart4: serial@49042000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
i2c1: i2c@48070000 {
|
||||
compatible = "ti,omap3-i2c";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -220,5 +231,74 @@
|
|||
compatible = "ti,omap3-wdt";
|
||||
ti,hwmods = "wd_timer2";
|
||||
};
|
||||
|
||||
mcbsp1: mcbsp@48074000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x48074000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <16>, /* OCP compliant interrupt */
|
||||
<59>, /* TX interrupt */
|
||||
<60>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp1";
|
||||
};
|
||||
|
||||
mcbsp2: mcbsp@49022000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x49022000 0xff>,
|
||||
<0x49028000 0xff>;
|
||||
reg-names = "mpu", "sidetone";
|
||||
interrupts = <17>, /* OCP compliant interrupt */
|
||||
<62>, /* TX interrupt */
|
||||
<63>, /* RX interrupt */
|
||||
<4>; /* Sidetone */
|
||||
interrupt-names = "common", "tx", "rx", "sidetone";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <1280>;
|
||||
ti,hwmods = "mcbsp2";
|
||||
};
|
||||
|
||||
mcbsp3: mcbsp@49024000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x49024000 0xff>,
|
||||
<0x4902a000 0xff>;
|
||||
reg-names = "mpu", "sidetone";
|
||||
interrupts = <22>, /* OCP compliant interrupt */
|
||||
<89>, /* TX interrupt */
|
||||
<90>, /* RX interrupt */
|
||||
<5>; /* Sidetone */
|
||||
interrupt-names = "common", "tx", "rx", "sidetone";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp3";
|
||||
};
|
||||
|
||||
mcbsp4: mcbsp@49026000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x49026000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <23>, /* OCP compliant interrupt */
|
||||
<54>, /* TX interrupt */
|
||||
<55>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp4";
|
||||
};
|
||||
|
||||
mcbsp5: mcbsp@48096000 {
|
||||
compatible = "ti,omap3-mcbsp";
|
||||
reg = <0x48096000 0xff>;
|
||||
reg-names = "mpu";
|
||||
interrupts = <27>, /* OCP compliant interrupt */
|
||||
<81>, /* TX interrupt */
|
||||
<82>; /* RX interrupt */
|
||||
interrupt-names = "common", "tx", "rx";
|
||||
interrupt-parent = <&intc>;
|
||||
ti,buffer-size = <128>;
|
||||
ti,hwmods = "mcbsp5";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Device Tree Source for OMAP3 SoC
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "omap3.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial3 = &uart4;
|
||||
};
|
||||
|
||||
ocp {
|
||||
uart4: serial@49042000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -8,6 +8,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "omap4.dtsi"
|
||||
/include/ "elpida_ecb240abacn.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP4 PandaBoard";
|
||||
|
|
@ -126,3 +127,13 @@
|
|||
ti,non-removable;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&emif1 {
|
||||
cs1-used;
|
||||
device-handle = <&elpida_ECB240ABACN>;
|
||||
};
|
||||
|
||||
&emif2 {
|
||||
cs1-used;
|
||||
device-handle = <&elpida_ECB240ABACN>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "omap4.dtsi"
|
||||
/include/ "elpida_ecb240abacn.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP4 SDP board";
|
||||
|
|
@ -18,7 +19,7 @@
|
|||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
|
||||
vdd_eth: fixedregulator@0 {
|
||||
vdd_eth: fixedregulator-vdd-eth {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_ETH";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
|
|
@ -28,7 +29,7 @@
|
|||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vbat: fixedregulator@2 {
|
||||
vbat: fixedregulator-vbat {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VBAT";
|
||||
regulator-min-microvolt = <3750000>;
|
||||
|
|
@ -115,6 +116,33 @@
|
|||
};
|
||||
};
|
||||
|
||||
&omap4_pmx_core {
|
||||
uart2_pins: pinmux_uart2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0xd8 0x118 /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
|
||||
0xda 0 /* uart2_rts.uart2_rts OUTPUT | MODE0 */
|
||||
0xdc 0x118 /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
|
||||
0xde 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart3_pins: pinmux_uart3_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x100 0x118 /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
|
||||
0x102 0 /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
|
||||
0x104 0x100 /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
|
||||
0x106 0 /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart4_pins: pinmux_uart4_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x11c 0x100 /* uart4_rx.uart4_rx INPUT | MODE0 */
|
||||
0x11e 0 /* uart4_tx.uart4_tx OUTPUT | MODE0 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
|
|
@ -226,3 +254,98 @@
|
|||
bus-width = <4>;
|
||||
ti,non-removable;
|
||||
};
|
||||
|
||||
&emif1 {
|
||||
cs1-used;
|
||||
device-handle = <&elpida_ECB240ABACN>;
|
||||
};
|
||||
|
||||
&emif2 {
|
||||
cs1-used;
|
||||
device-handle = <&elpida_ECB240ABACN>;
|
||||
};
|
||||
|
||||
&keypad {
|
||||
keypad,num-rows = <8>;
|
||||
keypad,num-columns = <8>;
|
||||
linux,keymap = <0x00000012 /* KEY_E */
|
||||
0x00010013 /* KEY_R */
|
||||
0x00020014 /* KEY_T */
|
||||
0x00030066 /* KEY_HOME */
|
||||
0x0004003f /* KEY_F5 */
|
||||
0x000500f0 /* KEY_UNKNOWN */
|
||||
0x00060017 /* KEY_I */
|
||||
0x0007002a /* KEY_LEFTSHIFT */
|
||||
0x01000020 /* KEY_D*/
|
||||
0x01010021 /* KEY_F */
|
||||
0x01020022 /* KEY_G */
|
||||
0x010300e7 /* KEY_SEND */
|
||||
0x01040040 /* KEY_F6 */
|
||||
0x010500f0 /* KEY_UNKNOWN */
|
||||
0x01060025 /* KEY_K */
|
||||
0x0107001c /* KEY_ENTER */
|
||||
0x0200002d /* KEY_X */
|
||||
0x0201002e /* KEY_C */
|
||||
0x0202002f /* KEY_V */
|
||||
0x0203006b /* KEY_END */
|
||||
0x02040041 /* KEY_F7 */
|
||||
0x020500f0 /* KEY_UNKNOWN */
|
||||
0x02060034 /* KEY_DOT */
|
||||
0x0207003a /* KEY_CAPSLOCK */
|
||||
0x0300002c /* KEY_Z */
|
||||
0x0301004e /* KEY_KPLUS */
|
||||
0x03020030 /* KEY_B */
|
||||
0x0303003b /* KEY_F1 */
|
||||
0x03040042 /* KEY_F8 */
|
||||
0x030500f0 /* KEY_UNKNOWN */
|
||||
0x03060018 /* KEY_O */
|
||||
0x03070039 /* KEY_SPACE */
|
||||
0x04000011 /* KEY_W */
|
||||
0x04010015 /* KEY_Y */
|
||||
0x04020016 /* KEY_U */
|
||||
0x0403003c /* KEY_F2 */
|
||||
0x04040073 /* KEY_VOLUMEUP */
|
||||
0x040500f0 /* KEY_UNKNOWN */
|
||||
0x04060026 /* KEY_L */
|
||||
0x04070069 /* KEY_LEFT */
|
||||
0x0500001f /* KEY_S */
|
||||
0x05010023 /* KEY_H */
|
||||
0x05020024 /* KEY_J */
|
||||
0x0503003d /* KEY_F3 */
|
||||
0x05040043 /* KEY_F9 */
|
||||
0x05050072 /* KEY_VOLUMEDOWN */
|
||||
0x05060032 /* KEY_M */
|
||||
0x0507006a /* KEY_RIGHT */
|
||||
0x06000010 /* KEY_Q */
|
||||
0x0601001e /* KEY_A */
|
||||
0x06020031 /* KEY_N */
|
||||
0x0603009e /* KEY_BACK */
|
||||
0x0604000e /* KEY_BACKSPACE */
|
||||
0x060500f0 /* KEY_UNKNOWN */
|
||||
0x06060019 /* KEY_P */
|
||||
0x06070067 /* KEY_UP */
|
||||
0x07000094 /* KEY_PROG1 */
|
||||
0x07010095 /* KEY_PROG2 */
|
||||
0x070200ca /* KEY_PROG3 */
|
||||
0x070300cb /* KEY_PROG4 */
|
||||
0x0704003e /* KEY_F4 */
|
||||
0x070500f0 /* KEY_UNKNOWN */
|
||||
0x07060160 /* KEY_OK */
|
||||
0x0707006c>; /* KEY_DOWN */
|
||||
linux,input-no-autorepeat;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins>;
|
||||
};
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue