staging: comedi: s626: cleanup comments in s626_initialize()
Cleanup the comments to follow the coding style of the kernel. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
98667bf7cc
commit
54a2a02ea5
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@ -2461,83 +2461,80 @@ static void s626_initialize(struct comedi_device *dev)
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uint16_t chan;
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int i;
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/* enab DEBI and audio pins, enable I2C interface. */
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/* Enable DEBI and audio pins, enable I2C interface */
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MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C);
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/* Configure DEBI operating mode. */
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WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */
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/* bits wide. */
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| (DEBI_TOUT << DEBI_CFG_TOUT_BIT)
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/* Declare DEBI */
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/* transfer timeout */
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/* interval. */
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|DEBI_SWAP /* Set up byte lane */
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/* steering. */
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| DEBI_CFG_INTEL); /* Intel-compatible */
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/* local bus (DEBI */
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/* never times out). */
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/*
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* Configure DEBI operating mode
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*
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* Local bus is 16 bits wide
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* Declare DEBI transfer timeout interval
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* Set up byte lane steering
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* Intel-compatible local bus (DEBI never times out)
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*/
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WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 |
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(DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
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DEBI_SWAP | DEBI_CFG_INTEL);
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/* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */
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/* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */
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/* Disable MMU paging */
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WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE);
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/* Paging is disabled. */
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WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */
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/* Init GPIO so that ADC Start* is negated. */
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/* Init GPIO so that ADC Start* is negated */
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WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
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/* I2C device address for onboard eeprom (revb) */
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devpriv->I2CAdrs = 0xA0;
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/* Issue an I2C ABORT command to halt any I2C operation in */
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/* progress and reset BUSY flag. */
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/*
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* Issue an I2C ABORT command to halt any I2C
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* operation in progress and reset BUSY flag.
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*/
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WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
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/* Write I2C control: abort any I2C activity. */
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MC_ENABLE(P_MC2, MC2_UPLD_IIC);
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/* Invoke command upload */
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while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
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;
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/* and wait for upload to complete. */
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/* Per SAA7146 data sheet, write to STATUS reg twice to
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* reset all I2C error flags. */
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/*
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* Per SAA7146 data sheet, write to STATUS
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* reg twice to reset all I2C error flags.
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*/
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for (i = 0; i < 2; i++) {
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WR7146(P_I2CSTAT, I2C_CLKSEL);
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/* Write I2C control: reset error flags. */
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MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */
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MC_ENABLE(P_MC2, MC2_UPLD_IIC);
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while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
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;
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/* and wait for upload to complete. */
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}
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/* Init audio interface functional attributes: set DAC/ADC
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/*
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* Init audio interface functional attributes: set DAC/ADC
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* serial clock rates, invert DAC serial clock so that
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* DAC data setup times are satisfied, enable DAC serial
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* clock out.
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*/
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WR7146(P_ACON2, ACON2_INIT);
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/* Set up TSL1 slot list, which is used to control the
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/*
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* Set up TSL1 slot list, which is used to control the
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* accumulation of ADC data: RSD1 = shift data in on SD1.
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* SIB_A1 = store data uint8_t at next available location in
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* FB BUFFER1 register. */
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* SIB_A1 = store data uint8_t at next available location
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* in FB BUFFER1 register.
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*/
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WR7146(P_TSL1, RSD1 | SIB_A1);
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/* Fetch ADC high data uint8_t. */
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WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
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/* Fetch ADC low data uint8_t; end of TSL1. */
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/* enab TSL1 slot list so that it executes all the time. */
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/* Enable TSL1 slot list so that it executes all the time */
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WR7146(P_ACON1, ACON1_ADCSTART);
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/* Initialize RPS registers used for ADC. */
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/* Physical start of RPS program. */
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WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
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/*
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* Initialize RPS registers used for ADC
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*/
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/* Physical start of RPS program */
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WR7146(P_RPSADDR1, (uint32_t)devpriv->RPSBuf.PhysicalBase);
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/* RPS program performs no explicit mem writes */
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WR7146(P_RPSPAGE1, 0);
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/* RPS program performs no explicit mem writes. */
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WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */
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/* Disable RPS timeouts */
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WR7146(P_RPS1_TOUT, 0);
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#if 0
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/*
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@ -2584,39 +2581,45 @@ static void s626_initialize(struct comedi_device *dev)
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}
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#endif /* SAA7146 BUG WORKAROUND */
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/* end initADC */
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/*
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* Initialize the DAC interface
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*/
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/* init the DAC interface */
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/* Init Audio2's output DMAC attributes: burst length = 1
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* DWORD, threshold = 1 DWORD.
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/*
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* Init Audio2's output DMAC attributes:
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* burst length = 1 DWORD
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* threshold = 1 DWORD.
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*/
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WR7146(P_PCI_BT_A, 0);
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/* Init Audio2's output DMA physical addresses. The protection
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/*
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* Init Audio2's output DMA physical addresses. The protection
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* address is set to 1 DWORD past the base address so that a
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* single DWORD will be transferred each time a DMA transfer is
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* enabled. */
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* enabled.
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*/
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pPhysBuf = devpriv->ANABuf.PhysicalBase +
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(DAC_WDMABUF_OS * sizeof(uint32_t));
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WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf);
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WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t)));
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WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */
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WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */
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/* Cache Audio2's output DMA buffer logical address. This is
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* where DAC data is buffered for A2 output DMA transfers. */
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/*
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* Cache Audio2's output DMA buffer logical address. This is
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* where DAC data is buffered for A2 output DMA transfers.
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*/
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devpriv->pDacWBuf = (uint32_t *)devpriv->ANABuf.LogicalBase +
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DAC_WDMABUF_OS;
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/* Audio2's output channels does not use paging. The protection
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* violation handling bit is set so that the DMAC will
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* automatically halt and its PCI address pointer will be reset
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* when the protection address is reached. */
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/*
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* Audio2's output channels does not use paging. The
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* protection violation handling bit is set so that the
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* DMAC will automatically halt and its PCI address pointer
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* will be reset when the protection address is reached.
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*/
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WR7146(P_PAGEA2_OUT, 8);
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/* Initialize time slot list 2 (TSL2), which is used to control
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/*
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* Initialize time slot list 2 (TSL2), which is used to control
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* the clock generation for and serialization of data to be sent
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* to the DAC devices. Slot 0 is a NOP that is used to trap TSL
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* execution; this permits other slots to be safely modified
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@ -2627,48 +2630,52 @@ static void s626_initialize(struct comedi_device *dev)
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* not yet finished executing.
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*/
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/* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
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SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
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/* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */
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/* Initialize slot 1, which is constant. Slot 1 causes a
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/*
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* Initialize slot 1, which is constant. Slot 1 causes a
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* DWORD to be transferred from audio channel 2's output FIFO
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* to the FIFO's output buffer so that it can be serialized
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* and sent to the DAC during subsequent slots. All remaining
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* slots are dynamically populated as required by the target
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* DAC device.
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*/
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SETVECT(1, LF_A2);
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/* Slot 1: Fetch DWORD from Audio2's output FIFO. */
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/* Start DAC's audio interface (TSL2) running. */
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/* Slot 1: Fetch DWORD from Audio2's output FIFO */
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SETVECT(1, LF_A2);
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/* Start DAC's audio interface (TSL2) running */
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WR7146(P_ACON1, ACON1_DACSTART);
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/* end init DAC interface */
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/* Init Trim DACs to calibrated values. Do it twice because the
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/*
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* Init Trim DACs to calibrated values. Do it twice because the
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* SAA7146 audio channel does not always reset properly and
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* sometimes causes the first few TrimDAC writes to malfunction.
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*/
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LoadTrimDACs(dev);
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LoadTrimDACs(dev); /* Insurance. */
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LoadTrimDACs(dev);
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/* Manually init all gate array hardware in case this is a soft
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/*
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* Manually init all gate array hardware in case this is a soft
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* reset (we have no way of determining whether this is a warm
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* or cold start). This is necessary because the gate array will
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* reset only in response to a PCI hard reset; there is no soft
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* reset function. */
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* reset function.
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*/
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/* Init all DAC outputs to 0V and init all DAC setpoint and
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/*
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* Init all DAC outputs to 0V and init all DAC setpoint and
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* polarity images.
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*/
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for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
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SetDAC(dev, chan, 0);
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/* Init counters. */
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/* Init counters */
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CountersInit(dev);
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/* Without modifying the state of the Battery Backup enab, disable
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/*
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* Without modifying the state of the Battery Backup enab, disable
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* the watchdog timer, set DIO channels 0-5 to operate in the
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* standard DIO (vs. counter overflow) mode, disable the battery
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* charger, and reset the watchdog interval selector to zero.
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@ -2676,11 +2683,11 @@ static void s626_initialize(struct comedi_device *dev)
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WriteMISC2(dev, (uint16_t)(DEBIread(dev, LP_RDMISC2) &
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MISC2_BATT_ENABLE));
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/* Initialize the digital I/O subsystem. */
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/* Initialize the digital I/O subsystem */
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s626_dio_init(dev);
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/* enable interrupt test */
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/* writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */
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/* writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER); */
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}
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static int s626_attach_pci(struct comedi_device *dev, struct pci_dev *pcidev)
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