From 54a2a02ea51f606ba37f800c5e5eebb049ca6fb8 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Mon, 24 Sep 2012 13:39:14 -0700 Subject: [PATCH] staging: comedi: s626: cleanup comments in s626_initialize() Cleanup the comments to follow the coding style of the kernel. Signed-off-by: H Hartley Sweeten Cc: Ian Abbott Signed-off-by: Greg Kroah-Hartman --- drivers/staging/comedi/drivers/s626.c | 165 ++++++++++++++------------ 1 file changed, 86 insertions(+), 79 deletions(-) diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c index 6f1705ba60e2..e1d10f366c2f 100644 --- a/drivers/staging/comedi/drivers/s626.c +++ b/drivers/staging/comedi/drivers/s626.c @@ -2461,83 +2461,80 @@ static void s626_initialize(struct comedi_device *dev) uint16_t chan; int i; - /* enab DEBI and audio pins, enable I2C interface. */ + /* Enable DEBI and audio pins, enable I2C interface */ MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C); - /* Configure DEBI operating mode. */ - WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */ - /* bits wide. */ - | (DEBI_TOUT << DEBI_CFG_TOUT_BIT) - /* Declare DEBI */ - /* transfer timeout */ - /* interval. */ - |DEBI_SWAP /* Set up byte lane */ - /* steering. */ - | DEBI_CFG_INTEL); /* Intel-compatible */ - /* local bus (DEBI */ - /* never times out). */ + /* + * Configure DEBI operating mode + * + * Local bus is 16 bits wide + * Declare DEBI transfer timeout interval + * Set up byte lane steering + * Intel-compatible local bus (DEBI never times out) + */ + WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 | + (DEBI_TOUT << DEBI_CFG_TOUT_BIT) | + DEBI_SWAP | DEBI_CFG_INTEL); - /* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */ - /* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */ + /* Disable MMU paging */ + WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); - /* Paging is disabled. */ - WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */ - - /* Init GPIO so that ADC Start* is negated. */ + /* Init GPIO so that ADC Start* is negated */ WR7146(P_GPIO, GPIO_BASE | GPIO1_HI); /* I2C device address for onboard eeprom (revb) */ devpriv->I2CAdrs = 0xA0; - /* Issue an I2C ABORT command to halt any I2C operation in */ - /* progress and reset BUSY flag. */ + /* + * Issue an I2C ABORT command to halt any I2C + * operation in progress and reset BUSY flag. + */ WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT); - /* Write I2C control: abort any I2C activity. */ MC_ENABLE(P_MC2, MC2_UPLD_IIC); - /* Invoke command upload */ while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0) ; - /* and wait for upload to complete. */ - /* Per SAA7146 data sheet, write to STATUS reg twice to - * reset all I2C error flags. */ + /* + * Per SAA7146 data sheet, write to STATUS + * reg twice to reset all I2C error flags. + */ for (i = 0; i < 2; i++) { WR7146(P_I2CSTAT, I2C_CLKSEL); - /* Write I2C control: reset error flags. */ - MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */ + MC_ENABLE(P_MC2, MC2_UPLD_IIC); while (!MC_TEST(P_MC2, MC2_UPLD_IIC)) ; - /* and wait for upload to complete. */ } - /* Init audio interface functional attributes: set DAC/ADC + /* + * Init audio interface functional attributes: set DAC/ADC * serial clock rates, invert DAC serial clock so that * DAC data setup times are satisfied, enable DAC serial * clock out. */ - WR7146(P_ACON2, ACON2_INIT); - /* Set up TSL1 slot list, which is used to control the + /* + * Set up TSL1 slot list, which is used to control the * accumulation of ADC data: RSD1 = shift data in on SD1. - * SIB_A1 = store data uint8_t at next available location in - * FB BUFFER1 register. */ + * SIB_A1 = store data uint8_t at next available location + * in FB BUFFER1 register. + */ WR7146(P_TSL1, RSD1 | SIB_A1); - /* Fetch ADC high data uint8_t. */ WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS); - /* Fetch ADC low data uint8_t; end of TSL1. */ - /* enab TSL1 slot list so that it executes all the time. */ + /* Enable TSL1 slot list so that it executes all the time */ WR7146(P_ACON1, ACON1_ADCSTART); - /* Initialize RPS registers used for ADC. */ - - /* Physical start of RPS program. */ - WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase); + /* + * Initialize RPS registers used for ADC + */ + /* Physical start of RPS program */ + WR7146(P_RPSADDR1, (uint32_t)devpriv->RPSBuf.PhysicalBase); + /* RPS program performs no explicit mem writes */ WR7146(P_RPSPAGE1, 0); - /* RPS program performs no explicit mem writes. */ - WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */ + /* Disable RPS timeouts */ + WR7146(P_RPS1_TOUT, 0); #if 0 /* @@ -2584,39 +2581,45 @@ static void s626_initialize(struct comedi_device *dev) } #endif /* SAA7146 BUG WORKAROUND */ - /* end initADC */ + /* + * Initialize the DAC interface + */ - /* init the DAC interface */ - - /* Init Audio2's output DMAC attributes: burst length = 1 - * DWORD, threshold = 1 DWORD. + /* + * Init Audio2's output DMAC attributes: + * burst length = 1 DWORD + * threshold = 1 DWORD. */ WR7146(P_PCI_BT_A, 0); - /* Init Audio2's output DMA physical addresses. The protection + /* + * Init Audio2's output DMA physical addresses. The protection * address is set to 1 DWORD past the base address so that a * single DWORD will be transferred each time a DMA transfer is - * enabled. */ - + * enabled. + */ pPhysBuf = devpriv->ANABuf.PhysicalBase + (DAC_WDMABUF_OS * sizeof(uint32_t)); + WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); + WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); - WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */ - WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */ - - /* Cache Audio2's output DMA buffer logical address. This is - * where DAC data is buffered for A2 output DMA transfers. */ + /* + * Cache Audio2's output DMA buffer logical address. This is + * where DAC data is buffered for A2 output DMA transfers. + */ devpriv->pDacWBuf = (uint32_t *)devpriv->ANABuf.LogicalBase + DAC_WDMABUF_OS; - /* Audio2's output channels does not use paging. The protection - * violation handling bit is set so that the DMAC will - * automatically halt and its PCI address pointer will be reset - * when the protection address is reached. */ - + /* + * Audio2's output channels does not use paging. The + * protection violation handling bit is set so that the + * DMAC will automatically halt and its PCI address pointer + * will be reset when the protection address is reached. + */ WR7146(P_PAGEA2_OUT, 8); - /* Initialize time slot list 2 (TSL2), which is used to control + /* + * Initialize time slot list 2 (TSL2), which is used to control * the clock generation for and serialization of data to be sent * to the DAC devices. Slot 0 is a NOP that is used to trap TSL * execution; this permits other slots to be safely modified @@ -2627,48 +2630,52 @@ static void s626_initialize(struct comedi_device *dev) * not yet finished executing. */ + /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */ SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS); - /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */ - /* Initialize slot 1, which is constant. Slot 1 causes a + /* + * Initialize slot 1, which is constant. Slot 1 causes a * DWORD to be transferred from audio channel 2's output FIFO * to the FIFO's output buffer so that it can be serialized * and sent to the DAC during subsequent slots. All remaining * slots are dynamically populated as required by the target * DAC device. */ - SETVECT(1, LF_A2); - /* Slot 1: Fetch DWORD from Audio2's output FIFO. */ - /* Start DAC's audio interface (TSL2) running. */ + /* Slot 1: Fetch DWORD from Audio2's output FIFO */ + SETVECT(1, LF_A2); + + /* Start DAC's audio interface (TSL2) running */ WR7146(P_ACON1, ACON1_DACSTART); - /* end init DAC interface */ - - /* Init Trim DACs to calibrated values. Do it twice because the + /* + * Init Trim DACs to calibrated values. Do it twice because the * SAA7146 audio channel does not always reset properly and * sometimes causes the first few TrimDAC writes to malfunction. */ - LoadTrimDACs(dev); - LoadTrimDACs(dev); /* Insurance. */ + LoadTrimDACs(dev); - /* Manually init all gate array hardware in case this is a soft + /* + * Manually init all gate array hardware in case this is a soft * reset (we have no way of determining whether this is a warm * or cold start). This is necessary because the gate array will * reset only in response to a PCI hard reset; there is no soft - * reset function. */ + * reset function. + */ - /* Init all DAC outputs to 0V and init all DAC setpoint and + /* + * Init all DAC outputs to 0V and init all DAC setpoint and * polarity images. */ for (chan = 0; chan < S626_DAC_CHANNELS; chan++) SetDAC(dev, chan, 0); - /* Init counters. */ + /* Init counters */ CountersInit(dev); - /* Without modifying the state of the Battery Backup enab, disable + /* + * Without modifying the state of the Battery Backup enab, disable * the watchdog timer, set DIO channels 0-5 to operate in the * standard DIO (vs. counter overflow) mode, disable the battery * charger, and reset the watchdog interval selector to zero. @@ -2676,11 +2683,11 @@ static void s626_initialize(struct comedi_device *dev) WriteMISC2(dev, (uint16_t)(DEBIread(dev, LP_RDMISC2) & MISC2_BATT_ENABLE)); - /* Initialize the digital I/O subsystem. */ + /* Initialize the digital I/O subsystem */ s626_dio_init(dev); /* enable interrupt test */ - /* writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */ + /* writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER); */ } static int s626_attach_pci(struct comedi_device *dev, struct pci_dev *pcidev)