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drm/i915: Switch to use HWS indices rather than addresses 

If we use the STORE_DATA_INDEX function we can use a fixed offset and
avoid having to lookup up the engine HWS address. A step closer to being
able to emit the final breadcrumb during request_add rather than later
in the submission interrupt handler.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190318095204.9913-9-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson 2019-03-18 09:51:51 +00:00
parent 7c1200456c
commit 54939ea0bd
4 changed files with 17 additions and 23 deletions
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3
drivers/gpu/drm/i915/intel_guc_submission.c
View File

@ -583,7 +583,8 @@ static void inject_preempt_context(struct work_struct *work)
} else { } else {
cs = gen8_emit_ggtt_write(cs, cs = gen8_emit_ggtt_write(cs,
GUC_PREEMPT_FINISHED, GUC_PREEMPT_FINISHED,
addr); addr,
0);
*cs++ = MI_NOOP; *cs++ = MI_NOOP;
*cs++ = MI_NOOP; *cs++ = MI_NOOP;
} }

17
drivers/gpu/drm/i915/intel_lrc.c
View File

@ -173,12 +173,6 @@ static void execlists_init_reg_state(u32 *reg_state,
struct intel_engine_cs *engine, struct intel_engine_cs *engine,
struct intel_ring *ring); struct intel_ring *ring);
static inline u32 intel_hws_hangcheck_address(struct intel_engine_cs *engine)
{
return (i915_ggtt_offset(engine->status_page.vma) +
I915_GEM_HWS_HANGCHECK_ADDR);
}
static inline struct i915_priolist *to_priolist(struct rb_node *rb) static inline struct i915_priolist *to_priolist(struct rb_node *rb)
{ {
return rb_entry(rb, struct i915_priolist, node); return rb_entry(rb, struct i915_priolist, node);
@ -2214,11 +2208,14 @@ static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
{ {
cs = gen8_emit_ggtt_write(cs, cs = gen8_emit_ggtt_write(cs,
request->fence.seqno, request->fence.seqno,
request->timeline->hwsp_offset); request->timeline->hwsp_offset,
0);
cs = gen8_emit_ggtt_write(cs, cs = gen8_emit_ggtt_write(cs,
intel_engine_next_hangcheck_seqno(request->engine), intel_engine_next_hangcheck_seqno(request->engine),
intel_hws_hangcheck_address(request->engine)); I915_GEM_HWS_HANGCHECK_ADDR,
MI_FLUSH_DW_STORE_INDEX);
*cs++ = MI_USER_INTERRUPT; *cs++ = MI_USER_INTERRUPT;
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
@ -2242,8 +2239,8 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
cs = gen8_emit_ggtt_write_rcs(cs, cs = gen8_emit_ggtt_write_rcs(cs,
intel_engine_next_hangcheck_seqno(request->engine), intel_engine_next_hangcheck_seqno(request->engine),
intel_hws_hangcheck_address(request->engine), I915_GEM_HWS_HANGCHECK_ADDR,
0); PIPE_CONTROL_STORE_DATA_INDEX);
*cs++ = MI_USER_INTERRUPT; *cs++ = MI_USER_INTERRUPT;
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

16
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@ -43,12 +43,6 @@
*/ */
#define LEGACY_REQUEST_SIZE 200 #define LEGACY_REQUEST_SIZE 200
static inline u32 hws_hangcheck_address(struct intel_engine_cs *engine)
{
return (i915_ggtt_offset(engine->status_page.vma) +
I915_GEM_HWS_HANGCHECK_ADDR);
}
unsigned int intel_ring_update_space(struct intel_ring *ring) unsigned int intel_ring_update_space(struct intel_ring *ring)
{ {
unsigned int space; unsigned int space;
@ -317,8 +311,8 @@ static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
*cs++ = rq->fence.seqno; *cs++ = rq->fence.seqno;
*cs++ = GFX_OP_PIPE_CONTROL(4); *cs++ = GFX_OP_PIPE_CONTROL(4);
*cs++ = PIPE_CONTROL_QW_WRITE; *cs++ = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_STORE_DATA_INDEX;
*cs++ = hws_hangcheck_address(rq->engine) | PIPE_CONTROL_GLOBAL_GTT; *cs++ = I915_GEM_HWS_HANGCHECK_ADDR | PIPE_CONTROL_GLOBAL_GTT;
*cs++ = intel_engine_next_hangcheck_seqno(rq->engine); *cs++ = intel_engine_next_hangcheck_seqno(rq->engine);
*cs++ = MI_USER_INTERRUPT; *cs++ = MI_USER_INTERRUPT;
@ -423,8 +417,10 @@ static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
*cs++ = rq->fence.seqno; *cs++ = rq->fence.seqno;
*cs++ = GFX_OP_PIPE_CONTROL(4); *cs++ = GFX_OP_PIPE_CONTROL(4);
*cs++ = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB; *cs++ = (PIPE_CONTROL_QW_WRITE |
*cs++ = hws_hangcheck_address(rq->engine); PIPE_CONTROL_STORE_DATA_INDEX |
PIPE_CONTROL_GLOBAL_GTT_IVB);
*cs++ = I915_GEM_HWS_HANGCHECK_ADDR;
*cs++ = intel_engine_next_hangcheck_seqno(rq->engine); *cs++ = intel_engine_next_hangcheck_seqno(rq->engine);
*cs++ = MI_USER_INTERRUPT; *cs++ = MI_USER_INTERRUPT;

4
drivers/gpu/drm/i915/intel_ringbuffer.h
View File

@ -408,14 +408,14 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
} }
static inline u32 * static inline u32 *
gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset) gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
{ {
/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
GEM_BUG_ON(gtt_offset & (1 << 5)); GEM_BUG_ON(gtt_offset & (1 << 5));
/* Offset should be aligned to 8 bytes for both (QW/DW) write types */ /* Offset should be aligned to 8 bytes for both (QW/DW) write types */
GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8)); GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
*cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW | flags;
*cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT; *cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;
*cs++ = 0; *cs++ = 0;
*cs++ = value; *cs++ = value;