net/mlx5e: Move helper functions to a new txrx datapath header
Take datapath helper functions to a new header file en/txrx.h. Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Tariq Toukan
David S. Miller
parent
fc707e59c9
commit
542578c679
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@ -549,12 +549,6 @@ struct mlx5e_icosq {
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struct mlx5e_channel *channel;
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} ____cacheline_aligned_in_smp;
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static inline bool
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mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
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{
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return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc);
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}
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struct mlx5e_wqe_frag_info {
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struct mlx5e_dma_info *di;
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u32 offset;
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@ -1023,102 +1017,6 @@ static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
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MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
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}
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struct mlx5e_swp_spec {
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__be16 l3_proto;
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u8 l4_proto;
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u8 is_tun;
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__be16 tun_l3_proto;
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u8 tun_l4_proto;
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};
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static inline void
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mlx5e_set_eseg_swp(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg,
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struct mlx5e_swp_spec *swp_spec)
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{
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/* SWP offsets are in 2-bytes words */
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eseg->swp_outer_l3_offset = skb_network_offset(skb) / 2;
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if (swp_spec->l3_proto == htons(ETH_P_IPV6))
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eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L3_IPV6;
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if (swp_spec->l4_proto) {
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eseg->swp_outer_l4_offset = skb_transport_offset(skb) / 2;
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if (swp_spec->l4_proto == IPPROTO_UDP)
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eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L4_UDP;
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}
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if (swp_spec->is_tun) {
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eseg->swp_inner_l3_offset = skb_inner_network_offset(skb) / 2;
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if (swp_spec->tun_l3_proto == htons(ETH_P_IPV6))
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eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6;
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} else { /* typically for ipsec when xfrm mode != XFRM_MODE_TUNNEL */
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eseg->swp_inner_l3_offset = skb_network_offset(skb) / 2;
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if (swp_spec->l3_proto == htons(ETH_P_IPV6))
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eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6;
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}
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switch (swp_spec->tun_l4_proto) {
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case IPPROTO_UDP:
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eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L4_UDP;
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/* fall through */
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case IPPROTO_TCP:
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eseg->swp_inner_l4_offset = skb_inner_transport_offset(skb) / 2;
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break;
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}
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}
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static inline void mlx5e_sq_fetch_wqe(struct mlx5e_txqsq *sq,
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struct mlx5e_tx_wqe **wqe,
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u16 *pi)
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{
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struct mlx5_wq_cyc *wq = &sq->wq;
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*pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
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*wqe = mlx5_wq_cyc_get_wqe(wq, *pi);
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memset(*wqe, 0, sizeof(**wqe));
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}
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static inline
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struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
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{
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u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc);
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struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
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struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
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memset(cseg, 0, sizeof(*cseg));
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cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
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cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
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(*pc)++;
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return wqe;
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}
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static inline
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void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
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void __iomem *uar_map,
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struct mlx5_wqe_ctrl_seg *ctrl)
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{
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ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
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/* ensure wqe is visible to device before updating doorbell record */
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dma_wmb();
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*wq->db = cpu_to_be32(pc);
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/* ensure doorbell record is visible to device before ringing the
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* doorbell
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*/
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wmb();
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mlx5_write64((__be32 *)ctrl, uar_map);
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}
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static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
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{
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struct mlx5_core_cq *mcq;
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mcq = &cq->mcq;
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mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
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}
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extern const struct ethtool_ops mlx5e_ethtool_ops;
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#ifdef CONFIG_MLX5_CORE_EN_DCB
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extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
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@ -0,0 +1,163 @@
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/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/* Copyright (c) 2019 Mellanox Technologies. */
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#ifndef __MLX5_EN_TXRX_H___
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#define __MLX5_EN_TXRX_H___
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#include "en.h"
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#define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start))
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static inline bool
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mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
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{
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return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc);
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}
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static inline void mlx5e_sq_fetch_wqe(struct mlx5e_txqsq *sq,
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struct mlx5e_tx_wqe **wqe,
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u16 *pi)
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{
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struct mlx5_wq_cyc *wq = &sq->wq;
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*pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
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*wqe = mlx5_wq_cyc_get_wqe(wq, *pi);
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memset(*wqe, 0, sizeof(**wqe));
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}
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static inline struct mlx5e_tx_wqe *
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mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
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{
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u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc);
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struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
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struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
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memset(cseg, 0, sizeof(*cseg));
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cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
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cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
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(*pc)++;
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return wqe;
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}
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static inline void
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mlx5e_fill_sq_frag_edge(struct mlx5e_txqsq *sq, struct mlx5_wq_cyc *wq,
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u16 pi, u16 nnops)
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{
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struct mlx5e_tx_wqe_info *edge_wi, *wi = &sq->db.wqe_info[pi];
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edge_wi = wi + nnops;
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/* fill sq frag edge with nops to avoid wqe wrapping two pages */
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for (; wi < edge_wi; wi++) {
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wi->skb = NULL;
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wi->num_wqebbs = 1;
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mlx5e_post_nop(wq, sq->sqn, &sq->pc);
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}
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sq->stats->nop += nnops;
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}
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static inline void
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mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, void __iomem *uar_map,
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struct mlx5_wqe_ctrl_seg *ctrl)
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{
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ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
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/* ensure wqe is visible to device before updating doorbell record */
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dma_wmb();
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*wq->db = cpu_to_be32(pc);
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/* ensure doorbell record is visible to device before ringing the
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* doorbell
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*/
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wmb();
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mlx5_write64((__be32 *)ctrl, uar_map);
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}
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static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
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{
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struct mlx5_core_cq *mcq;
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mcq = &cq->mcq;
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mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
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}
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static inline struct mlx5e_sq_dma *
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mlx5e_dma_get(struct mlx5e_txqsq *sq, u32 i)
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{
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return &sq->db.dma_fifo[i & sq->dma_fifo_mask];
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}
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static inline void
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mlx5e_dma_push(struct mlx5e_txqsq *sq, dma_addr_t addr, u32 size,
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enum mlx5e_dma_map_type map_type)
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{
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struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, sq->dma_fifo_pc++);
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dma->addr = addr;
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dma->size = size;
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dma->type = map_type;
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}
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static inline void
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mlx5e_tx_dma_unmap(struct device *pdev, struct mlx5e_sq_dma *dma)
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{
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switch (dma->type) {
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case MLX5E_DMA_MAP_SINGLE:
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dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
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break;
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case MLX5E_DMA_MAP_PAGE:
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dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
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break;
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default:
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WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
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}
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}
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/* SW parser related functions */
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struct mlx5e_swp_spec {
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__be16 l3_proto;
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u8 l4_proto;
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u8 is_tun;
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__be16 tun_l3_proto;
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u8 tun_l4_proto;
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};
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static inline void
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mlx5e_set_eseg_swp(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg,
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struct mlx5e_swp_spec *swp_spec)
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{
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/* SWP offsets are in 2-bytes words */
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eseg->swp_outer_l3_offset = skb_network_offset(skb) / 2;
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if (swp_spec->l3_proto == htons(ETH_P_IPV6))
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eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L3_IPV6;
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if (swp_spec->l4_proto) {
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eseg->swp_outer_l4_offset = skb_transport_offset(skb) / 2;
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if (swp_spec->l4_proto == IPPROTO_UDP)
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eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L4_UDP;
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}
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if (swp_spec->is_tun) {
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eseg->swp_inner_l3_offset = skb_inner_network_offset(skb) / 2;
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if (swp_spec->tun_l3_proto == htons(ETH_P_IPV6))
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eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6;
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} else { /* typically for ipsec when xfrm mode != XFRM_MODE_TUNNEL */
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eseg->swp_inner_l3_offset = skb_network_offset(skb) / 2;
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if (swp_spec->l3_proto == htons(ETH_P_IPV6))
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eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6;
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}
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switch (swp_spec->tun_l4_proto) {
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case IPPROTO_UDP:
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eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L4_UDP;
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/* fall through */
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case IPPROTO_TCP:
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eseg->swp_inner_l4_offset = skb_inner_transport_offset(skb) / 2;
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break;
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}
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}
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#endif
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@ -33,6 +33,7 @@
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#define __MLX5_EN_XDP_H__
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#include "en.h"
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#include "en/txrx.h"
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#define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
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#define MLX5E_XDP_TX_EMPTY_DS_COUNT \
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@ -39,6 +39,7 @@
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#include "en_accel/ipsec_rxtx.h"
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#include "en_accel/tls_rxtx.h"
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#include "en.h"
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#include "en/txrx.h"
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#if IS_ENABLED(CONFIG_GENEVE)
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static inline bool mlx5_geneve_tx_allowed(struct mlx5_core_dev *mdev)
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@ -39,6 +39,7 @@
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#include <linux/skbuff.h>
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#include <net/xfrm.h>
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#include "en.h"
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#include "en/txrx.h"
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struct sk_buff *mlx5e_ipsec_handle_rx_skb(struct net_device *netdev,
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struct sk_buff *skb, u32 *cqe_bcnt);
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@ -38,6 +38,7 @@
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#include <linux/skbuff.h>
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#include "en.h"
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#include "en/txrx.h"
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struct sk_buff *mlx5e_tls_handle_tx_skb(struct net_device *netdev,
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struct mlx5e_txqsq *sq,
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@ -41,6 +41,7 @@
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#include <net/xdp_sock.h>
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#include "eswitch.h"
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#include "en.h"
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#include "en/txrx.h"
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#include "en_tc.h"
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#include "en_rep.h"
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#include "en_accel/ipsec.h"
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@ -62,6 +63,7 @@
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#include "en/xsk/rx.h"
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#include "en/xsk/tx.h"
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bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
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{
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bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
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@ -35,6 +35,7 @@
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#include <net/geneve.h>
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#include <net/dsfield.h>
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#include "en.h"
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#include "en/txrx.h"
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#include "ipoib/ipoib.h"
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#include "en_accel/en_accel.h"
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#include "lib/clock.h"
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@ -52,38 +53,6 @@
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MLX5E_SQ_NOPS_ROOM)
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#endif
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static inline void mlx5e_tx_dma_unmap(struct device *pdev,
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struct mlx5e_sq_dma *dma)
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{
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switch (dma->type) {
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case MLX5E_DMA_MAP_SINGLE:
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dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
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break;
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case MLX5E_DMA_MAP_PAGE:
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dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
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break;
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default:
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WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
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}
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}
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static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_txqsq *sq, u32 i)
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{
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return &sq->db.dma_fifo[i & sq->dma_fifo_mask];
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}
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static inline void mlx5e_dma_push(struct mlx5e_txqsq *sq,
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dma_addr_t addr,
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u32 size,
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enum mlx5e_dma_map_type map_type)
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{
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struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, sq->dma_fifo_pc++);
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dma->addr = addr;
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dma->size = size;
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dma->type = map_type;
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}
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static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
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{
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int i;
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@ -277,23 +246,6 @@ dma_unmap_wqe_err:
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return -ENOMEM;
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}
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static inline void mlx5e_fill_sq_frag_edge(struct mlx5e_txqsq *sq,
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struct mlx5_wq_cyc *wq,
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u16 pi, u16 nnops)
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{
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struct mlx5e_tx_wqe_info *edge_wi, *wi = &sq->db.wqe_info[pi];
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edge_wi = wi + nnops;
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/* fill sq frag edge with nops to avoid wqe wrapping two pages */
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for (; wi < edge_wi; wi++) {
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wi->skb = NULL;
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wi->num_wqebbs = 1;
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mlx5e_post_nop(wq, sq->sqn, &sq->pc);
|
||||
}
|
||||
sq->stats->nop += nnops;
|
||||
}
|
||||
|
||||
static inline void
|
||||
mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
|
||||
u8 opcode, u16 ds_cnt, u8 num_wqebbs, u32 num_bytes, u8 num_dma,
|
||||
|
|
@ -326,8 +278,6 @@ mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
|
|||
mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
|
||||
}
|
||||
|
||||
#define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start))
|
||||
|
||||
netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
|
||||
struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue