ixgbe: Add support for maximum headroom when using build_skb
This patch increases the headroom allocated when using build_skb on a system with 4K pages. Specifically the breakdown of headroom versus cache size is as follows: L1 Cache Size Headroom 64 192 64, NET_IP_ALIGN == 2 194 128 128 128, NET_IP_ALIGN == 2 130 256 512 256, NET_IP_ALIGN == 2 258 I stopped at supporting only a cache line size of 256 as that was the largest cache size I could find supported in the kernel. With this we are guaranteeing at least 128 bytes of headroom to spare in the frame. This should be enough for us to insert a couple of IPv6 headers if needed which is likely enough room for anything XDP should need. I'm leaving the padding for systems with pages larger than 4K unmodified for now. XDP currently isn't really setup to work on those types of systems so we can cross that bridge when we get there. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -86,17 +86,62 @@
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/* Supported Rx Buffer Sizes */
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#define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
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#define IXGBE_RXBUFFER_1536 1536
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#define IXGBE_RXBUFFER_2K 2048
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#define IXGBE_RXBUFFER_3K 3072
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#define IXGBE_RXBUFFER_4K 4096
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#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
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#define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
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/* Attempt to maximize the headroom available for incoming frames. We
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* use a 2K buffer for receives and need 1536/1534 to store the data for
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* the frame. This leaves us with 512 bytes of room. From that we need
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* to deduct the space needed for the shared info and the padding needed
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* to IP align the frame.
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*
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* Note: For cache line sizes 256 or larger this value is going to end
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* up negative. In these cases we should fall back to the 3K
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* buffers.
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*/
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#if (PAGE_SIZE < 8192)
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#define IXGBE_MAX_FRAME_BUILD_SKB \
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(SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K) - IXGBE_SKB_PAD)
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#define IXGBE_MAX_2K_FRAME_BUILD_SKB (IXGBE_RXBUFFER_1536 - NET_IP_ALIGN)
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#define IXGBE_2K_TOO_SMALL_WITH_PADDING \
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((NET_SKB_PAD + IXGBE_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IXGBE_RXBUFFER_2K))
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static inline int ixgbe_compute_pad(int rx_buf_len)
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{
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int page_size, pad_size;
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page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
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pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len;
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return pad_size;
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}
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static inline int ixgbe_skb_pad(void)
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{
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int rx_buf_len;
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/* If a 2K buffer cannot handle a standard Ethernet frame then
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* optimize padding for a 3K buffer instead of a 1.5K buffer.
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*
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* For a 3K buffer we need to add enough padding to allow for
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* tailroom due to NET_IP_ALIGN possibly shifting us out of
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* cache-line alignment.
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*/
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if (IXGBE_2K_TOO_SMALL_WITH_PADDING)
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rx_buf_len = IXGBE_RXBUFFER_3K + SKB_DATA_ALIGN(NET_IP_ALIGN);
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else
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rx_buf_len = IXGBE_RXBUFFER_1536;
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/* if needed make room for NET_IP_ALIGN */
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rx_buf_len -= NET_IP_ALIGN;
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return ixgbe_compute_pad(rx_buf_len);
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}
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#define IXGBE_SKB_PAD ixgbe_skb_pad()
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#else
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#define IXGBE_MAX_FRAME_BUILD_SKB IXGBE_RXBUFFER_2K
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#define IXGBE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
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#endif
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/*
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@ -361,7 +406,7 @@ static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
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return IXGBE_RXBUFFER_3K;
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#if (PAGE_SIZE < 8192)
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if (ring_uses_build_skb(ring))
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return IXGBE_MAX_FRAME_BUILD_SKB;
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return IXGBE_MAX_2K_FRAME_BUILD_SKB;
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#endif
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return IXGBE_RXBUFFER_2K;
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}
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@ -3813,7 +3813,7 @@ void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
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/* Limit the maximum frame size so we don't overrun the skb */
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if (ring_uses_build_skb(ring) &&
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!test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
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rxdctl |= IXGBE_MAX_FRAME_BUILD_SKB |
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rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB |
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IXGBE_RXDCTL_RLPML_EN;
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#endif
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}
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@ -3983,8 +3983,8 @@ static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
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if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
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set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
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if ((max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)) ||
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(max_frame > IXGBE_MAX_FRAME_BUILD_SKB))
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if (IXGBE_2K_TOO_SMALL_WITH_PADDING ||
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(max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
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set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
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#endif
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}
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